Category Archives: Device Architecture

Watlow, a designer and manufacturer of complete thermal systems, announced that it has acquired Yarbrough Solutions Worldwide of Austin, Texas. Terms of the transaction were not disclosed.

Yarbrough is a semiconductor equipment solutions provider that services semiconductor fabrication companies globally by developing, installing and servicing high-performance solutions at its customer’s fabrication plants. In performing these services, Yarbrough has long relied upon a myriad of Watlow product offerings such as electric heaters, temperature sensors, temperature controllers and power controllers.

“Yarbrough is a known leader in providing innovative thermal system solutions to semiconductor equipment end users,” said Rob Gilmore, vice president and general manager of Watlow’s semiconductor business unit. “Adding Yarbrough’s know-how and expertise to Watlow’s world-class suite of thermal system capabilities enhances our ability to serve customers through the entire semiconductor fabrication process, from the tool to the scrubber, to ensure thermal optimization of the complete system.”

“This acquisition enables both parties to provide even more value to our semiconductor equipment customers,” said Pat Swayze, vice president of Yarbrough. “We are very excited about Watlow’s long-term vision and we look forward to contributing to the company’s future growth.”

A key element of the acquisition is a South Korean joint venture, which enhances Watlow’s presence in the region. This joint venture between Watlow and its partner, Global Standard Technology Co., Ltd., an established semiconductor business, will be named Watlow Pacific Inc.

Watlow has experienced significant recent growth and aspires to be the share leader in all of its core markets. According to Peter Desloge, Watlow’s president, chief executive officer and chairman, “Watlow is committed to the success of its customers through product and technology leadership, and this is one of the many reasons why the world’s leading companies begin with Watlow for their thermal needs. The Yarbrough acquisition is a continuation of Watlow’s strategy to combine organic investments and acquisitions to achieve consistent, sustainable long-term growth. This acquisition enhances our thermal control capabilities and our ability to create value and deliver a competitive advantage to our customers. We are very excited to welcome Yarbrough to the Watlow team.”

North America-based manufacturers of semiconductor equipment posted $2.36 billion in billings worldwide in July 2018 (three-month average basis), according to the July Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 4.9 percent lower than the final June 2018 level of $2.48 billion, and is 4.1 percent higher than the July 2017 billings level of $2.27 billion.

“Global billings declined for the second month in a row, indicative of customer push-outs,” said Ajit Manocha, president and CEO of SEMI. “We expect the industry to weather this soft patch and end the year overall with strong growth.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg.)
Year-Over-Year
February 2018
$2,417.8
22.5%
March 2018
$2,431.8
16.9%
April 2018
$2,689.9
25.9%
May 2018
$2,702.3
8.1%
June 2018 (final)
$2,484.3
8.0%
July 2018 (prelim)
$2,363.1
4.1%

Source: SEMI (www.semi.org), August 2018

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

A new study by scientists at the National Institute of Standards and Technology (NIST) has uncovered a source of error in an industry-standard calibration method that could lead microchip manufacturers to lose a million dollars or more in a single fabrication run. The problem is expected to become progressively more acute as chipmakers pack ever more features into ever smaller space.

The error occurs when measuring very small flows of exotic gas mixtures. Small gas flows occur during chemical vapor deposition (CVD), a process that occurs inside a vacuum chamber when ultra-rarefied gases flow across a silicon wafer to deposit a solid film. CVD is widely used to fabricate many kinds of high-performance microchips containing as many as several billion transistors. CVD builds up complex 3D structures by depositing successive layers of atoms or molecules; some layers are only a few atoms thick. A complementary process called plasma etching also uses small flows of exotic gases to produce tiny features on the surface of semiconducting materials by removing small amounts of silicon.

The exact amount of gas injected into the chamber is critically important to these processes and is regulated by a device called a mass flow controller (MFC). MFCs must be highly accurate to ensure that the deposited layers have the required dimensions. The potential impact is large because chips with incorrect layer depths must be discarded.

“Flow inaccuracies cause nonuniformities in critical features in wafers, directly causing yield reduction,” said Mohamed Saleem, Chief Technology Officer at Brooks Instrument, a U.S. company that manufactures MFCs among other precision measurement devices. “Factoring in the cost of running cleanrooms, the loss on a batch of wafers scrapped due to flow irregularities can run around $500,000 to $1,000,000. Add to that cost the process tool downtime required for troubleshooting, and it becomes prohibitively expensive.”

Modern nanofabrication facilities cost several billion dollars each, and it is generally not cost-effective for a company to constantly fine tune CVD and plasma etching. Instead, the facilities rely on accurate gas flows controlled by MFCs. Typically, MFCs are calibrated using the “rate of rise” (RoR) method, which makes a series of pressure and temperature measurements over time as gas fills a collection tank through the MFC.

“Concerns about the accuracy of that technique came to our attention recently when a major manufacturer of chip-fabrication equipment found that they were getting inconsistent results for flow rate from their instruments when they were calibrated on different RoR systems,” said John Wright of NIST’s Fluid Metrology Group, whose members conducted the error analysis.

Wright was particularly interested because for many years he had seen that RoR readings didn’t agree with results obtained with NIST’s “gold standard” pressure/volume/temperature/time system. He and colleagues developed a mathematical model of the RoR process and conducted detailed experiments. The conclusion: conventional RoR flow measurements can have significant errors because of erroneous temperature values. “The gas is heated by flow work as it is compressed in the collection tank, but that is not easily accounted for: it is difficult to measure the temperature of nearly stationary gas.”

Wright and colleagues found that without corrections for these temperature errors, RoR readings can be off by as much as 1 percent, and perhaps considerably more. That might not seem like a lot, but low uncertainty is critical to attaining uniformity and quality in the chip manufacturing process. And the challenge is growing. Current low-end flow rates in the semiconductor industry are in the range of one standard cubic centimeter (1 sccm)–about the volume of a sugar cube–per minute, but they will soon shrink by a factor of 10 to 0.1 sccm.

Precise flow measurement is a particularly serious concern for manufacturing processes that use etching of deposited layers to form trench-like features. In that case, the MFC is often open for no more than a few seconds.

“A tiny amount of variation in the flow rate has a profound effect on the etch rate and critical dimensions of the structures” in very large-scale integrated circuits, said Iqbal Shareef of Lam Research, a company headquartered in California that provides precision fabrication equipment to microchip manufacturers.

“So, we are extremely concerned about flow rates being accurate and consistent from chamber to chamber and wafer to wafer,” Shareef said. “Our industry is already headed toward very small flow rates.”

“We are talking about wafer uniformity today on the nanometer and even subnanometer scale,” Shareef said.

That’s very small. But it’s what the complexity of three-dimensional chip manufacturing increasingly demands. Not so long ago, “a 3D integrated circuit used to have four layers of metals,” said William White, Director of Advanced Technology at HORIBA Instruments Incorporated, a global firm that provides analytical and measurement systems. “Now companies are regularly going to 32 layers and sometimes to 64. Just this year I heard about 128.” And some of those chips have as many as 3,000 process steps.

“Each 300 mm wafer can cost up to $400, and contains 281 dies for a die size of 250 to 300 mm2,” Brooks’ Saleem said. “Each die in today’s high-end integrated circuits consists of about three to four billion transistors. Each wafer goes through 1 or 2 months of processing that includes multiple runs of separate individual processes,” including chemical vapor deposition, etch, lithography and ion implantation. All those processes use expensive chemicals and gases.

Many companies are already re-examining their practices in light of the NIST publication, which provides needed theoretical explanations for the source of RoR flow measurement errors. The theory guides designers of RoR collection tanks and demonstrates easy-to-apply correction methods. RoR theory shows that different temperature errors will occur for the different gases used in CVD processes. The NIST publication also provides a model uncertainty analysis that others can use to know what level of agreement to expect between MFCs calibrated on different RoR systems.

“NIST serves as a reliable reference for knowledge and measurement where industry can assess agreement between their systems,” Wright said. “As manufacturers’ measurement needs push to ever lower flows, so will NIST calibration standards.”

Global semiconductor industry revenue grew 4.4 percent, quarter over quarter, in the second quarter of 2018, reaching a record $120.8 billion. Semiconductor growth occurred in all application markets and world regions, according to IHS Markit (Nasdaq: INFO).

“The explosive growth in enterprise and storage drove the market to new heights in the second quarter,” said Ron Ellwanger, senior analyst and component landscape tool manager, IHS Markit. “This growth contributed to record application revenue in data processing and wired communication markets as well as in the microcomponent and memory categories.”

Due to the ongoing growth in the enterprise and storage markets, sequential microcomponent sales grew 6.5 percent in the second quarter, while memory semiconductor revenue increased 6.4 percent. “Broadcom Limited experienced exceptional growth in its wired communication division, due to increased cloud and data-center demand,” Ellwanger said.

Memory component revenue continued to rise in the second quarter, compared to the previous quarter, reaching $42.0 billion dollars. “This is the ninth consecutive quarter of rising revenue from memory components, and growth in the second quarter of 2018 was driven by higher density in enterprise and storage,” Ellwanger said. “This latest uptick comes at a time of softening prices for NAND flash memory. However, more attractive pricing for NAND memory is pushing SSD demand and revenue higher.”

Semiconductor market share

Samsung Electronics continued to lead the overall semiconductor industry in the second quarter with 15.9 percent of the market, followed by Intel at 13.9 percent and SK Hynix at 7.9 percent. Quarter-over-quarter market shares were relatively flat, with no change in the top-three ranking. SK Hynix achieved the highest growth rate and record quarterly sales among the top three companies, recording 16.4 percent growth in the second quarter.

Integrated Device Technology, Inc. (IDT) (NASDAQ :IDTI ) announced today a strategic partnership with Steradian Semiconductor Pvt. Ltd. to deliver ultra-high resolution 4D mmWave imaging RADAR for emerging industrial, security, medical, and autonomous vehicle markets.

Steradian Semiconductor is a fabless semiconductor company based out of Bangalore, India. Steradian is founded by industry experts with decades of experience in designing cellular/RF and microwave transceiver ICs. Their unique IP has enabled IDT to offer highly differentiated “SenseVerse” series of RADAR transceiver ICs to our customers.

The IDT® SenseVerse SVR4410 IC is a multi-channel high resolution MIMO RADAR device that operates in the 76-81 GHz frequency band offering superior interference performance and the highest number of channels per device in the industry. With integrated beamforming and support for multi-device aggregation, the SVR4410 provides best-in-class angular resolution, range, and power consumption in a very small form factor. The two companies are collaborating on a series of roadmap ICs with increasing levels of integration and enable customers’ adoption by means of providing radar modules with integrated antennas, SVR transceiver ICs, radar processing IC and DSP algorithms.

“IDT’s SenseVerse RADAR family will add new dimension to sensing and vision, causing a disruptive change in Industry 4.0 and similar end markets needing high resolution solutions,” stated Sailesh Chittipeddi, executive vice president, global operations and chief technology officer at IDT. “IDT’s novel imaging RADAR architecture based on mmWave technology will be key to reliable and autonomous operation in various climatic conditions and continues IDT’s tradition of delivering high value-added solutions for its customers.”

“IDT’s SenseVerse RADAR family offers all weather high resolution sensing and will enhance and complement human and computer vision,” said Gireesh Rajendran, CEO of Steradian Semiconductor. “IDT’s SVR4410 and roadmap ICs together with Steradian’s RF expertise will offer exceptional value to a wide variety of application spaces.”

IDT’s SenseVerse RADAR products are currently sampling at selected customers.

Semtech Corporation (Nasdaq: SMTC), a supplier of high performance analog and mixed-signal semiconductors and advanced algorithms, announced that EasyLinkin, a high-tech enterprise specializing in the research and development of low power wide area network (LPWAN) technologies, has incorporated Semtech’s LoRa® devices and wireless radio frequency technology (LoRa Technology) into its IoT smart metering solutions to improve facility management.

LoRa-enabled smart meters from EasyLinkin monitor utility usage rates in real-time to provide facilities more visibility to reduce operating costs. EasyLinkin’s LoRa-based products are easy to install on existing meters and are currently being deployed across China in both public and private LoRaWAN™ networks. Utility companies are able to monitor utility usage in real-time to reduce operational costs and conserve natural resources.

“Our customers are able to analyze their usage through real-time data collected by our smart metering solutions to reduce operational costs,” said Kun Xu, Co-Founder & Executive President at EasyLinkin. “This was enabled and would not be possible without Semtech’s LoRa Technology, which provides the ideal IoT solution for utility monitoring and management. The easy deployment and flexibility of LoRa Technology enables consistent data transmission in either a private or public network.”

“With an increased emphasis on sustainability, there’s an absolute need for IoT solutions, like Semtech’s LoRa Technology, to solve real-world environmental challenges,” said Vivek Mohan, Director of IoT, Semtech’s Wireless and Sensing Products Group. “Integrating LoRa Technology into EasyLinkin’s metering devices provides an IoT solution that reduces operational costs like maintenance and allows an inside look into utility consumption, letting consumers change their usage accordingly.”

About Semtech’s LoRa® Devices and Wireless RF Technology

Semtech’s LoRa devices and wireless radio frequency technology is a widely adopted long-range, low-power solution for IoT that gives telecom companies, IoT application makers and system integrators the feature set necessary to deploy low-cost, interoperable IoT networks, gateways, sensors, module products, and IoT services worldwide. IoT networks based on the LoRaWAN™ specification have been deployed in over 100 countries and Semtech is a founding member of the LoRa Alliance™, the fastest growing IoT Alliance for Low Power Wide Area Network applications. To learn more about how LoRa enables IoT, visit Semtech’s LoRa site and join the LoRa Community to access free training as well as an online industry catalog showcasing the products you need for building your ideal IoT application.

A team of researchers led by the University of Minnesota has developed a new material that could potentially improve the efficiency of computer processing and memory. The researchers have filed a patent on the material with support from the Semiconductor Research Corporation, and people in the semiconductor industry have already requested samples of the material.

The findings are published in Nature Materials, a peer-reviewed scientific journal published by Nature Publishing Group.

This cross-sectional transmission electron microscope image shows a sample used for the charge-to-spin conversion experiment. The nano-sized grains of less than 6 nanometers in the sputtered topological insulator layer created new physical properties for the material that changed the behavior of the electrons in the material. Credit: Wang Group, University of Minnesota

“We used a quantum material that has attracted a lot of attention by the semiconductor industry in the past few years, but created it in unique way that resulted in a material with new physical and spin-electronic properties that could greatly improve computing and memory efficiency,” said lead researcher Jian-Ping Wang, a University of Minnesota Distinguished McKnight Professor and Robert F. Hartmann Chair in electrical engineering.

The new material is in a class of materials called “topological insulators,” which have been studied recently by physics and materials research communities and the semiconductor industry because of their unique spin-electronic transport and magnetic properties. Topological insulators are usually created using a single crystal growth process. Another common fabrication technique uses a process called Molecular Beam Epitaxy in which crystals are grown in a thin film. Both of these techniques cannot be easily scaled up for use in the semiconductor industry.

In this study, researchers started with bismuth selenide (Bi2Se3), a compound of bismuth and selenium. They then used a thin film deposition technique called “sputtering,” which is driven by the momentum exchange between the ions and atoms in the target materials due to collisions. While the sputtering technique is common in the semiconductor industry, this is the first time it has been used to create a topological insulator material that could be scaled up for semiconductor and magnetic industry applications.

However, the fact that the sputtering technique worked was not the most surprising part of the experiment. The nano-sized grains of less than 6 nanometers in the sputtered topological insulator layer created new physical properties for the material that changed the behavior of the electrons in the material. After testing the new material, the researchers found it to be 18 times more efficient in computing processing and memory compared to current materials.

“As the size of the grains decreased, we experienced what we call ‘quantum confinement’ in which the electrons in the material act differently giving us more control over the electron behavior,” said study co-author Tony Low, a University of Minnesota assistant professor of electrical and computer engineering.

Researchers studied the material using the University of Minnesota’s unique high-resolution transmission electron microscopy (TEM), a microscopy technique in which a beam of electrons is transmitted through a specimen to form an image.

“Using our advanced aberration-corrected scanning TEM we managed to identify those nano-sized grains and their interfaces in the film,” said Andre Mkhoyan, a University of Minnesota associate professor of chemical engineering and materials science and electron microscopy expert.

Researchers say this is only the beginning and that this discovery could open the door to more advances in the semiconductor industry as well as related industries, such as magnetic random access memory (MRAM) technology.

“With the new physics of these materials could come many new applications,” said Mahendra DC (Dangi Chhetri), first author of the paper and a physics Ph.D. student in Professor Wang’s lab.

Wang agrees that this cutting-edge research could make a big impact.

“Using the sputtering process to fabricate a quantum material like a bismuth-selenide-based topological insulator is against the intuitive instincts of all researchers in the field and actually is not supported by any existing theory,” Wang said. “Four years ago, with a strong support from Semiconductor Research Corporation and the Defense Advanced Research Projects Agency, we started with a big idea to search for a practical pathway to grow and apply the topological insulator material for future computing and memory devices. Our surprising experimental discovery led to a new theory for topological insulator materials.

“Research is all about being patient and collaborating with team members. This time there was a big pay off,” Wang said.

SiFive, a provider of commercial RISC-V processor IP, today announced that ASIC Design Services, a design house, IP provider, and a distributor for FPGA and EDA software, has joined the DesignShare ecosystem. Through this partnership, ASIC Design Services will provide its Core Deep Learning (CDL) technology that accelerates Convolutional Neural Networks (CNNs) on power-constrained embedded hardware platforms.

ASIC Design Services’ CDL technology optimizes its CNN accelerator FPGA core for performance, logic resources, and low power – making CDL suitable for IoT edge and node applications. The CDL Coldbrew software stack performs quantization and compression of CNNs, design space exploration, and generates a solution optimized for performance, resources, and low power. Coldbrew is built on the Caffe deep learning framework, and provides a simple user interface to bridge the gap between high-level CNN specification and FPGA design.

“We are excited about the increased performance and energy efficiency offered by FPGAs,” said Tony Dal Maso, CEO of ASIC Design Services. “Today, we can achieve 100 Gops/s/Watt on a low-power FPGA solution. By partnering with SiFive we enable the global community of embedded designers to accelerate deep learning solutions on embedded platforms.”

The availability of ASIC Design Services’ CDL IP through the DesignShare program shortens the time to market and removes common barriers to entry that have traditionally prevented smaller companies from developing custom silicon. Companies like SiFive, ASIC Design Services and other DesignShare partners provide low- or no-cost IP to emerging companies, minimizing the upfront engineering costs needed to bring a custom chip from design to realization.

“Adding artificial intelligence and neural networks to edge devices is increasingly in demand,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “With ASIC Design Services addition to the DesignShare ecosystem, we continue to expand the range of IP available to designers looking to bring prototype devices to life.”

Since DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from complete ASIC solutions and trace technology to embedded memory and precision PLL. For more information on DesignShare and to see the complete list of available technologies, visit www.sifive.com/designshare.

MRSI Systems (Mycronic Group), is expanding its high speed MRSI-HVM3 die bonder platform with the launch of the MRSI-HVM3P to offer configurations for active optical cable (AOC), gold-box packaging, and other applications in addition to chip-on-carrier (CoC).

This expansion is in response to our customer’s request to take advantage of the field-proven performance of the flexible high speed MRSI-HVM3 platform, for their other essential packaging applications in photonics manufacturing which are high volume and high mix by nature.

The new MRSI-HVM3P is the first major extension to the HVM3 family, equipped with inline conveyor for single fixture or multiple cassette inputs that can automatically transport large forms of carriers of the dies. This configuration is targeted at AOC or similar die-to-printed circuit board (PCB) applications, gold-box packaging, and CoC in fixture. The processes include eutectic, epoxy stamping, UV epoxy dispensing, and in-situ UV curing.

“With these extensions to our successful HVM3 platform, MRSI Systems is now able to offer flexible high volume die bonding solutions, not just for CoC, but also for PCB and box levels of packaging to our customers in photonics, sensors and other advanced technology fields,” said Dr. Yi Qian, Vice President of Product Management of MRSI Systems. “This is another demonstration of MRSI’s commitment to provide critical solutions promptly in response to our customers’ needs,” concluded Mr. Michael Chalsen, President of MRSI Systems.

Both MRSI-HVM3 and MRSI-HVM3P now carry the following options inherited from our long proven MRSI-M3 family:  localized heating, flip-chip bonding, and co-planarity bonding. These options are increasingly critical for new applications such as 400G transceivers and silicon photonics.

The MRSI-HVM3 product family delivers industry-leading speed, future-proof high precision (<3mm), and superior flexibility for true multi-process, multi-chip, high-volume production.

The launch of the MRSI-HVM3P builds on the success of our first configuration launched last year, the MRSI-HVM3 for CoC, Chip-on-Submount (CoS), and Chip-on-Baseplate (CoB) assembly using eutectic and/or epoxy stamping die bonding, which has proved to be the best-in-class die bonder with the leading speed, zero-time tool change between dies, and <3mm accuracy. The superior performance was enabled by dual head, dual stage, integrated “on-the-fly” tool changer, ultrafast eutectic stage, and multi-levels of parallel processing optimizations (see product launch press release August 14, 2017).

MRSI Systems is exhibiting at China International Optoelectronic Expo (CIOE) with our partner CYCAD Century Science and Technology (Booth #1C66) in Shenzhen, September 5-8, 2018 and ECOC (Booth #577) in Rome, Italy, September 24-26, 2018.

Soitec (Euronext Paris), a designer and manufacturer of semiconductor materials, and MBDA, announce the joint acquisition of Dolphin Integration.

Dolphin Integration is an industry recognized provider of semiconductor design, silicon IP and SoC (System-On-Chip) solutions for low power applications. Headquartered in Grenoble, Dolphin Integration was founded in 1985. It currently employs 155 people, including 130 design engineers. For the fiscal year ended March 31th, 2018, the company generated revenues of 17 million Euros.

The joint venture formed by Soitec and MBDA acquires Dolphin Integration, including all employees. The resulting ownership of the joint venture is as follows: Soitec at 60% and MBDA at 40%.

The transaction was authorized today by the Commercial Court of Grenoble. It comes as a prompt and positive outcome of Dolphin Integration insolvency proceedings. The company went into receivership on July 24, 2018.

Soitec and MBDA each provide complementary strategic support to Dolphin Integration.

Soitec brings its engineered substrates expertise and unique low-power design methodology (body biasing) to accelerate Dolphin Integration design activities in low-power electronic devices, where a growing number of critical chips are built on FD-SOI technology. In addition, Soitec will strengthen Dolphin Integration’s position within the entire semiconductor ecosystem, to develop and promote products and services in several strategic markets, including mobile devices and infrastructure, data centers, and space and industrial applications.

MBDA, a strategic customer of Dolphin Integration for defense applications since 2004, strengthens its existing industrial collaboration and long-term commercial pipeline for ASIC (Application Specific Integrated Circuit) and SoC (System on Chip) products. With the support of MBDA, Dolphin Integration will be able to advance its positions in aerospace and defense design.

Soitec and MBDA confident in Dolphin Integration profitable growth.

Soitec and MBDA together committed to a financial investment of around 6 million Euros including the acquisition of most of Dolphin Integration’s assets, the payment of certain liabilities and a significant cash injection to finance Dolphin Integration’s working capital requirements.

Soitec and MBDA are confident in their ability to turnaround the financial position of Dolphin Integration. Dolphin Integration is expected to be fully consolidated into Soitec’s financial statements as of September 2018.

“Dolphin Integration represents a strategic opportunity for Soitec to reinforce a full IP and service offering related to energy efficient solutions for chip design on FD-SOI. This is a major differentiating factor for FD-SOI and a key accelerator of FD-SOI adoption in major market segments,” highlighted Paul Boudre, CEO of Soitec.

“MBDA investment will strengthen the French defense industrial base since it will provide Dolphin Integration with a more stable flow of defense related revenues and a closer technological collaboration that will allow it to enhance the access of its specialized microelectronics offering to the entire French and European defense industry,” said Antoine Bouvier, CEO of MBDA.