Category Archives: Device Architecture

SiFive, a provider of commercial RISC-V processor IP, today announced the first open-source RISC-V-based SoC platform for edge inference applications based on NVIDIA’s Deep Learning Accelerator (NVDLA) technology.

The demo will be shown this week at the Hot Chips conference and consists of NVDLA running on an FPGA connected via ChipLink to SiFive’s HiFive Unleashed board powered by the Freedom U540, the world’s first Linux-capable RISC-V processor. The complete SiFive implementation is well suited for intelligence at the edge, where high-performance with improved power and area profiles are crucial. SiFive’s silicon design capabilities and innovative business model enables a simplified path to building custom silicon on the RISC-V architecture with NVDLA.

NVIDIA open-sourced its leading deep learning accelerator over a year ago to spark the creation of more AI silicon solutions. Open-source architectures such as NVDLA and RISC-V are essential building blocks of innovation for Big Data and AI solutions.

“It is great to see open-source collaborations, where leading technologies such as NVDLA can make the way for more custom silicon to enhance the applications that require inference engines and accelerators,” said Yunsup Lee, co-founder and CTO, SiFive. “This is exactly how companies can extend the reach of their platforms.”

“NVIDIA open sourced its NVDLA architecture to drive the adoption of AI,” said Deepu Talla, vice president and general manager of Autonomous Machines at NVIDIA. “Our collaboration with SiFive enables customized AI silicon solutions for emerging applications and markets where the combination of RISC-V and NVDLA will be very attractive.”

Toshiba Electronic Devices & Storage Corporation (“Toshiba”) has launched a new series of next-generation 650V power MOSFETs that are intended for use in server power supplies in data centers, solar (PV) power conditioners, uninterruptible power systems (UPS) and other industrial applications.

The first device in the DTMOS VI series is the TK040N65Z, a 650V device that supports continuous drain currents (ID) up to 57A and 228A when pulsed (IDP). The new device offers an ultra-low drain-source on-resistance RDS(ON) of 0.04Ω (0.033Ω typ.) which reduces losses in power applications. The enhancement mode device is ideal for use in modern high-speed power supplies, due to the reduced capacitance in the design.

Power supply efficiency is improved as a result of reductions in the key performance index / figure-of-merit (FoM) – RDS(ON) x Qgd. The TK040N65Z shows a 40% improvement in this important metric over the previous DTMOS IV-H device, which represents a significant gain in power supply efficiency in the region of 0.36%[1] – as measured in a 2.5kW PFC circuit.

The new device is housed in an industry-standard TO-247 package, ensuring compatibility with legacy designs as well as suitability for new projects.

Toshiba will continue to expand their product lineup to meet market trends and help improve the efficiency of power supplies and systems.

The new device enters mass production today and shipments begin immediately.

IC Insights released its August Update to the 2018 McClean Report earlier this month.  This Update included a discussion of the top-25 semiconductor suppliers in 1H18 (the top-15 1H18 semiconductor suppliers are covered in this research bulletin) and Part 1 of an extensive analysis of the IC foundry market and its suppliers.

The top-15 worldwide semiconductor (IC and O-S-D—optoelectronic, sensor, and discrete) sales ranking for 1H18 is shown in Figure 1.  It includes seven suppliers headquartered in the U.S., three in Europe, two each in South Korea and Taiwan, and one in Japan.  After announcing in early April 2018 that it had successfully moved its headquarters location from Singapore to the U.S. IC Insights now classifies Broadcom as a U.S. company.

Figure 1

As shown, all but four of the top 15 companies had double-digit year-over-year growth in 1H18. Moreover, seven companies had ≥20% growth, including the five big memory suppliers (Samsung, SK Hynix, Micron, Toshiba/Toshiba Memory, and Western Digital/SanDisk) as well as Nvidia and ST.

The top-15 ranking includes one pure-play foundry (TSMC) and four fabless companies. If TSMC were excluded from the top-15 ranking, U.S.-based Apple would have been ranked in the 15th position. Apple is an anomaly in the top company ranking with regards to major semiconductor suppliers. The company designs and uses its processors only in its own products—there are no sales of the company’s MPUs to other system makers. IC Insights estimates that Apple’s custom ARM-based SoC processors and other custom devices had a “sales value” of $3.5 billion in 1H18.

IC Insights includes foundries in the top-15 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted. With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers. Foundries and fabless companies are identified in the Figure. In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-15 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

In May 2018, Toshiba completed the $18.0 billion sale of its memory IC business to the Bain Capital-led consortium. Toshiba then repurchased a 40.2% share of the business. The Bain consortium goes by the name of BCPE Pangea and the group owns 49.9% of Toshiba Memory Corporation (TMC). Hoya Corp. owns the remaining 9.9% of TMC’s shares. The new owners have plans for an IPO within three years. Bain has said it plans to support the business in pursing M&A targets, including potentially large deals.

As a result of the sale of Toshiba’s memory business, the 2Q18 sales results shown in Figure 1 include the combined sales of the remaining semiconductor products at Toshiba (e.g., Discrete devices and System LSIs) and the new Toshiba Memory’s NAND flash sales. The estimated breakdown of these sales in 2Q18 is shown below:

Toshiba System LSI: $468M
Toshiba Discrete: $315M
Toshiba Memory Corporation: $3,107M
Total Toshiba/Toshiba Memory Corporation 2Q18 Sales: $3,890M

In total, the top-15 semiconductor companies’ sales surged by 24% in 1H18 compared to 1H17, four points higher than the total worldwide semiconductor industry 1H18/1H17 increase of 20%. Amazingly, the Big 3 memory suppliers—Samsung, SK Hynix, and Micron, each registered greater than 35% year-over-year growth in 1H18. Fourteen of the top-15 companies had sales of at least $4.0 billion in 1H18, three companies more than in 1H17. As shown, it took just over $3.7 billion in sales just to make it into the 1H18 top-15 semiconductor supplier list.

Intel was the number one ranked semiconductor supplier in 1Q17 but lost its lead spot to Samsung in 2Q17 as well as in the full-year 2017 ranking, a position it had held since 1993. With the continuation of the strong surge in the DRAM and NAND flash markets over the past year, Samsung went from having only 1% more total semiconductor sales than Intel in 1H17 to having 22% more semiconductor sales than Intel in 1H18!

It is interesting to note that memory devices are forecast to represent 84% of Samsung’s semiconductor sales in 2018, up three points from 81% in 2017 and up 13 points from 71% just two years earlier in 2016. Moreover, the company’s non-memory sales in 2018 are expected to be only $13.5 billion, up 8% from 2017’s non-memory sales level of $12.5 billion. In contrast, Samsung’s memory sales are forecast to be up 31% this year and reach $70.0 billion.

The 64thannual IEEE International Electron Devices Meeting (IEDM), the world’s largest, most influential forum for technologists to unveil breakthroughs and new concepts in transistors and related micro/nanoelectronics devices, will be held December 1-5, 2018 at the Hilton San Francisco Union Square hotel. The late-news submission deadline is September 10.

The IEDM’s tradition of spotlighting more leading work in more areas of the field continues, even as the conference evolves to support the interdisciplinary and continuing educational needs of the scientists, engineers and students whose efforts make possible the expansion of the worldwide electronics industry.

“We live in a time when electronics technology touches more aspects of business and industry than ever before,” said Kirsten Moselund, IEDM 2018 Publicity Chair and Research Staff Member at IBM Research–Zurich. “No matter what their specialty is, attendees will come away from the conference with a deeper understanding of the challenges and opportunities before them.”

“In terms of industrial applications, the evening panel session on EUV will give attendees the opportunity to explore and debate this emerging technology with the very people who are driving it forward,” said Rihito Kuroda, IEDM 2018 Publicity Vice Chair and Associate Professor at Tohoku University. “This is just one way in which the IEDM conference gives people insights into the technologies that will become mainstream in a few years.”

Here are details of some of the talks and events that will take place at this year’s IEDM. The papers to be presented in the technical sessions will be chosen in late September and highlights from them will be forthcoming soon thereafter:

Focus Sessions

  • Quantum Computing – Quantum computing will enable new types of algorithms to tackle problems in areas from materials science to medicine to artificial intelligence. We are still in early stages, facing fundamental questions such as: What is the best way to implement a quantum bit of information? How to connect them together? How to scale to larger systems without being overwhelmed by errors? This session brings together experts at the forefront of quantum computing research. Starting from an applications perspective, attendees will hear about different approaches to address fundamental questions at the device level; the progress achieved so far; and next steps.
    • Application Requirements for Quantum Computing, John Preskill, Caltech
    • Materials and Device Challenges for Near-Term Superconducting Quantum Processors, Jerry Chow, IBM
    • Towards Scalable Silicon Quantum Computing, Maud Vinet, CEA-Leti
    • Silicon Isotope Technology for Quantum Computing, Kohei Itoh, Keio University
    • Qubit Device Integration Using Advanced Semiconductor Manufacturing Process Technology, Ravi Pillarrisetty, Intel
    • Scalable Quantum Computing with Single Dopant Atoms in Silicon, Andrea Morello, Univ. New South Wales
    • Majorana Qubits, Leo Kouwenhoeven, Microsoft
  • Future Technologies Towards Wireless Communications: 5G and Beyond– 5G technology will drastically reduce limitations on accessibility, bandwidth, performance, and latency, but as it triggers fundamentally new applications it also will impose unique hardware requirements. This focus session will set a big picture view and then narrow down to how innovations in CMOS technologies, devices, filters, transceivers and antennas are coming together to enable the 5G platform.
    • Intel 22nm FinFET (22FFL) Process Technology for RF and mmWave Applications and Circuit Design Optimization for FinFET Technology, Hyung-Jin Lee, Intel
    • RFIC/CMOS Technologies for 5G, mmWave and Beyond, Ali Niknejad, UC Berkeley
    • GaN HEMTs for 5G Base Station Applications, Shigeru Nakajima, Sumitomo Electron Devices
    • Highly Integrated mm-Wave Transceivers for Communication Systems,Vadim Issakov, Infineon
    • BAW Filters for 5G Bands, Robert Aigner, Qorvo
    • Reconfigurable Micro/Millimeter-wave Filters, Dimitrios Peroulis, Purdue
  • Challenges for Wide Bandgap Device Adoption in Power Electronics– Wide bandgap (WBG) power devices offer potential savings in both energy and cost. But converters powered by WBG devices require innovation at all levels, entailing changes to system design, circuit architecture, qualification metrics and even market models. Can SiC or GaN push beyond what silicon can possibly achieve? What are the big challenges researchers should answer over the next decade? A team of experts will interpret the landscape and discuss challenges to the widespread adoption of these technologies.
    • GaN and SiC Devices for Automotive Applications, Tetsu Kachi, Nagoya University
    • SiC MOSFET for Mainstream Adoption, Peter Friedrichs, Infineon
    • GaN Power Commercialization with Highest Quality-Highest Reliability 650V HEMTs- Requirements, Successes and Challenges, Primit Parikh, Transphorm
    • The Current Status and Future Prospects of SiC High Voltage Technology, Andrei Mihaila, ABB
    • Barriers to Wide Bandgap Semiconductor Device Adoption in Power Electronics, Isik Kizilyalli, ARPA-E
    • High to Ultra-High Voltage SiC Power Device Technology, Yoshiyuki Yonezawa, AIST
    • Effects of Basal Plane Dislocations on SiC Power Device Reliability, Robert E. Stahlbush, Naval Research Laboratory
  • Interconnects to Enable Continued Technology Scaling –BEOL copper (Cu) interconnects are close to end-of-life as a manufacturing technology, while the increasing complexity of MEOL processes requires novel materials. Also, the end of the Cu roadmap will coincide with significant changes in the dominant transistor architecture, and therefore the interaction between transistor architecture and interconnect will drive future interconnect development. This session provides a holistic perspective of interconnect scaling challenges and solutions. It will address the drivers of future interconnect architectures, the process options likely to be implemented in manufacturing, and how they will be tuned to ensure circuit reliability is maintained.
    • Interconnect Design and Technology Optimization for Conventional and Exotic Nanoscale Devices: A Physical Design Perspective, Naeemi, Georgia Tech
    • Mechanisms of Electromigration Damage in Cu Interconnects, K. Hu, IBM
    • Interconnect Metals Beyond Copper: Reliability Challenges and Opportunities, K. Croes, Imec
    • Microstructure Evolution and Effect on Resistivity for Cu Nano-interconnects and Beyond, Paul Ho, UT Austin
    • Integrating Graphene into Future Generations of BEOL Interconnects,-S. Philip Wong, Stanford
    • Interconnect Trends for Single Digit Nodes, Mehul Naik, Applied Materials

90-Minute Tutorials – Saturday, Dec. 1

A series of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, bridging the gap between textbook-level knowledge and leading-edge current research.

  • Reliability Challenges in Advanced Technologies,Ryan Lu, TSMC
  • STT-MRAM Design and Device Requirements, Shinichiro Shiratake, Toshiba Memory
  • Quantum Computing Primer, Mark B. Ritter, IBM
  • Power Transistors in Integrated BCD Technologies, Hal Edwards, Texas Instruments
  • Design-Technology Co-optimization at RF and mmWave, Bertand Parvais, IMEC
  • Emerging Device Technologies for Neuromorphic Computing, Damien Querlioz, CNRS

Short Courses – Sunday, Dec. 2

Full-day Short Courses will be held, offering the opportunity to learn about important areas and developments, and to network with experts from around the world.

  • It’s All About Memory, Not Logic!, organized by Nirmal Ramaswamy, Micron
  • DRAM: Its Challenging History and Future, Dong Soo Woo, Samsung
  • 3D Flash Memories: Overview of Cell Structures, Operations and Scaling Challenges, Makoto Fujiwara, Toshiba Memory Corporation.
  • Emerging Memories Including Cross-Point, Opportunities and Challenges, Kiran Pangal, Intel
  • Memory Reliability, Qualification and their Relation to System-Level Reliability Strategies, Todd Marquart, Micron
  • Packaging Technology for High Bandwidth Memory, Nick (Namseog) Kim, SK Hynix
  • Processing in Memory (PIM): Performance and Thermal Challenges and Opportunities, Mircea Stan, UVA
  • Scaling Survival Guide in the More-than-Moore Era, organized by Jin Cai, TSMC
  • Extreme-UV Lithography – Principles, Present Status and Outlook,Tony Yen, ASML
  • MOSFET Scaling Knobs (GAA, NCFET…) and Future Alternatives,Witek Maszara, Globalfoundries
  • Overcoming Variation Challenges, Sivakumar Mudanai, Intel
  • Embedded Memory: Present Status and Emerging Architecture and Technology for Future Applications,Eric Wang, TSMC
  • 3D Integration for Density and Functionality,Julien Ryckaert, Imec
  • Advanced Packaging: the Next Frontier for Moore’s “Law,” Subramanian Iyer, UCLA

Plenary Presentations – Monday, Dec. 3

  • Future Computing Hardware for AI, Jeffery Welser, Vice President, IBM Research-Almaden
  • “4th Industrial Revolution and Foundry: Challenges and Opportunities,” Eun Seung Jung, President of Foundry Business, Samsung Electronics
  • The Status, Challenges and Opportunities of 5G, Prof. Gerhard P. Fettweis, TU Dresden

Evening Panel Session – Tuesday evening, Dec. 4

  • EUV: Too Little, Too Late, Too Expensive or the Ultimate Cure-All?,organized by Sanjay Natarajan, Senior VP of Applied Materials. Much progress has been made in EUV patterning technology, and yet manufacturing throughput, masks, pellicles and resists still persist as problems today. The complexity of reliably transferring features at the 7nm node and below using quadruple patterning and 193nm immersion is affecting yield, affecting the cost-per-gate reduction and slowing down Moore’s Law. The industry eagerly awaits EUV, but is it too little, too late and too expensive, or is it the ultimate panacea? A team of world-renowned experts from the leading logic and memory IDMs, foundries and fabless companies will vigorously debate the issue.

Luncheon – Wednesday, Dec. 5

The speakers are yet to be determined, but IEDM will have a new lunch event this year that features industry leaders engaging the audience on the state of the industry, and on careers in device and VLSI technology.

Vendor Exhibition/Poster Sessions

  • A vendor exhibition will be held once again, with special exhibit events in the evenings.
  • This year two poster sessions will be held, one on MRAM technology organized by the IEEE Magnetics Society, the other a student research showcase hosted by the Semiconductor Research Corporation.

Further information about IEDM

For registration and other information, visit www.ieee-iedm.org.

Follow IEDM via social media

About IEEE
IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity. Through its highly cited publications, conferences, technology standards, and professional and educational activities, IEEE is the trusted voice in a wide variety of areas ranging from aerospace systems, computers, and telecommunications to biomedical engineering, electric power, and consumer electronics. Learn more at http://www.ieee.org.

The Trump administration’s consideration of tariffs on Chinese printed circuit assemblies and connected devices would cost the economy $520.8 million and $2.4 billion annually for the 10 percent and 25 percent tariffs, respectively, according to a new study commissioned by the Consumer Technology Association (CTA).

“With the economy thriving under President Trump – we’ve seen remarkably low unemployment and a booming stock market – the administration shouldn’t jeopardize America’s global standing with tariffs,” said Gary Shapiro, CEO and president, CTA. “Foreign governments don’t pay the cost of tariffs, Americans do – and for that reason, U.S. trade policy needs to steer clear of tariffs that act like taxes on American manufacturers and consumers. The danger we face – the unintended consequence – is that tariffs mean Americans will pay more for all the devices they use every day to access the internet.”

The economic impact study shows American shoppers will have to pay between $1.6 billion and $3.2 billion more for connected devices such as gateways, modems, routers, smart speakers, smartwatches and other Bluetooth enabled products. The price of connected devices from China will increase by between 8.5 and 22 percent. And prices for these products from all sources will rise between 3.2 and 6.2 percent.

Similarly, the price of printed circuit assemblies from China –– will increase by between nine and 23 percent, while an alternative supply from U.S. manufacturers will cost two to three percent higher. As a result of higher input costs, totaling an additional $900 million to $1.8 billion, American manufacturers of products that contain printed circuit assemblies will purchase between six and 12 percent less from suppliers overall.

“When our government begins to charge its own companies and people with more taxes in the form of tariffs, we have put in jeopardy not just the American Dream of many small and mid-size businesses, but you put in jeopardy the people that work for them too,” said Win Cramer, CEO, JLab Audio, a California based company and CTA member. “These people support a growing economy, support a growing business and, most importantly, pay taxes. Pre-tariffs, JLab Audio was planning to scale up with new hires and programs to push our company’s growth to another level, but now we’ve put all of that on hold as we need to see how everything shakes out.”

Based on CTA’s most recent U.S. Consumer Technology Sales and Forecasts report, if the administration enacts tariffs of 10 and 25 percent, CTA projects 2019 U.S. unit shipments of connected devices such as fitness trackers, smartwatches, wireless headphones, modems/broadband gateways, wireless earbuds and smart speakers would decline by as much as 12 percent. Also, U.S. shipment revenues for these devices would decrease by as much as 6.5 percent in 2019.

Adesto Technologies (NASDAQ:IOTS), a provider of application-specific semiconductors for the IoT era, announced it will present new research showing the significant potential for Resistive RAM (RRAM) technology in high-reliability applications such as automotive. Adesto Fellow Dr. John Jameson, who led the research team, will share the results at the ESSCIRC-ESSDERC 48th European Solid-State Device Research Conference, being held in Germany on September 4th, 2018.

RRAM has great potential to become a widely used, low-cost and simple embedded non-volatile memory (NVM), as it utilizes simple cell structures and materials which can be integrated into existing manufacturing flows with as little as one additional mask. However, many RRAM technologies to-date have faced integration and reliability challenges. Adesto’s engineers will describe recent innovations that significantly increase the reliability of Adesto’s RRAM technology (trademarked as CBRAM®), making it a promising candidate for high-reliability applications. CBRAM consumes less power, requires fewer processing steps, and operates at lower voltages as compared to conventional embedded flash technologies.

“We’re delighted to share our latest RRAM research with the prestigious technical community at ESSCIRC-ESSDERC,” said Dr. Venkatesh Gopinath, VP of CBRAM and RRAM Technology and Production Development at Adesto. “For the first time, RRAM is being demonstrated as an ideal low-cost, one-mask embedded NVM for high-reliability applications. Adesto was the first company to bring commercial RRAM devices to market, and now our CBRAM technology is production-proven for IoT and other ultra-low power applications. Our continued innovation and advancements will bring the benefits of CBRAM to an even broader range of applications.”

Dr. Jameson will present the Adesto research on Tuesday, September 4th at 15:00 local time.

On the heels of a 37.3% growth in wafer front end (WFE) semiconductor equipment growth in 2017, the market will grow only 10% in 2018 to $62.3 billion, according to the report “The Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts,” recently published by The Information Network, (www.theinformationnet.com) a New Tripoli, PA-based market research company.

For the first six months of 2018, WFE billings were $35.3 billion, meaning billings of $27.0 billion will be registered in the second half of 2018 if the sector as a whole grows 10% in CY 2018.

This means a drop of 24% between 1H 2018 and 2H 2018.

The chart below shows that U.S. equipment companies held a 48.8% share of the total sector in 1H 2018 followed by Japan with a 30.3% share and ROW (primarily Europe) with a 26.9% share. For 2H 2018, the weak Japanese Yen means Japan will have a 29.1% share, but stronger EUV sales by ASML will mean Europe’s share will grow to 28.0%.

The memory market is moving into a period of oversupply: NAND oversupply started six months ago and has resulted in device price drops, while DRAMs will reach an oversupply situation in the next few months. As a result, market leader Samsung Electronics has pushed out purchases. Foundry leader TSMC has reduced its estimate for sales revenue growth in 2018 and its capital expenditure budget.

Automotive electronics are a bright light for the semiconductor industry, as smartphone growth slows, and personal computing growth continues to decline. The expectation is that automotive electronics will become the next big technology market driver. The automotive semiconductor market will exceed the overall industry growth as semiconductor content expands with added features and functionality. The desire to put self-driving vehicles on the road is creating increased interest in innovative automotive solutions as well as increased semiconductor demand. A new research report from Semico Research, Automotive Semiconductors: Accelerating in the Fast Lane, states that the automotive segment of the semiconductor industry will grow to $73 billion by 2023.

“There are a number of challenges in the automotive industry that are unique for the system developers to navigate. Autonomous driving is a critical one,” says Jim Feldhan, President of Semico Research. “Many people feel AI is the key to the success of autonomous driving. Autonomous driving includes the ability to have optical character recognition, i.e. reading signs, distinguishing a sign from a person, and determining if the brakes should be turned on. Security surveillance, computer vision, virtual reality and image processing, real-time diagnosis and corrective solutions and strategic map planning are critical to autonomous driving. Increasing levels of processing are required as these systems become more sophisticated.”

Key findings in the report include:

The TAM market for automotive IP processor royalties will grow to $2.34 billion by 2023.
A fully autonomous vehicle (L5) is expected to require 74GB DRAM and 1TB NAND memory.
Powertrain requires the highest compute function and carries the highest ASP.

Revenue generated from processors in Autonomous Driving Systems will reach $422 million in 2018.
In its recent report, Automotive Semiconductors: Accelerating in the Fast Lane (MP118-18), Semico Research provides a comprehensive review of the current market and future opportunities for the semiconductor industry in the automotive segment. Topics covered in the report include Automotive Trends, Opportunities and Challenges, Manufacturing Technology for Auto ICs, Automotive Forecast, and Semiconductor IP in Automotive. The report is 56 pages long and includes 28 tables and 34 figures.

pSemi Corporation (formerly Peregrine Semiconductor), a Murata company focused on semiconductor integration, introduces the world’s first monolithic, silicon-on-insulator (SOI) Wi-Fi front-end module (FEM)—the PE561221. Ideal for Wi-Fi home gateways, routers and set-top boxes, this high-performance module uses a smart bias circuit to deliver a high linearity signal and excellent long-packet error vector magnitude (EVM) performance. The PE561221 combines the intelligent integration capabilities of pSemi’s SOI technology and Murata’s expertise in Wi-Fi connectivity solutions and advanced packaging. This 2.4 GHz Wi-Fi FEM integrates a low-noise amplifier (LNA), a power amplifier (PA) and two RF switches (SP4T, SP3T). The monolithic die uses a compact 16-pin, 2 x 2 mm LGA package ideal for either stand-alone use or in 4 x 4 MIMO and 8 x 8 MIMO modules.

“The new IEEE 802.11ax standard is utilizing high-order modulation schemes (1024 QAM) with demanding EVM requirements,” says Colin Hunt, vice president of worldwide sales at pSemi. “Traditional process technologies struggle to keep up with both performance and integration requirements, and only SOI can offer the ideal combination of integration and high performance. This new monolithic Wi-Fi module is a great example of the types of technology and product advancements pSemi and Murata can accomplish together.”

The 2.4 GHz Wi-Fi FEM is based on pSemi’s UltraCMOS® technology platform—a patented, advanced form of SOI. With its outstanding RF and microwave properties, SOI is an ideal substrate for integration. When paired with high-volume CMOS manufacturing—the most widely used semiconductor technology—the result is a reliable, repeatable technology platform that offers superior performance compared to other mixed-signal processes. UltraCMOS technology also enables intelligent integration—the unique design ability to integrate RF, digital and analog components on a single die.

Features, Packaging and Availability 

The PE561221 leverages the intelligent integration capabilities of UltraCMOS technology to deliver exceptional performance, low power consumption and high reliability with 2 kV HBM ESD rating. Through advanced analog and digital design techniques, the Wi-Fi FEM delivers excellent long-packet EVM performance with less than 0.1 dB of gain droop while operating across the entire -40°C to 85°C temperature range. At -40 dB EVM (MCS9), the output power is +19 dBm with less than 0.05 dBm droop in power output after a 4 milliseconds packet. The IC delivers best-in-class dynamic error vector magnitude (DEVM) and current consumption without requiring digital pre-distortion (DPD), and it has excellent MCS11 performance for 802.11ax applications.

Volume-production parts and samples of the PE561221 are available from pSemi. For sales information, please contact [email protected].

The PE561221 is the first product in the pSemi Wi-Fi FEM portfolio; the product roadmap includes 5 GHz Wi-Fi FEM solutions.

The American Institute for Manufacturing Integrated Photonics (AIM Photonics), a public-private partnership headquartered in New York State to advance the nation’s photonics manufacturing capabilities, today announced that three National Science Foundation (NSF) funded grants totaling $1.2 million will enable collaborative photonics-centered R&D with the Rochester Institute of Technology (RIT), University of California-San Diego (UCSD), and University of Delaware (UD), respectively.

“AIM Photonics is thrilled to work with leading academic institutions including RIT, UCSD, and UD on these three separate, NSF-funded projects to collaboratively enable photonics-focused devices and capabilities that can allow for the more efficient identification of materials, as well as enhanced processes for manufacturing complex photonic devices and next-generation computing capabilities. We are proud to be the central driver of photonics-based advances that can significantly improve the technologies our society depends on,” said Dr. Michael Liehr, CEO of AIM Photonics.

“Partnering with AIM Photonics provides NSF-funded researchers unique access to world-class manufacturing facilities, stimulating innovation and enabling faculty to span the spectrum from fundamental research breakthroughs to translational advances in integrated photonics devices and circuits that directly impact society,” said Dr. Filbert Bartoli, Director of the Division of Electrical, Communications and Cyber Systems in NSF’s Directorate for Engineering.

Rochester Institute of Technology – AIM Photonics Project

The NSF awarded RIT $423,000 as part of the research project, “PIC: Hybrid Silicon Electronic-Photonic Integrated Neuromorphic Networks,” which will focus on realizing high-performance neural networks that will be integrated onto photonic chips for scalable and efficient architectures that, in tandem with integrated electronics, overcome challenges related to photonic memory and amplification—offering a hybrid, high-bandwidth computing approach for applications to autonomous systems, information networks, cybersecurity, and robotics. To develop these architectures, RIT will work with AIM Photonics to use its leading-edge PIC toolset, located at SUNY Polytechnic Institute in Albany, NY, and the AIM Photonics TAP facility in Rochester, NY—the world’s first 300mm open access PIC Test, Assembly, and Packaging (TAP) facility. The project will take place within RIT’s Future Photon Initiative (FPI) and Center for Human-Aware AI (CHAI).

This research effort will also provide educational opportunities for elementary through high school, undergraduate, and graduate students, and the AIM Photonics Academy will be able to disseminate the project’s findings to further increase understanding of this fast-growing area of research.

“We are excited to partner with AIM Photonics on this research project. The hybrid electronic-photonic neuromorphic chips my Co-PI (Professor Dhireesha Kudithipudi) and I are developing are directly enabled by the state-of-the-art PIC and TAP capabilities of AIM Photonics,” said Project Principal Investigator, Professor Stefan Preble at Rochester Institute of Technology’s Kate Gleason College of Engineering.

University of California-San Diego – AIM Photonics Project 

The NSF awarded UCSD $405,000 for research entitled, “PIC: Mobile in Situ Fourier Transform Spectrometer on a Chip,” which will enable UCSD to rapidly prototype and test miniaturized and mobile platform-embedded optical spectrometers that will excel at chemical identification. The initial design, fabrication, and validation of such a spectrometer on a Si chip have been recently reported in Nature Communications 9:665 (2018). This effort will continue and culminate with full-scale manufacturing runs at AIM Photonics’ foundry at the Albany Nanotech Complex. The integrated chip-scale Fourier transform spectrometer is to be fully CMOS compatible for use in mobile phones and other mobile platforms with potential impacts in areas ranging from environmental management, medicine, and security.

Undergraduate and graduate students at the institution will also be able to gain hands-on training as the research project simultaneously serves as a community outreach tool to inspire students attending middle and high schools.

“Moreover, we are also developing an educational silicon photonics kit through the NSF’s ERC-CIAN (Engineering Research Center for Integrated Access Networks) and in collaboration with Tyndall National Institute at University College Cork (Ireland). The kit will initially be implemented in an undergraduate lab curriculum with the goal to prepare the future task force through hands-on experience in this evolving field,” said Project Principal Investigator, Professor Yeshaiahu Fainman, Cymer Chair in Advanced Optical Technologies and Distinguished Professor at the University of California-San Diego.

University of Delaware – AIM Photonics Project

The NSF awarded UD $360,000 as part of the research project, “PIC: Hybrid Integration of Electro-Optic and Semiconductor Photonic Devices and Circuits with the AIM Photonics Institute.” This effort will allow UD to work with AIM Photonics to leverage the initiative’s expertise and state-of-the-art foundry for the development of new heterogeneous manufacturing processes for photonic devices, using new materials such as Lithium Niobate (LiNbO3), which can then be directly integrated with silicon CMOS systems for photonic devices and chip scale systems.

More specifically, the effort aims to realize high performance RF-photonic devices such as ultra-high frequency modulators (> 100 GHz) that are used in data networks; high-efficiency chip-scale routers for advanced data centers; and high-power phased array antenna photonic feed networks that are compatible with older and next-generation wireless communications; in addition to enabling a number of other wide-ranging commercial applications.

“The heterogeneous integration of LiNbO3 with Silicon Photonics allows for the use of the best properties of both material systems, thereby enabling truly innovative systems for countless emerging applications,” said Project Principal Investigator, Dr. Dennis Prather, Engineering Alumni Professor at the University of Delaware.

AIM Photonics features research, development, and commercialization nodes in Albany, NY, at SUNY Polytechnic Institute, as well as in Rochester, NY, where state-of-the-art equipment and tools are being installed at AIM Photonics’ TAP facility. The initiative also includes an outreach and referral network with the University of Rochester, Rochester Institute for Technology, Columbia University, Massachusetts Institute of Technology, University of California – Santa Barbara, University of Arizona, as well as New York State community colleges. In total AIM Photonics includes more than 100 signed members, partners, and additional interested collaborators.