Category Archives: Device Architecture

Avnet (Nasdaq: AVT), a global technology company, has been named a global distribution partner for Microsemi Corporation, a wholly owned subsidiary of Microchip Technology, Inc. As an extension of Avnet’s multiyear relationship with Microchip Technology, Inc. (Nasdaq: MCHP), Avnet customers now have immediate access to the complete Microsemi portfolio of semiconductor and system solutions for aerospace and defense, communications, data center and industrial markets. Microchip completed its acquisition of Microsemi earlier this year.

“As our customers increasingly turn to us for secure solutions to help them bring their industrial, aerospace and defense products to market faster, Microsemi is the ideal fit to our product line card,” said Lynn Torrel, senior vice president of global supplier and customer management, Avnet. “Avnet is experienced and knowledgeable in the full Microsemi portfolio, and we’re ready to support our customers and drive growth for Microsemi’s target industries. The extension of our partnership with Microchip underscores our focus and commitment to providing our supplier partners with the highest level of expertise and services to improve their businesses.”

Microsemi is a leading provider of semiconductor solutions differentiated by power, security, reliability and performance. As part of the expansion of Avnet’s Microchip franchise, Avnet will now distribute the full line of Microsemi products which includes: high performance analog and mixed signal, enterprise storage and communication solutions, programmable solutions, power management, timing and ASIC offerings — as well as custom design capabilities and services.

SEMI today announced its support for calls on the Trump administration yesterday by nearly 50 members of Congress to remove tariffs on U.S. semiconductor products imported from China. In a bipartisan letterto Ambassador Robert Lighthizer, U.S. Trade Representative (USTR), the members of the House of Representatives – led by Reps. Pete Sessions (R-TX) and Zoe Lofgren (D-CA), the House co-chairs of the Congressional Semiconductor Caucus – stressed the importance of semiconductors in the modern economy and argued that the duties will do nothing to address concerns regarding China’s trade practices.

SEMI fully supports the Congressional recommendation and believes that the proposed tariffs will ultimately reduce semiconductor-related exports, limit technology innovation, introduce significant uncertainty in the semiconductor supply chain and cost U.S. companies an estimated more than $500 million annually. The tariffs also threaten to raise prices of semiconductor products and put thousands of high-paying and high skill jobs at risk. Last week, SEMI testified before a U.S. government interagency panel weighing the merits of the tariffs, urging the Trump administration to eliminate tariffs on semiconductor products.

In August, Toshiba Electronic Devices & Storage Corporation (“Toshiba”) will start mass production and shipments of “TPWR7904PB” and “TPW1R104PB”, 40V N-channel power MOSFETs for automotive applications. They are housed in the DSOP Advance(WF) packages that deliver double-sided cooling, low resistance, and small size.

The new products secure high heat dissipation and low On-resistance characteristics by mounting a U-MOS IX-H series chip, a MOSFET with the latest trench structure, into a DSOP Advance(WF) package. Heat generated by conduction loss is effectively dissipated, improving the flexibility of thermal design.

The U-MOS IX-H series also delivers lower switching noise than Toshiba’s previous U-MOS IV series, contributing to lower EMI[1].
The DSOP Advance(WF) package has a wettable flank terminal structure[2].

Applications
– Electric power steering
– Load switches
– Electric pumps

Features
– Qualified for AEC-Q101, suitable for automotive applications
– Double-sided cooling package with top plate[3] and drain
– Improved AOI visibility due to wettable flank structure
– U-MOS IX-H series featuring low On-resistance and low noise characteristics

Main Specifications

　(@Ta=25 ℃)

Part
number

Absolute
maximum ratings

Drain-source
On-resistance
RDS(ON) max (mΩ)

Built-in
Zener Diode
between
Gate-Source

 Series Package

Drain-
source
voltage
VDSS
(V)

Drain
current
(DC)
ID
(A)
@VGS＝6 V @VGS=10 V
TPWR7904PB 40 150 1.3 0.79 No U-MOSⅨ-H

DSOP
Advance(WF)L
TPW1R104PB 120 1.96 1.14

DSOP
Advance(WF)M

Notes:
[1] EMI (Electromagnetic interference)
[2] Wettable flank terminal structure: A terminal structure that allows AOI (Automated Optical Inspection) of installation on boards.
[3] Be aware that the top plate has the same electric potential as the sources; however, not intended for an electrode.

In its recently released Mid-Year Update to The McClean Report 2018, IC Insights forecasts that the 2018-2022 global GDP and IC market correlation coefficient will reach 0.95, up from 0.88 in the 2010-2017 time period.  IC Insights depicts the increasingly close correlation between worldwide GDP growth and IC market growth through 2017, as well as its forecast through 2022, in Figure 1.

As shown, over the 2010-2017 timeframe, the correlation coefficient between worldwide GDP lgrowth and IC market growth was 0.88, a strong figure given that a perfect correlation is 1.0.  In the three decades previous to this timeperiod, the correlation coefficient ranged from a relatively weak 0.63 in the early 2000s to a negative correlation (i.e., essentially no correlation) of -0.10 in the 1990s.

IC Insights believes that the increasing number of mergers and acquisitions, leading to fewer major IC manufacturers and suppliers, is one of major changes in the supply base that illustrate the maturing of the industry that is helping foster a closer correlation between worldwide GDP growth and IC market growth. Other factors include the strong movement to the fab-lite business model and a declining capex as a percent of sales ratio, all trends that are indicative of dramatic changes to the semiconductor industry that are likely to lead to less volatile market cycles over the long term.

In 2017, IC industry growth was greatly influenced by the “Capacity/Capital Spending Cycle Model” as the DRAM and NAND flash markets surged and served to drive total IC industry growth of 25%.  It would initially appear that the strong correlation coefficient between worldwide GDP growth and total IC market growth that had been evident from 2010 through 2016 had disappeared in 2017.  However, IC Insights does not believe that is the case.

When excluding the DRAM and NAND flash segments from the IC market in 2017, the remainder of the IC market displayed an 11% increase, which closely correlates to what would be expected given a worldwide GDP increase from 2.4% in 2016 to 3.1% in 2017.  Moreover, the three-point decline in the total IC market growth rate forecast for 2018, when excluding DRAM and NAND flash (from 11% in 2017 to 8% in 2018), is expected to mirror the slight decline expected for worldwide GDP growth this year as compared to last year.  Thus, excluding the amazing surge for the DRAM and NAND flash markets in 2017 and 2018, IC Insights believes that the trend toward an increasingly close correlation between total IC market growth and worldwide GDP growth is still largely intact.

Figure 1

 

Rambus Inc. (NASDAQ: RMBS), a developer of digital security, semiconductor and IP products and services, today announced the appointment of Sanjay Saraf to its board of directors, effective immediately.

Mr. Saraf currently serves as the executive vice president and chief technology officer at YapStone, where he is responsible for product engineering, infrastructure, operations, information security, research and development, and product innovation. Prior to YapStone, he was chief technology officer at Western Union Digital and was responsible for digital transformation and leading product engineering teams. Throughout Mr. Saraf’s career, he successfully launched mobile payments applications in over 50 countries, integrated payments with over a thousand banks in over 70 countries and processed over $80 billion in principal volume in over 200 countries.

“Sanjay’s accomplished background in mobile payments and digital transformation makes him an outstanding addition to the Board. He will bring strong leadership, especially for our growing security and payments business,” said Eric Stang, chairman of the Board at Rambus. “We are pleased to welcome Sanjay to the Board and look forward to his collaboration and contribution.”

“I am honored and thrilled to be joining Rambus’ Board of Directors,” said Saraf. “I look forward to using my leadership experience and knowledge of the payments and security industry to support Rambus’ strategy and growth initiatives.”

Mr. Saraf holds a B.S. in Engineering from the University of Bombay and a M.S. in Engineering from the University of Wyoming. He will be serving on the Board alongside E. Thomas Fisher, Emiko Higashi, Charles Kissner, David Shrigley and Eric Stang.

By Jay Chittooran, Public Policy Manager, SEMI 

Two months after opposing $34 billion in U.S. trade tariffs on behalf of the U.S. semiconductor manufacturing industry, Jonathan Davis, global vice president of industry advocacy at SEMI, this week spoke out against an additional $16 billion duties on Chinese goods. Testifying before the same U.S. interagency panel mulling the merits of the tariffs, Davis called for the removal of 29 tariff lines covering items critical to semiconductor manufacturing including machines and spare parts used to make, wafers, flat panel displays and masks.

In his testimony to the panel, Davis stressed that while SEMI supports stronger protections against the theft of valuable intellectual property (IP), tariffs do little to address U.S. concerns over IP loss. Over the past month, SEMI has also submitted written comments and opposed the tariffs in public testimony. The panel includes representatives from the U.S. Trade Representative (USTR), Departments of Treasury, Commerce, State and Defense, and the Council of Economic Advisers.

Also testifying, Joe Pon, corporate vice president at Applied Materials, explained that the proposed tariffs will harm small and midsized companies and other U.S. business interests. Describing the tariffs as a tax on exports of high-value U.S. goods, Pon said the duties give non-U.S. firms an unfair competitive advantage.

In a parallel push to Davis’s testimony, SEMI, with more than 10 representatives from six member companies, met with 16 congressional offices this week to underscore the damage the tariffs would wreak on the U.S. semiconductor industry. The fallout would include higher operating costs, fewer exports and slower innovation. The tariffs would also curb industry growth and put thousands of high-paying, high-skill jobs at risk. SEMI pressed congressional leaders to reject the tariffs and support a push for congress to re-assert itself on trade policy.

Tariffs to cost U.S. SEMI members more than $500 million

SEMI estimates that the second list of proposed tariffs, covering about $16 billion in Chinese goods, will cost its 400 U.S. members more than $500 million annually in additional duties.

The tariffs on $34 billion in Chinese goods, which took effect July 6, impact products such as test and inspection equipment as well as spare parts that enter the U.S. from China. That round of tariffs will cost SEMI member companies and estimated tens of millions of dollars annually.

SEMI public policy team asks members to review tariff list

Looking ahead, SEMI encourages members to review the newly released $200 billion tariff list, determine any impact to their businesses and share their findings with SEMI’s public policy team.

The U.S. Trade Representative (USTR) has published the exclusion process for products subject to the China 301 tariffs. If your company’s products are subject to tariffs, you can request an exclusion.

In evaluating product exclusion requests, the USTR will consider whether a product is available from a source outside of China, whether the additional duties would cause severe economic harm to the requestor or other U.S. interests, and whether the product is strategically important or related to Chinese industrial programs (such as “Made in China 2025”).

The deadline for submitting product exclusion requests to USTR is October 9, 2018. Approved exclusions will be effective for one year upon approval and retroactive to July 6, 2018.

More information including the process for submitting the product exclusion request can be found here.

Any SEMI members with questions should contact Jay Chittooran, Public Policy Manager at SEMI, at [email protected].

Imec, a research and innovation hub in nanoelectronics and digital technologies, announces that Niels Verellen, one of its young scientists, has been awarded an ERC Starting Grant. The grant of 1.5 million euros (for 5 years) will be used to enable high-resolution, fast, robust, zero-maintenance, inexpensive and ultra-compact microscopy technology based on on-chip photonics and CMOS image sensors. The technology paves the way for multiple applications of cell imaging in life sciences, biology, and medicine and compact, cost-effective DNA sequencing instruments.

Microscopy is an indispensable tool in biology and medicine that has fueled many breakthroughs. Recently the world of microscopy has witnessed a true revolution in terms of increased resolution of fluorescent imaging techniques, including a Nobel Prize in 2014. Yet, these techniques remain largely locked-up in specialized laboratories as they require bulky, expensive instrumentation and highly skilled operators.

The next big push in microscopy with a large societal impact will come from extremely compact and robust optical systems that will make high-resolution microscopy highly accessible and as such facilitate the diagnosis and treatment of diseases or disorders caused by problems at the cell or molecular level, such as meningitis, malaria, diabetes, cancer, and Alzheimer’s disease. Moreover, it will pave the way to DNA analysis as a more standard procedure, not only for the diagnosis of genomic disorders or in forensics, but also in cancer treatment, follow-up of transplants, the microbiome, pre-natal tests, and even agriculture, and archeology.

Niels Verellen, Senior Photonics Researcher & project leader at imec: “Compact, high-resolution and high-throughput microscopy devices will induce a profound change in the way cell biologists do research, in the way DNA sequencing becomes more and more accessible, in the way certain diseases can be diagnosed, new drugs are screened in the pharma industry, and healthcare workers can diagnose patients in remote areas.”

The topic of Verellen’s ERC grant is the development of Integrated high-Resolution On-Chip Structured Illumination Microscopy (IROCSIM). This new technology is based on a novel imaging platform that integrates active on-chip photonics and CMOS image sensors. “Whereas existing microscopy techniques today suffer from a trade-off between equipment size, field-of-view, and resolution, the IROCSIM solution will eliminate the need for bulky optical components and enable microscopy in the smallest possible form-factor, with a scalable field-of-view and without compromising the resolution,” continues Verellen.

The European Research Council (ERC) is a pan European funding body designed to support investigator-driven frontier research and stimulate scientific excellence across Europe. The ERC aims to support the best and most creative scientists to identify and explore new opportunities and directions in any field of research. ERC Starting grants in particular are designed to support outstanding researchers with 2 to 7 years postdoctoral experience.

Jo De Boeck, imec’s CTO says: “We are very proud that young researchers such as Niels Verellen are awarded an ERC Starting Grant and as such get a unique opportunity to fulfill their ambitions and creative ideas in research. At imec, we select and foster our young scientists and provide them with a world-class infrastructure. These ERC Starting Grants show that their work indeed meets the highest standards.”

The silicon-on-insulator market is expected to reach USD 1,832.5 million by 2023 from USD 686.0 million by 2018, at a CAGR of 21.7%, According to the new market research report “Silicon on Insulator (SOI) Market by Wafer Size (200 mm and less than 200 mm, 300 mm), Wafer type (RF-SOI, FD-SOI, PD-SOI, Power SOI, Emerging-SOI), Application (Consumer Electronics, Automotive, Datacom, Industrial), Technology – Global Forecast to 2023”, published by MarketsandMarkets™ . The increasing use of SOI wafers in advanced devices such as smartphones, tablets, earphones/headphones, and wearables is expected to boost the market for consumer electronics application. Moreover, while manufacturing thin wafers, the use of SOI technology prevents the wastage of silicon, which reduces the cost of semiconductor devices. Hence, the effective use of silicon during the manufacture of thin SOI wafers is a major factor driving the growth of the SOI market.

SOI market for 300-mm wafers size to grow at a higher CAGR during forecast period

The market for 300-mm wafer size is expected to grow at the highest CAGR during 2018-2023. Wafer and foundry players expanding their capacity for producing 300-mm wafers is one of the driving factors for the growth of the SOI market. For instance, Soitec expanded its manufacturing capacity for the production of 300-mm SOI wafers.

Consumer electronics application expected to hold the largest share of the SOI market during the forecast period

Among the SOI applications, the market for consumer electronics is expected to hold the largest share during 2018-2023. The growth of this market is attributed to the increasing demand for SOI products in smartphones and other consumer electronics devices. For instance, RF SOI wafers are commonly used in smart devices as these wafers enable device integration, cost-effectiveness, and high performance. Also, the growing adoption of FD SOI for consumer or IoT devices is expected to drive the growth of the market.

SOI market in APAC expected to grow at the highest CAGR during the forecast period

SOI market in APAC is expected to grow at the highest CAGR during 2018-2023. APAC is witnessing an increase in the use of SOI products owing to the presence of a large number of consumer electronic companies, smartphone manufacturers, and advanced ICT technology providers, and wafer and foundry players in APAC.

Major players operating in this market are Soitec (France), Shin-Etsu Chemical (Japan), GlobalWafers (Taiwan), SUMCO (Japan), Simgui (China), GlobalFoundries (US), STMicroelectronics N.V. (Switzerland), TowerJazz (Isreal), NXP Semiconductor N.V. (Netherlands), and Murata Manufacturing (Japan).

Know more about the Silicon on Insulator (SOI) Market:

https://www.marketsandmarkets.com/Market-Reports/global-silicon-on-insulator-market-158.html

SiFive, the provider of commercial RISC-V processor IP, today welcomed Chipus Microelectronics, a semiconductor company with proven expertise in the development of ultra-low-power (ULP), low-voltage, analog and mixed-signal integrated circuits, to the growing DesignShare ecosystem. Through the partnership, Chipus will provide ULP IP for power management and ULP RF Front-Ends.

Chipus’ customizable technology will make it easier for SiFive customers to save power and extend battery life for IoT edge devices. Chipus also plans to add temperature sensors and switched regulators to the DesignShare program in the near future.

“Chipus is thrilled to partner up with SiFive to bring more chip design opportunities to reality, enabling innovation with our Ultra-Low-Power and simple-to-customize IP solutions,” said Murilo Pilon Pessatti, CEO and co-founder of Chipus. “Our mission, together with SiFive, is to enable innovation. With our expertise, Chipus looks forward to contributing to new IoT applications and edge devices.”

The availability of Chipus’ ULP IP through the DesignShare program shortens the time to market and removes common barriers to entry that have traditionally prevented smaller companies from developing custom silicon. Companies like SiFive, Chipus and other DesignShare partners provide low- or no-entry fee IP to emerging companies, minimizing the upfront engineering costs needed to bring a custom chip from design to realization.

“Startups today go through extensive processes, from sourcing viable IP to negotiating legal contracts, before they can even develop a prototype,” said Shafy Eltoukhy, vice president of operations and head of DesignShare for SiFive. “With Chipus joining our growing DesignShare economy, we continue to simplify the prototyping process and spur innovation across the industry.”

Since DesignShare launched in 2017, the program has grown to include a wide range of IP solutions, from complete ASIC solutions and trace technology to embedded memory and precision PLL. For more information on DesignShare and to see the complete list of available technologies, visit www.sifive.com/designshare.

Hewlett Packard Enterprise (HPE) and PLDA®, an industry leader in high-speed interconnect IP, today announced a joint collaboration to meet the challenges of next-generation connectivity for advanced workloads. Gen-Z is a new open interconnect protocol and connector developed by the Gen-Z Consortium to solve the challenges associated with processing and analyzing huge amounts of data in real time. HPE and PLDA are working together to develop Gen-Z semiconductor IP designed to the Gen-Z Core Specification 1.0.

Announced in February 2018, the Core Specification 1.0 enables the industry to begin the development of products that incorporate the Gen-Z interconnect protocol.

Creating one standard interconnect is important because it allows any component – processing, memory, accelerators, networking – to talk to any other component as if it were communicating with its own local memory using simple commands. PLDA’s Gen-Z IP will provide the building blocks to create high performance low latency solutions where every device in the system is connected at the speed of memory.

“PLDA is proud to collaborate with HPE to provide comprehensive design IP to silicon providers to enable volume production of Gen-Z compatible components and to enable system vendors to utilize the Gen-Z silicon components to build network, storage and compute systems and solutions,” said Arnaud Schleich, CEO, at PLDA. “This will enable an open ecosystem of Gen-Z building blocks for a variety of solutions from the intelligent edge to the cloud.”

With Gen-Z, the industry can simultaneously support memory, I/O, storage and different forms of compute on a common disaggregated, composable or memory-semantic fabric (or interconnect).

Gen-Z reflects a broader industry trend that recognizes the importance and role of open standards in providing a level playing field to promote adoption, innovation and choice. By enabling technologists to collaborate and contribute to an open and competitive ecosystem, Gen-Z will help the industry fundamentally change how the world thinks about computing.

“At HPE, we recognize the need to partner in the development of new architectures and technologies that can effectively meet the needs of our customers,” said Mark Potter, CTO, HPE and Director, Hewlett Packard Labs. “HPE is committed to supporting open standards and working collaboratively to develop this new interconnect. The collaboration with PLDA is a demonstration of HPE’s commitment to the development and industry-wide proliferation of Gen-Z, an important technology in meeting the demands of the modern data center and in creating a Memory-Driven Computing architecture.”

With Gen-Z, the industry can combine fast persistent memory, DRAM and task-specific processing and accelerators on a fast memory fabric without legacy constraints or device hierarchies. This approach optimizes and simplifies system configurations to deliver optimal performance tailored to specific user demands simply and efficiently with better performance at reduced cost.