Category Archives: Device Architecture

In a key move to inspire the next generation of innovators, the School District of Osceola County (SDOC) today became the first school district to join the SEMI High Tech U (HTU) Certified Partner Program (CPP), a curriculum that prepares high-school students to pursue careers in STEM fields.

Under the program sponsored by the SEMI Foundation, SDOC will independently deliver HTU programs to local students at the Osceola Technical College Campus, in Kissimmee, Florida. SEMI Foundation awarded SDOC the certification today at a graduation ceremony for HTU students.

“SDOC’s partnership with the SEMI Foundation gives young people and families in our community exposure to high-tech career opportunities and the educational pathways to reach their goals,” said Debra Pace, superintendent of School District of Osceola County. “Our industry partners – including Mercury, University of Central Florida, BRIDG, Osceola Technical College, imec, Neo City and the Osceola County Education Foundation – have all made it possible for SDOC to offer this amazing opportunity to students.”

“We are delighted to partner with SDOC in our common goal to motivate the next generation of innovators,” said Leslie Tugman, executive director of the SEMI Foundation. “The School District of Osceola County is well-positioned to put college-bound high school students on a track that speeds the time from graduation to employment in high technology. SDOC’s certification is a tremendous benefit for it students, the community and employers in the fast-growing Central Florida tech corridor.”

To win the certification, SDOC delivered HTU over the past three years with guidance and instruction from SEMI. SDOC is only the second organization to receive the certification.

The nonprofit SEMI Foundation has been delivering its flagship program, SEMI High Tech U, at industry sites around the world since 2001 to emphasize the importance of STEM skills and inspire young people to pursue careers in high-technology fields. HTU students meet engineers and STEM volunteer instructors from industry for site tours and hands-on classroom activities such as etching wafers, making circuits, coding and training for professional interviews.

SEMI’s Certified Partner Program identifies organizations that provide quality training and can recruit and educate local high-school students in the value of careers in science, technology, engineering and math (STEM). Participating organizations are trained to deliver the unique SEMI curriculum with the support of volunteer instructors from the high-tech and STEM industries. SEMI High Tech U is the longest-running STEM career exploration program in the United States with documented student impact. Since inception, SEMI has reached over 8,000 high-school students in 12 states and nine countries with its award-winning program.

SEMI Foundation is a 501(c)(3) nonprofit charitable organization founded in 2001 to support education and career awareness in the electronics and high-tech fields through career exploration programs and scholarships. For more information, visit www.semifoundation.org.

Solar cells need to slim down.

Solar cells are devices that absorb photons from sunlight and convert their energy to move electrons — enabling the production of clean energy and providing a dependable route to help combat climate change. But most solar cells used widely today are thick, fragile and stiff, which limits their application to flat surfaces and increases the cost to make the solar cell.

“Thin-film solar cells” could be 1/100th the thickness of a piece of paper and flexible enough to festoon surfaces ranging from an aerodynamically sleek car to clothing. To make thin-film solar cells, scientists are moving beyond the “classic” semiconductor compounds, such as gallium arsenide or silicon, and working instead with other light-harvesting compounds that have the potential to be cheaper and easier to mass produce. The compounds could be widely adopted if they could perform as well as today’s technology.

In a paper published online this spring in the journal Nature Photonics, scientists at the University of Washington report that a prototype semiconductor thin-film has performed even better than today’s best solar cell materials at emitting light.

“It may sound odd since solar cells absorb light and turn it into electricity, but the best solar cell materials are also great at emitting light,” said co-author and UW chemical engineering professor Hugh Hillhouse, who is also a faculty member with both the UW’s Clean Energy Institute and Molecular Engineering & Sciences Institute. “In fact, typically the more efficiently they emit light, the more voltage they generate.”

The UW team achieved a record performance in this material, known as a lead-halide perovskite, by chemically treating it through a process known as “surface passivation,” which treats imperfections and reduces the likelihood that the absorbed photons will end up wasted rather than converted to useful energy.

“One large problem with perovskite solar cells is that too much absorbed sunlight was ending up as wasted heat, not useful electricity,” said co-author David Ginger, a UW professor of chemistry and chief scientist at the CEI. “We are hopeful that surface passivation strategies like this will help improve the performance and stability of perovskite solar cells.”

Ginger’s and Hillhouse’s teams worked together to demonstrate that surface passivation of perovskites sharply boosted performance to levels that would make this material among the best for thin-film solar cells. They experimented with a variety of chemicals for surface passivation before finding one, an organic compound known by its acronym TOPO, that boosted perovskite performance to levels approaching the best gallium arsenide semiconductors.

“Our team at the UW was one of the first to identify performance-limiting defects at the surfaces of perovskite materials, and now we are excited to have discovered an effective way to chemically engineer these surfaces with TOPO molecules,” said co-lead author Dane deQuilettes, a postdoctoral researcher at the Massachusetts Institute of Technology who conducted this research as a UW chemistry doctoral student. “At first, we were really surprised to find that the passivated materials seemed to be just as good as gallium arsenide, which holds the solar cell efficiency record. So to double-check our results, we devised a few different approaches to confirm the improvements in perovskite material quality.”

DeQuilettes and co-lead author Ian Braly, who conducted this research as a doctoral student in chemical engineering, showed that TOPO-treating a perovskite semiconductor significantly impacted both its internal and external photoluminescence quantum efficiencies — metrics used to determine how good a semiconducting material is at utilizing an absorbed photon’s energy rather than losing it as heat. TOPO-treating the perovskite increased the internal photoluminescence quantum efficiencies by tenfold — from 9.4 percent to nearly 92 percent.

“Our measurements observing the efficiency with which passivated hybrid perovskites absorb and emit light show that there are no inherent material flaws preventing further solar cell improvements,” said Braly. “Further, by fitting the emission spectra to a theoretical model, we showed that these materials could generate voltages 97 percent of the theoretical maximum, equal to the world record gallium arsenide solar cell and much higher than record silicon cells that only reach 84 percent.”

These improvements in material quality are theoretically predicted to enable the light-to-electricity power conversion efficiency to reach 27.9 percent under regular sunlight levels, which would push the perovskite-based photovoltaic record past the best silicon devices.

The next step for perovskites, the researchers said, is to demonstrate a similar chemical passivation that is compatible with easily manufactured electrodes — as well as to experiment with other types of surface passivation.

“Perovskites have already demonstrated unprecedented success in photovoltaic devices, but there is so much room for further improvement,” said deQuilettes. “Here we think we have provided a path forward for the community to better harness the sun’s energy.”

Semiconductor Research Corporation (SRC), today announced the release of $26 million in added research funding for its New Science Team (NST) Joint University Microelectronics Program (JUMP). JUMP will fund 24 additional research projects spanning 14 unique U.S. universities. The new projects will be integrated into JUMP’s six existing research centers. NST will continue to distribute funds over its five-year plan, and industrial sponsors are welcome to join to further accentuate those plans.

The awards have been given to 27 faculty and will enhance the program’s expertise in technical areas such as atomic layer deposition (ALD), novel ferroelectric and spintronic materials and devices, 3D and heterogeneous integration, thermal management solutions, architectures for machine learning and statistical computing, memory abstractions, reconfigurable RF frontends, and mmWave to THz arrays and systems for communications and sensing.

“The goal of the NST project is not only to extend the viability of Moore’s Law economics through 2030, but to also change the research paradigm to one of co-optimization across the design hierarchy stack through multi-disciplinary teams,” said Ken Hansen, President and CEO of Semiconductor Research Corporation. “Our strategic partnerships with industry, academia, and government agencies foster the environment needed to realize the next wave of semiconductor technology innovations.”

“A new wave of fundamental research is required to unlock the ultimate potential of autonomous vehicles, smart cities, and Artificial Intelligence (AI),” said Dr. Michael Mayberry, Senior Vice President and Chief Technology Officer of Intel and the elected Chairman of the NST Governing Council. “Such advances will be fueled by novel and far-reaching improvements in the materials, devices, circuits, architectures, and systems used for computing and communications.”

The JUMP program, a consortium consisting of 11 industrial participants and the Defense Advanced Research Projects Agency (DARPA), is one of two complementary research programs for the NST project—a 5-year, greater than $300 million SRC initiative launched this January. JUMP and its six thematic centers will advance a new wave of fundamental research focused on the high-performance, energy-efficient microelectronics for communications, computing, and storage needs for 2025 and beyond.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today welcomed newly announced research partnerships between the Defense Department’s Defense Advanced Research Projects Agency (DARPA) and research teams from industry and academia that aim to bolster long-term semiconductor research. The research partnerships, part of new programs within DARPA’s Electronics Resurgence Initiative (ERI), will target advances in semiconductor circuit design, materials, and systems architectures. The selected research teams were unveiled yesterday in San Francisco during the first annual DARPA ERI Summit, a three-day event bringing together hundreds of members of the microelectronics community.

“As the brains of modern electronics, semiconductors are central to America’s economy, national security, and global competitiveness,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The DARPA research partnerships announced yesterday will help catalyze transformational advances in semiconductor technology and enhance semiconductors’ positive impacts on our country.”

The ERI is divided into three main research thrust areas – Design, Materials & Integration, and Architectures. Each thrust area will feature two new research programs. The Design research thrust area will include the Intelligent Design of Electronic Assets (IDEA) program and the Posh Open Source Hardware (POSH) program. The Materials & Integration research thrust area will include the Three-Dimensional Monolithic System-on-a-Chip (3DSoC) program and the Foundations Required for Novel Compute (FRANC) program. The ERI Architectures research thrust area will include the Software Defined Hardware (SDH) program and the Domain-specific System on Chip (DSSoC) program.

“The semiconductor industry plows about one-fifth of its revenues into R&D – among the highest shares of any sector – and has a long record of partnering with our government to advance early-stage research,” Neuffer said. “The new DARPA research partnerships mark a major commitment to furthering semiconductor technology and keeping America at the tip of the spear globally in semiconductor innovation.”

Neuffer also noted SIA’s longstanding support for basic scientific research funded through other federal agencies such as the National Science Foundation (NSF), the National Institute of Standards and Technology (NIST), and the Department of Energy (DOE) Office of Science. He expressed the semiconductor industry’s eagerness to work with the Administration and Congress to advance research investments that will promote America’s economic and national security and technological leadership.

In total, the ERI will invest upwards of $1.5 billion over five years to jumpstart innovation in the electronics industry. In addition to fostering advancements in semiconductor technologies used for national security, the ripple effect from this research will be felt across the full range of semiconductor applications: communications, computing, health care, transportation, clean energy, and countless others. For more information about the Electronics Resurgence Initiative and the first annual ERI Summit, please visit http://www.eri-summit.com/.

SiFive, a provider of commercial RISC-V processor IP, today announced Brad Holtzinger as Vice President of Worldwide Sales, where he will work with the existing global portfolio of SiFive customers and onboard new clients seeking to take advantage of the company’s market-leading Core IP.  Holtzinger brings more than 30 years of embedded industry experience in sales, marketing and engineering.

“It is rare to see a company rapidly disrupting the silicon sector,” Holtzinger said. “I look forward to joining the SiFive team and supporting our customers and partners globally in adopting RISC-V and SiFive’s IP to move the industry forward.”

Previously, Holtzinger was the Vice President of Worldwide Sales for MIPS Technologies where he led licensing and sales of its global IP portfolio.  While at MIPS, Holtzinger drove the company to record sales and negotiated the sale and licensing of the MIPS patent portfolio to Bridge Crossing for $350 million and the sale of the remaining company to Imagination.

Prior to MIPS, he led the sales, operations and business development efforts as well as held the position of CEO for a number of privately funded and venture backed startups. He also founded the OEM Systems division of Force Computers, which was sold to Solectron for approximately $190 million.

Holtzinger started his career at Motorola as an embedded hardware and software design engineer, where he authored Motorola’s Technical Training class on Unix® System V and eventually was one of the founding members of Motorola’s Microcomputer Group, (MCG), that sold OEM systems and VME boards.  Holtzinger received his bachelor’s degree in electrical engineering from Purdue University and was an instructor at University of California, Berkeley.

“SiFive is excited to bring someone with Brad’s decades-long silicon sales leadership to the SiFive executive team,” said Naveed Sherwani, CEO of SiFive. “His experience leading a world-class sales organization and embedded hardware expertise will help continue to propel SiFive customer adoption.”

Semiconductor revenues are expected to increase 12.8% in 2018 as a result of continued strong memory prices. Units are expected to grow 7.2%. The forecast is based on moderate smartphone sales with a possible return to lower memory prices in the second half of the year. This, among other market issues, will push 2018 wafer demand to over 115 million units in 300mm equivalents according to Semico Research’s newest report, Semico Wafer Demand Update Q2 2018 (MA111-18).

“Semiconductor manufacturers are rolling out new products targeted at artificial intelligence applications. Products require both the most advanced technologies for AI training functions as well as potentially high-volume products for edge devices,” says Joanne Itow, Manager Manufacturing Research for Semico. “On the other side of the technology spectrum, mature processes for sensors and analog products such as biometric sensors, RF and power management continue to be in high demand aided by growth in Internet of Things (IoT) applications along with more ‘smart devices’ that are beginning to build in algorithms that are the precursor to full-fledged AI devices.”

Key findings include:

  • 2018 NAND revenues are expected to increase 18.9%.
  • MCU revenues are expected to exceed $17 billion in 2018.
  • Total Communication MOS Logic wafer demand is expected to increase 4.0% in 2018.
  • Sensor units are expected to grow 20.4% in 2018.

North America-based manufacturers of semiconductor equipment posted $2.49 billion in billings worldwide in June 2018 (three-month average basis), according to the June Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 8.0 percent lower than the final May 2018 level of $2.70 billion, and is 8.1 percent higher than the June 2017 billings level of $2.30 billion.

“Global billings of North American equipment manufacturers declined for the current month by 8 percent from the historic high but is still 8 percent higher than billings for the same period last year,” said Ajit Manocha, president and CEO of SEMI. “Billings remain robust.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
January 2018
$2,370.1
27.5%
February 2018
$2,417.8
22.5%
March 2018
$2,431.8
16.9%
April 2018
$2,689.9
25.9%
May 2018 (final)
$2,702.3
19.0%
June 2018 (prelim)
$2,485.7
8.1%

Source: SEMI (www.semi.org), July 2018

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

Toshiba Memory Corporation today held a groundbreaking ceremony for the first semiconductor fabrication facility (fab), called K1, in Kitakami, Iwate prefecture, in northeastern Japan. On its completion in autumn 2019, the facility will be one of the most advanced manufacturing operations in the world, dedicated to production of 3D flash memory.

Toshiba Memory continues to advance technologies in flash memory. The company is now leading the way forward with advances in its BiCS FLASH™, its proprietary 3D flash memory.

Demand for 3D flash memory is increasing significantly on fast growing demand for enterprise servers, datacenters and smartphones. Toshiba memory expects continued strong growth in the mid and long term. The new facility will make a major contribution to business competitiveness in corporation with Yokkaichi operations.

The new facility will not only be the largest Toshiba Memory fab, but it will be the most advanced as well. It will be constructed with a seismic isolation structure that allows it to absorb earthquake tremors, and it will reduce environmental loads by deployment of the latest energy-saving manufacturing facilities. It will also introduce an advanced production system that uses artificial intelligence (AI) to boost productivity. Decisions on the new fab’s equipment investment, production capacity and production plan will reflect market trends.

Toshiba Memory expects to continue its joint venture investments in the new facility based on ongoing discussions with Western Digital Corporation.

Going forward, Toshiba Memory will continue to actively cultivate initiatives aimed at strengthening competitiveness, including timely capital investments and R&D in line with market trends. The company will also contribute to the development of the regional economy of Iwate prefecture, Japan.

Researchers have shown that a chip-based device measuring a millimeter square could be used to generate quantum-based random numbers at gigabit per second speeds. The tiny device requires little power and could enable stand-alone random number generators or be incorporated into laptops and smart phones to offer real-time encryption.

Researchers created a chip-based device measuring a millimeter square that can potentially generate quantum-based random numbers at gigabit per second speeds. The small square to the right of the penny contains all the optical components of the random number generator. Credit: Francesco Raffaelli, University of Bristol

“While part of the control electronics is not integrated yet, the device we designed integrates all the required optical components on one chip,” said first author Francesco Raffaelli, University of Bristol, United Kingdom. “Using this device by itself or integrating it into other portable devices would be very useful in the future to make our information more secure and to better protect our privacy.”

Random number generators are used to encrypt data transmitted during digital transactions such as buying products online or sending a secure e-mail. Today’s random number generators are based on computer algorithms, which can leave data vulnerable if hackers figure out the algorithm used.

In The Optical Society (OSA) journal Optics Express, the researchers report a quantum random number generator based on randomly emitted photons from a diode laser. Because the photon emission is inherently random, it is impossible to predict the numbers that will be generated.

“Compared to other integrated quantum random number generators demonstrated recently, ours can accomplish very high generation rates with relatively low optical powers,” said Raffaelli. “Using less power to produce random numbers helps avoid problems such as excess heat on the chip.”

Silicon photonics

The new chip was enabled by developments in silicon photonics technology, which uses the same semiconductor fabrication techniques used to make computer chips to fabricate optical components in silicon. It is now possible to fabricate waveguides into silicon that can guide light through the chip without losing the light energy along the way. These waveguides can be integrated onto a chip with electronics and integrated detectors that operate at very high speeds to convert the light signals into information.

The new chip-based random number generator takes advantage of the fact that under certain conditions a laser will emit photons randomly. The device converts these photons into optical power using a tiny device called an interferometer. Very small photodetectors integrated into the same chip then detect the optical power and convert it into a voltage that can be turned into random numbers.

“Despite the advancements in silicon photonics, there is still light lost inside the chip, which leads to very little light reaching the detectors,” said Raffaelli. “This required us to optimize all the parameters very precisely and design low noise electronics to detect the optical signal inside the chip.”

The new chip-based device not only brings portability advantages but is also more stable than the same device made using bulk optics. This is because interferometers are very sensitive to environmental conditions such as temperature and it is easier to control the temperature of a small chip. It is also far easier to precisely reproduce thousands of identical chips using semiconductor fabrication, whereas reproducing the necessary precision with bulk optics is more difficult.

Testing the chip

To experimentally test their design, the researchers had a foundry fabricate the random number generator chip. After characterizing the optical and electronic performance, they used it for random number generation. They estimate a potential randomness generation rate of nearly 2.8 gigabits per second for their device, which would be fast enough to enable real-time encryption.

“We demonstrated random number generation using about a tenth of the power used in other chip-based quantum random number generator devices,” said Raffaelli. “Our work shows the feasibility of this type of integrated platform.”

Although the chip containing the optical components is only one millimeter square, the researchers used an external laser which provides the source of randomness and electronics and measurement tools that required an optical table. They are now working to create a portable device about the size of a mobile phone that contains both the chip and the necessary electronics.

Applied Materials, Inc. today announced it has been awarded a contract by the Defense Advanced Research Projects Agency (DARPA) to develop a new type of electronic switch for artificial intelligence that mimics the way the human brain works to enable dramatic improvements in performance and power efficiency. The project is being supported by DARPA’s Electronics Resurgence Initiative, a multi-year research effort intended to achieve far-reaching improvements in electronics performance well beyond the limits of traditional Moore’s Law scaling.

Applied is working with Arm and Symetrix to develop a new neuromorphic switch based on CeRAM memory that can allow data to be stored and processed in the same material. The goal of the project is to enable a major improvement in artificial intelligence compute performance and power efficiency with the use of analog signal processing as compared to current digital approaches.

“This project is a perfect example of how new materials and architectures can be developed to enable new ways to accelerate artificial intelligence applications as classic Moore’s Law scaling slows,” said Steve Ghanayem, senior vice president of New Markets and Alliances at Applied Materials. “Applied has the industry’s broadest portfolio in materials engineering capabilities and is excited to be part of a team enabling breakthroughs for artificial intelligence.”

Today’s announcement was part of DARPA’s first annual ERI Summit in San Francisco. Applied Materials’ president and CEO, Gary Dickerson, delivered a keynote speech at the event highlighting the need for materials innovation in the AI era and calling for a new level of industry connectivity to speed progress across materials engineering, design and manufacturing.

Announced in September 2017, the ERI Materials & Integration programs seek to answer this question: Can we use the integration of unconventional electronics materials to enhance conventional silicon circuits and continue the progress in performance traditionally associated with scaling?

The Applied Materials team is part of the ERI Foundations Required for Novel Compute (FRANC) program, which seeks innovations that go beyond von Neumann compute architectures. Central is the design of circuits that leverage the properties of new materials and integration schemes to process data in ways that eliminate or minimize data movement. The novel compute topologies that come out of this effort could allow processing to happen where the data is stored with structures that are radically different from conventional digital logic processors, ultimately allowing for significant gains in compute performance.

Applied Materials, Inc. (Nasdaq:AMAT) is a developer of materials engineering solutions used to produce virtually every new chip and advanced display in the world.