Category Archives: Device Architecture

Imec, a research and innovation hub in nanoelectronics, energy and digital technology, within the partnership of EnergyVille, today announced a record result for its 4-terminal Perovskite/silicon tandem photovoltaic cell. With a power conversion efficiency of 27.1 percent, the new imec tandem cell beats the most efficient standalone silicon solar cell. Further careful engineering of the Perovskite material will bring efficiencies over 30% in reach.

Perovskite microcrystals are a promising material system to make high-performance thin-film solar cells. They can be processed into thin, light, semitransparent modules that can achieve a high power conversion efficiency, are inexpensive to produce, and have a high absorption efficiency for sunlight. Because they can be made semitransparent, perovskite solar cells and modules can also be used on top of silicon solar cells. When the Perovskite is carefully engineered, the absorbance in the Perovskite minimizes the thermal losses that occur in the silicon cell. As a result, a Perovskite-silicon tandem solar cell can potentially reach power conversion efficiencies above 30 percent.

Imec’s new record tandem cell uses a 0.13 cm² spin-coated Perovskite cell developed within our Solliance cooperation stacked on top of a 4 cm² industrial interdigitated back-contact (IBC) silicon cell in a 4-terminal configuration, which is known to have a higher annual energy yield compared to a 2-terminal configuration. Additionally, scaling up the tandem device by using a 4 cm2 perovskite module on a 4 cm2 IBC silicon cell, a tandem efficiency of 25.3% was achieved, surpassing the stand-alone efficiency of the silicon cell.

Manoj Jaysankar, doctoral researcher at imec/EnergyVille, adds: “We have been working on this tandem technology for two years now, and the biggest difference with previous versions is in the engineering and processing of the Perovskite absorber, tuning its bandgap to optimize the efficiency for tandem configuration with silicon.”

“Adding Perovskite on top of industrial silicon PV may prove to be the most cost-effective approach to further improve the efficiency of photovoltaics,” concludes Tom Aernouts, group leader for thin-film photovoltaics at imec/EnergyVille. “Therefore, we invite all companies in the PV value chain that are looking into higher efficiencies, to partner with us and explore this promising path.”

Toshiba Memory Corporation today announced that it has developed a prototype sample of 96-layer BiCS FLASH, its proprietary 3D flash memory, with 4-bit-per-cell (quad level cell, QLC) technology that boosts single-chip memory capacity to the highest level yet achieved.

Toshiba Memory will start to deliver samples to SSD and SSD controller manufacturers for evaluation from the beginning of September, and expects to start mass production in 2019.

The advantage of QLC technology is pushing the bit count for data per memory cell from three to four and significantly expanding capacity. The new product achieves the industry’s maximum capacity [1] of 1.33 terabits for a single chip which was jointly developed with Western Digital Corporation.

This also realizes an unparalleled capacity of 2.66 terabytes with a 16-chip stacked architecture in one package. The huge volumes of data generated by mobile terminals and the like continue to increase with the spread of SNS and progress in IoT, and the need to analyze and utilize that data in real time is expected to increase dramatically. That will require even faster than HDD, larger capacity storage and QLC products using the 96-layer process will contribute a solution.

A packaged prototype of the new device will be exhibited at the 2018 Flash Memory Summit in Santa Clara, California, USA from August 6th to 9th.

Looking to the future, Toshiba Memory will continue to improve memory capacity and performance and to develop 3D flash memories that meet diverse market needs, including the fast expanding data center storage market.

Rahul Goyal of Intel has been elected to a one-year term as board chair of Silicon Integration Initiative, a research and development joint venture that provides standard interoperability solutions for integrated circuit design tools. The election was held during Si2’s board meeting at the recent Design Automation Conference.

A member of the Si2 board since 2003, Goyal is vice president, Technology and Manufacturing Group and director, Research and Development Strategic Enabling for Intel. He has global responsibility for strategic sourcing, supply chain strategy, industry relations, ecosystem development, strategic collaborations, data analytics, and capacity management related to product development across Intel’s broad product portfolio. This includes software, system and semiconductor intellectual property, product development outsourcing services, electronic measurement solutions, electronic design automation software, prototyping and verification products used in all aspects of product design, validation and technology development.

Goyal joined Intel in 1989 and has held various technical and management positions in software engineering and technology development. His previous roles there include engineering director in the Design and Technology Solutions Group, director of the integrated silicon technology roadmap development in the Microprocessor Products Group, and senior engineering manager of mask operations.

Goyal holds a bachelor’s degree in electrical and electronics engineering from Birla Institute of Technology and Science, Pilani, India, and a master’s degree in computer engineering from Syracuse University, Syracuse, N.Y.

Working to address “hotspots” in computer chips that degrade their performance, UCLA engineers have developed a new semiconductor material, defect-free boron arsenide, that is more effective at drawing and dissipating waste heat than any other known semiconductor or metal materials.

This could potentially revolutionize thermal management designs for computer processors and other electronics, or for light-based devices like LEDs.

Illustration showing a schematic of a computer chip with a hotspot (bottom); an electron microscope image of defect-free boron arsenide (middle); and an image showing electron diffraction patterns in boron arsenide. Credit: Hu Research Lab / UCLA Samueli

The study was recently published in Science and was led by Yongjie Hu, UCLA assistant professor of mechanical and aerospace engineering.

Computer processors have continued to shrink down to nanometer sizes where today there can be billions of transistors on a single chip. This phenomenon is described under Moore’s Law, which predicts that the number of transistors on a chip will double about every two years. Each smaller generation of chips helps make computers faster, more powerful and able to do more work. But doing more work also means they’re generating more heat.

Managing heat in electronics has increasingly become one of the biggest challenges in optimizing performance. High heat is an issue for two reasons. First, as transistors shrink in size, more heat is generated within the same footprint. This high heat slows down processor speeds, in particular at “hotspots” on chips where heat concentrates and temperatures soar. Second, a lot of energy is used to keep those processors cool. If CPUs did not get as hot in the first place, then they could work faster and much less energy would be needed to keep them cool.

The UCLA study was the culmination of several years of research by Hu and his students that included designing and making the materials, predictive modeling, and precision measurements of temperatures.

The defect-free boron arsenide, which was made for the first time by the UCLA team, has a record-high thermal conductivity, more than three-times faster at conducting heat than currently used materials, such as silicon carbide and copper, so that heat that would otherwise concentrate in hotspots is quickly flushed away.

“This material could help greatly improve performance and reduce energy demand in all kinds of electronics, from small devices to the most advanced computer data center equipment,” Hu said. “It has excellent potential to be integrated into current manufacturing processes because of its semiconductor properties and the demonstrated capability to scale-up this technology. It could replace current state-of-the-art semiconductor materials for computers and revolutionize the electronics industry.”

The study’s other authors are UCLA graduate students in Hu’s research group: Joonsang Kang, Man Li, Huan Wu, and Huuduy Nguyen.

In addition to the impact for electronic and photonics devices, the study also revealed new fundamental insights into the physics of how heat flows through a material.

“This success exemplifies the power of combining experiments and theory in new materials discovery, and I believe this approach will continue to push the scientific frontiers in many areas, including energy, electronics, and photonics applications,” Hu said.

In its upcoming Mid-Year Update to The McClean Report 2018 (to be released at the end of July), IC Insights forecasts that the 2018 global electronic systems market will grow 5% to $1,622 billion while the worldwide semiconductor market is expected to surge by 14% this year to $509.1 billion, exceeding the $500.0 billion level for the first time.  If the 2018 forecasts come to fruition, the average semiconductor content in an electronic system will reach 31.4%, breaking the all-time record of 28.8% that was set in 2017 (Figure 1).

Figure 1

Historically, the driving force behind the higher average annual growth rate of the semiconductor industry as compared to the electronic systems market is the increasing value or content of semiconductors used in electronic systems.  With global unit shipments of cellphones (-1%), automobiles (3%), and PCs (-1%) forecast to be weak in 2018, the disparity between the moderate growth in the electronic systems market and high growth of the semiconductor market is directly due to the increasing content of semiconductors in electronic systems.

While the trend of increasing semiconductor content has been evident for the past 30 years, the big jump in the average semiconductor content in electronic systems in 2018 is expected to be primarily due to the huge surge in DRAM and NAND flash ASPs and average electronic system sales growth this year. After slipping to 30.2% in 2020, the semiconductor content percentage is expected to climb to a new high of 31.5% in 2022.  IC Insights does not anticipate the percentage will fall below 30% any year through the forecast period.

The trend of increasingly higher semiconductor value in electronic systems has a limit.  Extrapolating an annual increase in the percent semiconductor figure indefinitely would, at some point in the future, result in the semiconductor content of an electronic system reaching 100%.  Whatever the ultimate ceiling is, once it is reached, the average annual growth for the semiconductor industry will closely track that of the electronic systems market (i.e., about 4%-5% per year).

Micron (Nasdaq:MU) and Intel today announced an update to their 3D XPoint™ joint development partnership, which has resulted in the development of an entirely new class of non-volatile memory with dramatically lower latency and exponentially greater endurance than NAND memory.

The companies have agreed to complete joint development for the second generation of 3D XPoint technology, which is expected to occur in the first half of 2019. Technology development beyond the second generation of 3D XPoint technology will be pursued independently by the two companies in order to optimize the technology for their respective product and business needs.

The two companies will continue to manufacture memory based on 3D XPoint technology at the Intel-Micron Flash Technologies (IMFT) facility in Lehi, Utah.

“Micron has a strong track record of innovation with 40 years of world-leading expertise in memory technology development, and we will continue driving the next generations of 3D XPoint technology,” said Scott DeBoer, executive vice president of Technology Development at Micron. “We are excited about the products that we are developing based on this advanced technology which will allow our customers to take advantage of unique memory and storage capabilities. By developing 3D XPoint technology independently, Micron can better optimize the technology for our product roadmap while maximizing the benefits for our customers and shareholders.”

“Intel has developed a leadership position delivering a broad portfolio of Optane products across client and data center markets with strong support from our customers,” said Rob Crooke, senior vice president and general manager of Non-Volatile Memory Solutions Group at Intel Corporation. “Intel Optane’s direct connection to the world’s most advanced computing platforms is achieving breakthrough results in IT and consumer applications. We intend to build on this momentum and extend our leadership with Optane, which combined with our high-density 3D NAND technology, offer the best solutions for today’s computing and storage needs.”

Silicon Labs (NASDAQ: SLAB), a provider of silicon, software and solutions for a smarter, more connected world, announces two new executive appointments. Daniel Cooley has been named Senior Vice President and Chief Strategy Officer. In this new role, Mr. Cooley will focus on Silicon Labs’ overall growth strategy, business development, new technologies and emerging markets. Matt Johnson, a semiconductor veteran with more than 15 years of industry experience, joins Silicon Labs as Senior Vice President and General Manager of IoT products. Both executives will report to Tyson Tuttle, CEO.

Mr. Cooley has led Silicon Labs’ IoT business for the past four years. Under his leadership, the company built an industry-leading portfolio of secure connectivity solutions, with IoT revenue now exceeding a $100 million per quarter run rate. Mr. Cooley joined Silicon Labs in 2005 as a chip design engineer developing broadcast audio products and short-range wireless devices. Over the years, he has served in various senior management, engineering and product management roles at the company’s Shenzhen, Singapore, Oslo and Austin sites. The new role leverages Mr. Cooley’s proven talents in strategy and business development.

Mr. Johnson will lead Silicon Labs’ IoT business including the development and market success of the company’s broad portfolio of wireless products, microcontrollers, sensors, development tools and wireless software. Mr. Johnson has a track record of growing revenue and leading large global teams, and he brings a deep understanding of analog, MCU and embedded software businesses to Silicon Labs. Previously, he served as Senior Vice President and General Manager of automotive processing products and software development at NXP Semiconductors/Freescale, as well as SVP and General Manager of mobile solutions at Fairchild Semiconductor.

“With these executive appointments, we are expanding our ability to execute on large and growing market opportunities in the IoT,” said Tyson Tuttle, CEO of Silicon Labs. “Together, these two talented leaders will help Silicon Labs scale the business to the next level and focus on future growth.”

Intel to acquire eASIC


July 16, 2018

The following is an opinion editorial provided by Dan McNamara of Intel Corporation.

Intel is competing to win in the largest-ever addressable market for silicon, which is being driven by the explosion of data and the need to process, analyze, store and share it. This dynamic is fueling demand for computing solutions of all kinds. Of course Intel is known for world-class CPUs, but today we offer a broader range of custom computing solutions to help customers tackle all kinds of workloads – in the cloud, over the network and at the edge. In recent years, Intel has expanded its products and introduced breakthrough innovations in memory, modems, purpose-built ASICs, vision processing units and field programmable gate arrays (FPGAs).

FPGAs are experiencing expanding adoption due to their versatility and real-time performance. These devices can be programmed anytime – even after equipment has been shipped to customers. FPGAs contain a mixture of logic, memory and digital signal processing blocks that can implement any desired function with extremely high throughput and very low latency. This makes FPGAs ideal for many critical cloud and edge applications, and Intel’s Programmable Solutions Group revenue has grown double digits as customers use FPGAs to accelerate artificial intelligence, among other applications.

Customers designing for high-performance, power-constrained applications in market segments like wireless, networking and the internet of things (IoT) sometimes begin deployments with FPGAs for fast time-to-market and flexibility. They then migrate to devices called structured ASICs, which can be used to optimize performance and power-efficiency. A structured ASIC is an intermediary technology between FPGAs and ASICs. It offers performance and power-efficiency closer to a standard-cell ASIC, but with the faster design time and at a fraction of the non-recurring engineering costs associated with ASICs.

Today, I’m excited to announce that Intel plans to expand its programmable solutions portfolio to include structured ASICs by acquiring eASIC®, a leading structured ASICs provider headquartered in Santa Clara, California. eASIC has a proven, 19-year success record, leading products and a world-class team, which will join Intel’s Programmable Solutions Group. The addition of eASIC will help us meet customers’ diverse needs of time-to-market, features, performance, cost, power and product life cycles.

This combination brings together the best-in-class technologies from both companies to provide customers with more choice, faster time-to-market and lower development costs. Specifically, having a structured ASICs offering will help us better address high-performance and power-constrained applications that we see many of our customers challenged with in market segments like 4G and 5G wireless, networking and IoT. We can also provide a low-cost, automated conversion process from FPGAs (including competing FPGAs) to structured ASICs.

Longer term, we see an opportunity to architect a new class of programmable chip that takes advantage of Intel’s Embedded Multi-Die Interconnect Bridge (EMIB) technology to combine Intel FPGAs with structured ASICs in a system in package solution. Together with partners and customers, Intel and eASIC expect to deliver industry-leading solutions.

We expect to complete the acquisition in the third quarter of 2018 after customary closing conditions are met. We look forward to serving eASIC’s current customers and to offering Intel customers a new solution for unlocking the power of data.

Australian scientists have achieved a new milestone in their approach to creating a quantum computer chip in silicon, demonstrating the ability to tune the control frequency of a qubit by engineering its atomic configuration. The work has been published in Science Advances.

A team of researchers from the Centre of Excellence for Quantum Computation and Communication Technology (CQC2T) at UNSW Sydney have successfully implemented an atomic engineering strategy for individually addressing closely spaced spin qubits in silicon.

The frequency spectrum of an engineered molecule. The three peaks represent three different configurations of spins within the atomic nuclei, and the distance between the peaks depends on the exact distance between atoms forming the molecule. Credit: Dr. Sam Hile

The researchers built two qubits – one an engineered molecule consisting of two phosphorus atoms with a single electron, and the other a single phosphorus atom with a single electron – and placed them just 16 nanometres apart in a silicon chip.

By patterning a microwave antenna above the qubits with precision alignment, the qubits were exposed to frequencies of around 40GHz. The results showed that when changing the frequency of the signal used to control the electron spin, the single atom had a dramatically different control frequency compared to the electron spin in the molecule of two phosphorus atoms.

The UNSW researchers collaborated closely with experts at Purdue University, who used powerful computational tools to model the atomic interactions and understand how the position of the atoms impacted the control frequencies of each electron even by shifting the atoms by as little as one nanometre.

“Individually addressing each qubit when they are so close is challenging,” says UNSW Scientia Professor Michelle Simmons, Director CQC2T and co-author of the paper.

“The research confirms the ability to tune neighbouring qubits into resonance without impacting each other.”

Creating engineered phosphorus molecules with different separations between the atoms within the molecule allows for families of qubits with different control frequencies. Each molecule can be operated individually by selecting the frequency that controls its electron spin.

“We can tune into this or that molecule – a bit like tuning in to different radio stations,” says Sam Hile, lead co-author of the paper and Research Fellow at UNSW.

“It creates a built-in address which will provide significant benefits for building a silicon quantum computer.”

Tuning in and individually controlling qubits within a 2 qubit system is a precursor to demonstrating the entangled states that are necessary for a quantum computer to function and carry out complex calculations.

These results show how the team – led by Professor Simmons – have further built on their unique Australian approach of creating quantum bits from precisely positioned individual atoms in silicon.

By engineering the atomic placement of the atoms within the qubits in the silicon chip, the molecules can be created with different resonance frequencies. This means that controlling the spin of one qubit will not affect the spin of the neighbouring qubit, leading to fewer errors – an essential requirement for the development of a full-scale quantum computer.

“The ability to engineer the number of atoms within the qubits provides a way of selectively addressing one qubit from another, resulting in lower error rates even though they are so closely spaced,” says Professor Simmons.

“These results highlight the ongoing advantages of atomic qubits in silicon.”

This latest advance in spin control follows from the team’s recent research into controllable interactions between two qubits.

Broadcom Inc. (NASDAQ: AVGO), a semiconductor device supplier to the wired, wireless, enterprise storage, and industrial end markets, and CA Technologies (NASDAQ: CA), one of the world’s leading providers of information technology (IT) management software and solutions, today announced that the companies have entered into a definitive agreement under which Broadcom has agreed to acquire CA to build one of the world’s leading infrastructure technology companies.

Under the terms of the agreement, which has been approved by the boards of directors of both companies, CA’s shareholders will receive $44.50 per share in cash. This represents a premium of approximately 20% to the closing price of CA common stock on July 11, 2018, the last trading day prior to the transaction announcement, and a premium of approximately 23% to CA’s volume-weighted average price (“VWAP”) for the last 30 trading days. The all-cash transaction represents an equity value of approximately $18.9 billion, and an enterprise value of approximately $18.4 billion.

Hock Tan, President and Chief Executive Officer of Broadcom, said, “This transaction represents an important building block as we create one of the world’s leading infrastructure technology companies. With its sizeable installed base of customers, CA is uniquely positioned across the growing and fragmented infrastructure software market, and its mainframe and enterprise software franchises will add to our portfolio of mission critical technology businesses. We intend to continue to strengthen these franchises to meet the growing demand for infrastructure software solutions.”

“We are excited to have reached this definitive agreement with Broadcom,” said Mike Gregoire, CA Technologies Chief Executive Officer. “This combination aligns our expertise in software with Broadcom’s leadership in the semiconductor industry. The benefits of this agreement extend to our shareholders who will receive a significant and immediate premium for their shares, as well as our employees who will join an organization that shares our values of innovation, collaboration and engineering excellence. We look forward to completing the transaction and ensuring a smooth transition.”

The transaction is expected to drive Broadcom’s long-term Adjusted EBITDA margins above 55% and be immediately accretive to Broadcom’s non-GAAP EPS. On a combined basis, Broadcom expects to have last twelve months non-GAAP revenues of approximately $23.9 billion and last twelve months non-GAAP Adjusted EBITDA of approximately $11.6 billion.

As a global leader in mainframe and enterprise software, CA’s solutions help organizations of all sizes develop, manage, and secure complex IT environments that increase productivity and enhance competitiveness. CA leverages its learnings and development expertise across its Mainframe and Enterprise Solutions businesses, resulting in cross enterprise, multi-platform support for customers. The majority of CA’s largest customers transact with CA across both its Mainframe and Enterprise Solutions portfolios. CA benefits from predictable and recurring revenues with the average duration of bookings exceeding three years. CA operates across 40 countries and currently holds more than 1,500 patents worldwide, with more than 950 patents pending.