Category Archives: Device Architecture

Electrical circuits are constantly being scaled down and extended with specific functions. A new method now allows electrical contact to be established with simple molecules on a conventional silicon chip. The technique promises to bring advances in sensor technology and medicine, as reported in the journal Nature by chemists from the University of Basel and researchers from IBM Research – Zurich in Rüschlikon.

To further develop semiconductor technology, the field of molecular electronics is seeking to manufacture circuit components from individual molecules instead of silicon. Because of their unique electronic properties, molecules are suited to applications that cannot be implemented using conventional silicon technology. However, this requires reliable and inexpensive methods for creating electrical contacts at the two ends of a molecule.

The ability to produce thousands of elements

Researchers from the University of Basel and IBM Research – Zurich have now developed a technique that allows electrical contact to individual molecules to be established. Thousands of stable metal-molecule-metal components can be produced simultaneously by depositing a film of nanoparticles onto the molecules, without compromising the properties of the molecules. This approach was demonstrated using alkane-dithiol compounds, which are made up of carbon, hydrogen, and sulfur.

Tiny pores were filled with molecules and brought into electrical contact via a platinum electrode from below and a gold nanoparticle electrode from above. Credit: IBM Research – Zurich

The researchers used a type of sandwich construction in which an interlayer of molecules is brought into contact with metallic electrodes from above and below. The lower electrode consists of a layer of platinum, which is coated with a layer of non-conducting material. Tiny pores are then etched into this layer to produce arbitrary patterns of compartments of different sizes, inside which there is an electrical contact with the platinum electrode.

Self-assembled monolayers

The researchers then took advantage of the ability of certain molecules to self-assemble. Onto the pattern of pores, they applied a solution containing alkane-dithiol molecules, which self-assemble into the pores, forminga densely packed monolayer film. Within this film, the individual molecules exhibit a regular arrangement and an electrical connection with the lower platinum electrode. Electrical contact with the molecular layer is established via an upper electrode made of gold nanoparticles.

The new technique largely resolves the issues that previously hampered the creation of electrical contacts to molecules – such as high contact resistance or short circuits by filaments penetrating the film. Building blocks fabricated by this method can be operated under standard conditions and provide long-term stability. Moreover, the method can be applied to a variety of other molecular systems and opens up new avenues for integrating molecular compounds into solid-state devices. Its applications could include new types of instruments in the fields of sensor technology and medicine.

“Our approach will help speed up the development of chemically fabricated and controllable electronic and sensor components,” says Professor Marcel Mayor of the Department of Chemistry at the University of Basel. The project received significant funding from the National Center of Competence in Research (NCCR) for Molecular Systems Engineering, in which the University of Basel and ETH Zurich are leading houses.

By Ed Korczynski

To fulfill the promise of the Internet of Things (IoT), the world needs low-cost high-bandwidth radio-frequency (RF) chips for 5th-generation (5G) internet technology. Despite standards not being completely defined yet it is clear that 5G hardware will have to be more complex than 4G kit, because it will have to provide a total solution that is ultra-reliable with at least 10 Gb/second bandwidth. A significant challenge remains in developing new high-speed transistor technologies for RF communications with low power to allow IoT “edge” devices to operate reliably off of batteries.

At the most recent Imec Technology Forum in Antwerp, Belgium, Nadine Collaert, Distinguished MTS of imec, discussed recent research results from the consortium’s High-Speed Analog and RF Program. In addition to working on core transistor fabrication technology R&D, imec has also been working on system-technology co-integration (STCO) and design-technology co-integration (DTCO) for RF applications.

Comparing the system specifications needed for mobile handsets to those for base-stations, transmitter power consumption should be 10x lower, while the receiver power consumption needs to be 2x lower. Today using silicon CMOS transistors, four power amplifiers alone consume 65% of a transmitter chip’s power. Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) built using compound semiconductors such as gallium-arsenide (GaAs), gallium-nitride (GaN), or indium-phosphide (InP) provide excellent RF device results. However, compared to making CMOS chips on silicon, HBT and HEMT manufacturing on compound semiconductor substrates is inherently expensive and difficult.

Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) both rely upon the precise epitaxial growth of semiconductor layers, and such growth is easier when the underlying substrate material has similar atomic arrangement. While it is much more difficult to grow epi-layers of compound semiconductors on silicon wafers, imec does R&D using 300-mm diameter silicon substrates with a goal of maintaining device quality while lowering production costs. The Figure shows cross-sections of the two “tracks” of III-V and GaN transistor materials being explored by imec for future RF chips.

III-V on Silicon and GaN-on-Silicon RF device cross-sections, showing work on both Heterogeneous Bipolar Transistors (HBT) and High Electron Mobility Transistors (HEMT) for 5G applications. (Source: imec)

Imec’s High-Speed Analog/RF Program objectives include the following:

  • High-speed III-V RF devices using low-cost, high-volume silicon-compatible processes and modules,
  • Co-optimization with advance silicon CMOS to reduce form factor and enable power-efficient systems with higher performance, and
  • Technology-circuit design co-optimization to enable complex RF-FEM modules with heterogeneous integration.

5G technology deployment will start with speeds below 6GHz,  because technologies in that range have already been proven and the costs are known. However, after five years the frequency will change to the “mm-wave” range with the first wavelength band at ~28GHz. GaN material with a wide bandgap and high charge-density has been a base-station technology, and it could be an ideal material for low-power mm-wave RF devices for future handsets.

This R&D leverages the III-V on silicon capability that has been developed by imec for CMOS:Photonic integration. RF transistors could be stacked over CMOS transistors using either wafer- or die-stacking, or both could be monolithically co-integrated on one silicon chip. Work on monolithic integration of GaN-on-Silicon is happening now, and could also be used for photonics where faster transistors can improve the performance of optical links.

The Mid-Year Update to the 2018 McClean Report revises IC Insights’ worldwide economic and IC industry forecasts through 2022 that were originally presented in The 2018 McClean Report issued in January.

The Figure shows that IC Insights forecasts that China-headquartered companies will spend $11.0 billion in semiconductor industry capex in 2018, which would represent 10.6% of the expected worldwide outlays of $103.5 billion.  Not only would this amount be 5x what the Chinese companies spent only three years earlier in 2015, but it would also exceed the combined semiconductor industry capital spending of Japan- and Europe-headquartered companies this year.

Since adopting the fab-lite business model, the three major European producers have represented a very small share of total semiconductor industry capital expenditures and are forecast to account for only 4% of global spending in 2018 after representing 8% of worldwide capex in 2005.  Although there may be an occasional spike in capital spending from European companies (e.g., the surge in spending from ST and AMS in 2017), IC Insights believes that Europe-headquartered companies will represent only 3% of worldwide semiconductor capital expenditures in 2022.

It should be noted that several Japanese semiconductor companies have also transitioned to a fab-lite business model (e.g., Renesas, Sony, etc.).  With strong competition reducing the number and strength of Japanese semiconductor manufacturers, the loss of its vertically integrated businesses and thus missing out on supplying devices for several high-volume end-use applications, and its collective shift toward fab-lite business models, Japanese companies have greatly reduced their investment in new wafer fabs and equipment. In fact, Japanese companies are forecast to represent only 6% of total semiconductor industry capital expenditures in 2018, a big decline from the 22% share they held in 2005 and an even more precipitous drop from the 51% share they held in 1990.

Although China-headquartered pure-play foundry SMIC has been part of the list of major semiconductor industry capital spenders for quite some time, there are four additional Chinese companies that are forecast to become significant semiconductor industry spenders this year and next—memory suppliers XMC/YMTC, Innotron, JHICC, and pure-play foundry Shanghai Huali.  Each of these companies is expected to spend a considerable amount of money equipping and ramping up their new fabs in 2018 and 2019.

Due to the increased spending by startup China-based memory manufacturers, IC Insights believes that the Asia-Pac/Others share of semiconductor industry capital spending will remain over 60% for at least the next couple of years.

IC Insights will release its 200+ page Mid-Year Update to the 2018 McClean Report later this month. The Mid-Year Update revises IC Insights’ worldwide economic and IC industry forecasts through 2022 that were originally published in The 2018 McClean Report issued in January of this year.

Figure 1 compares the estimated required capex needed to increase NAND flash bit volume shipments 40% per year, sourced from a chart from Micron’s 2018 Analyst and Investor Event in May of this year, versus the annual capex targeting the NAND flash market segment using IC Insights’ data. As shown, Micron believes that the industry capex needed to increase NAND flash bit volume production by 40% more than doubled from $9 billion in 2015 to $22 billion only two years later in 2017! This tremendous surge in required capital was driven by the move to 3D NAND from planar NAND since 3D NAND requires much more fab equipment and additional cleanroom space to process the additional layers of the device as compared to planar NAND.

Most of the five major NAND flash suppliers have stated that they believe that NAND bit volume demand growth will average about 40% per year over the next few years. Figure 1 shows that the capex needed to support a 40% increase in NAND bit volume shipments was exceeded by 27% last year and is forecast to exceed the amount needed by another 41% this year (NAND bit volume shipments increased 41% in 2017 but 1H18/1H17 bit volume shipments were up only 30%). As a result, it is no surprise that NAND flash prices have already softened in early 2018. Moreover, the pace of the softening is expected to pick up in the second half of this year and continue into 2019.

Historical precedent in the memory market shows that too much spending usually leads to overcapacity and subsequent pricing weakness. With Samsung, SK Hynix, Micron, Intel, Toshiba/Western Digital/SanDisk, and XMC/Yangtze River Storage Technology all planning to significantly ramp up 3D NAND flash capacity over the next couple of years (with additional new Chinese producers possibly entering the market), IC Insights believes that the risk for significantly overshooting 3D NAND flash market demand is very high and growing.

Figure 1

By Ed Korczynski

As the commercial IC fabrication industry continues to shrink field-effect transistor (FET) sizes, 2D planar structures evolved into 3D fins which are now evolving into 3D stacks of 2D nano-sheets. While some researchers continue to work on integrating non-silicon “alternate channel” materials into finFETs for next generation logic ICs, published results from labs around the world now show that nano-wires or nano-sheets of silicon will likely follow silicon finFETs in high-volume manufacturing (HVM) fabs. 

Today’s finFETs are formed using self-aligned multi-patterning (SAMP) process flows with argon-fluoride immersion (ArFi) deep ultra-violet (DUV) steppers to provide arrays of equal-width lines. A block-mask can then pattern sets of lines into different numbers of fins per transistor to allow for different maximum current flows across the chip. When considering the next CMOS device structure to replace finFETs in commercial HVM we must anticipate the need to retain different current flows (ION) across the IC.

Gate-all-around (GAA) FETs can provide outstanding ION/IOFFratios, and future logic ICs could be built using either horizontal or vertical GAA devices. While vertical-GAA transistors have been explored for memory chips, their manufacturing process flows are significantly different from  those used to form finFETs. In contrast, horizontal-GAA FETs processing can be seen as a logical extension of flows already developed and refined for fin structuring.

“With a number of scaling boosters, the industry will be able to extend finFET technology to the 7 or even 5nm node,” said An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the finFET process steps.”

The figure shows simplified cross-sections of a finFET with fin height (FH) of 50 nm along with two different stacks of lateral nano-sheets (LNS, also known as horizontal nano-sheets or HNS), where the current flows would be normal to the cross-section. HNS are variations of horizontal nano-wires (HNW) with the wires widened, shown as 11nm and 21nm in the figure. The HNS are epitaxial-silicon grown separated by sacrificial sacrificial silicon-germanium (SiGe) spacer layers.

Cross-sectional schematics of idealized (left) 50nm high finFET, (center) 5nm high by 11nm wide lateral-nano-sheets at 12-18nm vertical pitch, and (right) lateral-nano-sheets 21nm wide. (Source: imec)

In an exclusive interview with Solid State Technology, Steegen discussed a few details of the process extensions needed to convert finFETs into HNS-FETs. The same work-function ALD metals can be used to tune threshold voltages such that one epi-stack process can grow silicon for both n-type and p-type FETs. Happily, no new epitaxial reactors nor precursor materials are needed. Isotropic etch of the SiGe vertical spacers, and then filling the spaces with a dielectric deposition may be the only new unit-processes needed.

Alternate channel wires and sheets

At the 2018 Symposia on VLSI Technology and Circuits, imec presented two papers on germanium as an alternate channel material for nanowire pFET devices. In the first paper they studied the electrical properties of strained germanium nanowire pFETs as high-end analog and high-performance digital solutions. The second paper demonstrated vertically-stacked GAA highly-strained germanium nanowire pFETs.

The commercial IC fab industry has considered use of alternate channels for planar devices and for finFETs, yet so far has found extensions of silicon to work well-enough for pFETs. Likewise, the first generation of HNS will likely use silicon channels for both nFETs and pFETs. Germanium GAA pFETs thus represent the ability to shrink HNS devices for future nodes.

By Pete Singer

Many new innovations were discussed at imec’s U.S. International Technology Forum (ITF) on Monday at the Grand Hyatt in San Francisco, including quantum computing, artificial intelligence, sub-3nm logic, memory computing, solid-state batteries, EUV, RF and photonics, but perhaps the most interesting was new technology that enables human cells, tissues and organs to be grown and analyzed on-chip.

After an introduction by SEMI President Ajit Monacha – who said he believes the semiconductor industry will reach $1 trillion in market size by 2030 (“there’s no shortage of killer applications,” he said) — Luc Van den hove, president and CEO of imec, kicked off the afternoon session speaking about many projects underway that bring leading microelectronics technologies to bear on today’s looming healthcare crisis. “We all live longer than ever before and that’s fantastic,” he said. “But by living longer we also spend a longer part of our life being ill. What we need is a shift from extending lifespan to extending healthspan. What we need is to find ways to cure and prevent some of these diseases like cancer, like heart diseases and especially dementia.”

Today, drug development is so time-consuming and costly, is because of the insufficiency of the existing methodologies for drug screening assays. These current assays are based on poor cell models that limit the quality of the resulting data, and result in inadequate biological relevance. Additionally, there is a lack of spatial resolution of the assays, resulting in the inability to screen single cells in a cell culture. “It is rather slow, it is quite labor intensive and it provides limited information,” Van den hove said. “With our semiconductor platform we have developed recently a multi-electrode array (MEA) chip on which we can grow cells, in which we can grow tissue and organs. We can monitor processes that are happening within the cells or between the cells during massive drug testing.”

The MEA (see Figure) packs 16,384 electrodes, distributed over 16 wells, and offers multiparametric analysis. Each of the 1,024 electrodes in a well can detect intracellular action potentials, aside from the traditional extracellular signals. Further, imec’s chip is patterned with microstructures to allow for a structured cell growth mimicking a specific organ.

A novel organ-on-chip platform for pharmacological studies with unprecedented signal quality. It fuses imec’s high-density multi-electrode array (MEA)-chip with a microfluidic well plate, developed in collaboration with Micronit Microtechnologies, in which cells can be cultured, providing an environment that mimics human physiology.

Earlier this year, in May at imec’s ITF forum in Europe, Veerle Reumers, project leader at imec, explained how the MEA works: “By using grooves, heart cells can for example grow into a more heart-like tissue. In this way, we fabricate miniature hearts-on-a-chip, making it possible to test the effect of drugs in a more biologically relevant context. Imec’s organ-on-chip platform is the first system that enables on-chip multi-well assays, which means that you can perform different experiments or – in other words – analyze different compounds, in parallel on a single chip,” he explained. “This is a considerable increase in throughput compared to current single-well MEAs and we aim to further increase the throughput by adding more wells in a system.”

Van den hove said they have been testing the chip. “The beauty of the semiconductor platform is that we can, because of the miniaturization capability, parallelize an enormous amount of this testing and accelerate drug testing. We can measure what we never measured before, at speeds that you couldn’t think of before.”

He added that imec recently embarked on a new initiative aimed to cure dementia called Mission Lucidity. “Together with some of our clinical biomedical research teams, we are on a mission to decode dementia, to develop a cure to prevent this disease,” he said.

The MEA will be one tool used in the initiative, but also coming into play will be the groups neuroprobes — which Van den hove said are among the world’s most advanced probes and are being used by nearly all the leading neuroscience research teams – along with next generation wearables. “By combining these tools, we want to better understand the processes that are happening in the brain. We can measure those processes with much higher resolution than what could be done before. This may be able to detect the onset disease earlier on. By administering the right medication earlier, we hope to be able to prevent the disease from further progressing,” he said.

BY PAUL VAN DER HEIDE, director of materials and components analysis, imec, Leuven, Belgium

To keep up with Moore’s Law, the semiconductor industry continues to push the envelope in developing new device architectures containing novel materials. This in turn pushes the need for new solid-state analytical capabilities, whether for materials characterization or inline metrology. Aside from basic R&D, these capabilities are established at critical points of the semiconductor device manufacturing line, to measure, for example, the thickness and composition of a thin film, dopant profiles of transistor’s source/drain regions, the nature of defects on a wafer’s surface, etc. This approach is used to reduce “time to data”. We cannot wait until the end of the manufacturing line to know if a device will be functional or not. Every process step costs money and a fully functional device can take months to fabricate. Recent advances in instrumentation and computational power have opened the door to many new, exciting analytical possibilities.

One example that comes to mind concerns the development of coherent sources. So far, coherent photon sources have been used for probing the atomic and electronic structure of materials, but only within large, dedicated synchrotron radiation facilities. Through recent developments, table top coherent photon sources have been introduced that could soon see demand in the semiconductor lab/fab environment.

The increased computational power now at our finger tips is also allowing us to make the most of these and other sources through imaging techniques such as ptychography. Ptychog- raphy allows for the complex patterns resulting from coherent electron or photon interaction with a sample to be processed into recognizable images to a resolution close to the sources wavelength without the requirement of lenses (lenses tend to introduce aberrations). Potential application areas extend from non-destructive imaging of surface and subsurface structures, to probing chemical reactions at sub femto-second timescales.

Detector developments are also benefiting many analytical techniques presently used. As an example, transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) can now image, with atomic resolution, heavy as well as light elements. Combining this with increased computational power, allows for further devel- opment of imaging approaches such as tomography, holography, ptychography, differential phase contrast imaging, etc. All of which allow TEM/STEM to not only look at atoms in e.g. 2D materials such as MoS2 in far greater detail, but also opens the possibility to map electric fields and magnetic domains to unprecedented resolution.

The semiconductor industry is evolving at a very rapid pace. Since the beginning of the 21st century, we have seen numerous disruptive technologies emerge; technologies that need to serve is an increasingly fragmented applications space. It’s no longer solely about ‘the central processing unit (CPU)’. Other applications ranging from the internet of things, autonomous vehicles, wearable human-electronics interface, etc., are being pursued, each coming with unique requirements and analytical needs.

Looking ten to fifteen years ahead, we will witness a different landscape. Although I’m sure that existing techniques such as TEM/STEM will still be heavily used – probably more so than we realize now (we are already seeing TEM/STEM being extended into the fab). We will also see developments that will push the boundaries of what is possible. This would range from the increased use of hybrid metrology (combining results from multiple different analytical techniques and process steps) to the development of new innovative approaches.

To illustrate the latter, I take the example of secondary ion mass spectrometry (SIMS). With SIMS, an energetic ion beam is directed at the solid sample of interest, causing atoms in the near surface region to leave this surface. A small percentage of them are ionized, and pass through a mass spectrometer which separates the ions from one another according to their mass to charge ratio. When this is done in the dynamic-SIMS mode, a depth profile of the sample’s composition can be derived. Today, with this technique, we can’t focus the incoming energetic ion beam into a confined volume, i.e. onto a spot that approaches the size of a transistor. But at imec, novel concepts were intro- duced, resulting in what are called 1.5D SIMS and self-focusing SIMS (SF-SIMS). These approaches are based on the detection of constituents within repeatable array structures, giving averaged and statistically significant information. This way, the spatial resolution limit of SIMS was overcome.

And there are exciting developments occurring here at imec in other analytical fields such as atom probe tomography (APT), photoelectron spectroscopy (PES), Raman spectroscopy, Rutherford back scattering (RBS), scanning probe microscopy (SPM), etc. One important milestone has been the development of Fast Fourier Transform-SSRM (FFT-SSRM) at imec. This allows one to measure carrier distributions in FinFETs to unparalleled sensitivity.

Yet, probably the biggest challenge materials characterization and inline metrology face over the next ten to fifteen years will be how to keep costs down. Today, we make use of highly specialized techniques developed on mutually exclusive and costly platforms. But why not make use of micro-electro-mechanical systems (MEMS) that could simultaneously perform analysis in a highly parallel fashion, and perhaps even in situ? One can imagine scenarios in which an army of such units could scan an entire wafer in the fraction of the time it takes now, or alternatively, the incorporation of such units into wafer test structure regions.

BY DEBRA VOGLER, SEMI, Milpitas, CA

With chipmakers looking toward 5nm manufacturing, it’s clear that traditional scaling is not dead but continuing in combination with other technologies. The industry sees scaling enabled by 3D architectures such as die stacking and the stacking of very small geometry wafers. Interconnect scaling also comes into play. This year’s Scaling Technologies TechXPOT at SEMICON West (Scaling Every Which Way! – Thursday, July 12, 2:00PM-4:00PM) will provide an update on the evolution of scaling and describe how the various players (foundry, IDM, fabless, and application developers) are jockeying for innovation leadership. As a prelude to the event, SEMI asked speakers to provide insights on important scaling trends. For a full list of speakers and program agenda, visit http://www.semiconwest.org/programs-catalog/scaling-every-which-way.

Challenges for gate-all-around (GAA) and FinFET devices

Common performance boosters for gate-all-around (GAA) FETs and FinFETs include lower access resistance, lower parasitic capacitance, and stress. “However, one specific performance booster that only applies to GAA is the reduction of the spacing between the vertical wires or sheets,” says Diederik Verkest, imec distinguished member of technical staff, Semiconductor Technology and Systems.

“This reduces parasitic capacitance without affecting drive current and hence benefits both performance and power.” He further notes that imec demonstrated the first stacked gate-all-around (GAA) devices in scaled nodes. “In fact, we are the only ones that published working circuits – ring oscillators in a scaled node using industry-standard processes – in our case replacement metal gate (RMG), and embedded in situ doped source/drain (S/D) epitaxy.”

“There are two elements of the stacked GAA architecture that need to be addressed,” says Verkest. “The first is that this architecture uses epitaxially-grown layers of Si and SiGe to define the device channel. The use of grown materials for the channel and the lattice mismatch between the two materials represent a departure from the traditional fabrication of CMOS devices, so the industry needs to develop and gain confidence in novel metrology that allows for good control of the layers and also proves their low defectivity.” The second aspect is the three-dimensional nature of the GAA devices. “During the processing of these devices, we have ‘non-line-of-sight’ hidden features that are difficult to control and characterize and may also lead to new defect mechanisms that would impact yield, and possibly product reliability.”

Huiming Bu, director, Advanced Logic/Memory Research – Integration and Device, IBM Research, Semiconductor Group, says that naming of technology nodes has been used extensively for marketing strategies in “foundry land,” but the designations have lost much of their meaning as technology scaling differentiators. “That said, when it comes to technology innovation and value proposition, IBM, in conjunction with Samsung and GLOBALFOUNDRIES, has developed the GAA NanoSheet transistor for 5nm to provide a full technology node scaling benefit in density, power and performance,” says Bu (FIGURE 1). The key parameters for intrinsic device optimization when scaling to the 3nm node, explains Bu, are the NanoSheet width for better electrostatic characteristics, and the number of sheets for increased current density. Also necessary are strain engineering for carrier transport enhancement, and interconnect innovations for parasitic RC reduction.

“Beyond that, the industry needs to look into something different, something more disruptive.”

Materials challenges

Materials challenges are also a concern as the industry moves to 5nm and below. “We see increasing complexity in the material systems that are being used,” explains Verkest. One example he cites in scaled FinFET or GAA technologies is the use of two to three layers of different materials–typically metals such as TiN – to which small amounts of other elements are added to set device characteristics such as the threshold voltage. “At the same time, the requirements for the thickness of these materials, driven by gate dimensions for example, or the distance between the wires, are increasingly challenging.” Other examples of materials challenges are the use of two to three different types of insulators in the middle-of-the- line, each with different etch contrasts. “We use novel materials such as carbon containing oxides or oxynitrides that have lower dielectric constants in order to boost the performance of circuits,” he says, noting that the materials list “is quite long.”

Several critical dimensions in transistors at advanced technology nodes have already reached a few monolayers of atoms, fueling expectations for innovation at the material level for transistor scaling, Bu notes. “The other argument is that there is a growing gap between computing demand and the slowdown of technology advancement driven by conventional scaling,” says Bu. One trend that addresses this gap is integrating more computing functions that make the technology solution more modular, which naturally leads to the incorporation of more materials for more applications. Bu cautions, however, that intro- ducing new materials in semiconductor technology has never been easy. “It takes many years of R&D to reach this implementation point, if it ever happens. So, do we need new materials when the industry moves to 5nm and 3nm? Yes, though I expect new material implementation to be a lot faster in interconnect and packaging at these nodes rather than intrinsic to the transistor.”

Challenges in developing atomic-level processes

There will be challenges in developing atomic-level processes used in scaling, such as atomic layer depositions (ALD) and atomic layer etches, notes Verkest. “These classes of processes are both required to handle the scaled dimensions at the 5nm and 3nm nodes, and also the 3D nature of the scaled technologies – and here we are talking about logic and memories,” Verkest says. “With respect to depositions, we would need to develop thermal ALD processes (not plasma-based) that enable accurate and conformal depositions in non-line-of-sight structures.”

Adhesion and wetting, smoothness, and throughput would also need to be addressed. “Longer term, these processes need to facilitate selectivity and self-alignment to address gap-fill challenges in highly scaled structures,” he says. Other concerns he notes with respect to atomic layer etches are selectivity to various materials, and fidelity requirements that increase the requirements for metrology accuracy. “Throughput is also a concern.”

Bu believes that a new device architecture beyond FinFET is required to provide a full technology node scaling benefit (i.e., density, power and performance) at 5nm and 3nm.
“Beyond 3nm, we may need to continue the transistor scaling in the vertical direction and start to stack them together,” Bu says. He also cites the need for parasitic R/C reduction in the interconnect to take advantage of the intrinsic transistor benefit at the circuit and chip levels. “We see a lot of opportunity in atomic-level processes, especially in atomic layer etch and selective material deposition, to address these challenges in the transistor and the interconnect.”

Multi-Trigger chemistry, which is designed specifically for EUV, creates a high- chemical gradient at pattern boundaries, significantly reducing blurring and improving line-edge roughness to reduce the RLS trade off.

BY DAVID URE, ALEXANDRA MCCLELLAND and ALEX ROBINSON, Irresistible Materials, Wellesley, MA and Birmingham, U.K.

The semiconductor industry has invested billions of dollars to develop extreme ultraviolet (EUV) lithography and high-volume deployment of the technology is imminent. However, EUV lithography is not yet a complete solution. Most notably, new photoresist materials that enable the full benefits of EUV have yet to be developed.

While incremental modifications of incumbent ‘chemically amplified resists’ will be used for the planned initial EUV introduction in 2019, there are presently no clear solutions that address the industry feature size targets, defectivity requirements, and sensitivity needs for 2020 and onwards. This is a significant concern and continues to cast a shadow over the industry’s long anticipated switch to EUV lithography. Indeed, the lack of a suitable resist for EUV lithography is now one of the biggest problems faced by the semiconductor industry.

What makes a good resist?

The critical performance parameters for any successful resist are: 1) Resolution (R): How narrow the lines on a microchip are, 2) Line-edge roughness LER (L): How ‘wobbly’ the lines are; and 3) Sensitivity (S): How small a dose of radiation is required (how quickly the pattern can be formed). These performance metrics are known as the RLS targets, and they are set out in the ITRS. For a given material, these metrics have a conflicting relationship (one can only be improved at the cost of another): The ‘RLS tradeoff’. For a given material, improving one or two of the metrics leads to a loss in the third. To improve the RLS tradeoff, it is necessary to move to a new RLS graph. This can only be done by changing the resist material as illustrated in FIGURE 1.

In addition to the primary RLS targets, there are a series of critical secondary peformance metrics a commercially successful resist system needs to address, including the ability to pattern with extraordinarily low level of defects, high durability in the post processing steps, ultra-low contamination levels and wide process latitude.

The limitations with current state-of-art resist technology

Existing state-of-the-art photoresists are polymer- based platforms known as Chemically Amplified Resists (or CARs). The original CAR was based on a poly(hydroxystryene) chain with acid-labile tBOC protecting groups on the phenols, mixed with a photoacid generator. The photoacid released upon light exposure diffused through the polymer matrix catalytically removing the protecting groups, leading to a strong change in the solubility. While modern chemically amplified resists have increased in complexity, often using proprietary co-polymers with multiple functional units to address etch durability, adhesion and other properties, the core mechanisms of patterning have remained the same as the original CAR technology.

Such materials have demostrated significant design flexibility to address the evolving needs of the lithog- raphy industry. However, as feature sizes have continued to shrink, the diffuse nature of the acid – required for high senstitivity – has hampered resolution, and the acid quenchers, added to address this, have driven defects and roughness up. These limitations have risen to the fore as the industry prepares for the introduction of EUV lithography and the targeted feature sizes are increas- ingly incompatible with CAR technology.

Solving the EUV resist problem?

Given the limitations of polymer-platform photoresists originally developed for 193nm lithography, as the industry prepares for EUV introduction, the approach to photoresist development is being challenged. Indeed, device manufacturers and scanner suppliers have urged the photoresist suppliers to consider novel approaches to design photoresist systems specifically to meet the needs of EUV lithography.

One of the new photoresist platforms that has risen to prominence has been given the name ‘molecular resist’ because it represents a departure from polymer- based photoresists to formulations based around ‘small molecules.’ Originally developed to reduce the chemical ‘pixel’ size of the resist, this platform has demonstrated promise in reducing line-edge roughness, but until recently has not fulfilled its early promise in EUV.

Another novel approach has been the development of metal-oxide resist platforms. These have demonstrated a compelling combination of high resolution, and low-line edge roughness, and sensitivities have improved recently. However, like other contenders, these materials currently demonstrate high defects and face a hurdle due to concerns over the use of metals in a cleanroom environment.

Another leading new ‘EUV specific’ resist system is being developed by Irresistible Materials Ltd (IM), a company headquartered in Birmingham, England. IM has developed a new approach to achieve high-resolution, high sensitivity, and a low LER resist called the Multi-Trigger Resist platform(MTR). MTRs comprise a small proprietary resin molecule; an MTR process compatible cross-linker; and (like a chemically amplified resist) a photo-acid generator (PAG). However, the novel Multi-Trigger chemistry creates a high-chemical gradient at pattern boundaries, significantly reducing blurring and improving line-edge roughness to reduce the RLS trade off (FIGURE 2).

In a Multi-Trigger material, resist exposure proceeds via a catalytic process in a similar manner to a chemically amplified resist. However, instead of a single photoacid causing a single deprotection event and then being regen- erated, the Multi-Trigger resist uses multiple photoacids to activate multiple acid sensitive molecules, which then react with each other to cause a single resist event while also regenerating the photoacids. Importantly, it is only when two complimentary activated molecules react with each other that the resist is exposed – a single activated molecule, which is not near another will quench the acid, and remain unexposed.

In areas with a high number of activated photoacids (higher dose areas, for instance at the centre of a pattern feature), resist components are activated in close proximity and the multi-step resist exposure reaction proceeds, ending with photoacids regeneration and thus further reactions, ensuring high sensitivity. In areas with only a low number of activated photoacids (lower dose areas, for instance at the edge of a pattern feature), the activated resist components are too widely separated to react and the photoacids are thus removed, stopping the catalytic chain. The Multi- Trigger resist creates an increase in the chemical gradient at the edge of patterned features and reduces undesirable acid diffusion out of the patterned area. FIGURE 3 and 4 illustrate how the Multi-Trigger approach departs from the traditional approach used in existing state-of-the-art resist systems (CARs).

How good is the MTR system and where is it in its development cycle?

The MTR system is presently in an advanced development phase. Results have already shown this system can match and exceed the performance capabilities of state-of-the- art CARs. Furthermore, the specific formulation of the MTR system can be tailored by changing the ratio of the components within the resist. To date, IM has demonstrated that the sensitivity of the resist can be varied from 12 mJ/cm2 to over 50 mJ/cm2, with the patterned resolution ranging from 20nm half pitch to under 16nm half pitch respectively, to meet varying lithographic requirements.

Some example data from the ASML NXE 3300 scanner at IMEC in Belgium is included for reference below. ASML’s NXE platform is the industry’s first production platform for extreme ultraviolet lithography (EUVL), using 13.5 nm EUV light, generated by a tin-based plasma source.

FIGURE 5 shows results for 20nm half-pitch lines patterned on a pitch of 40nm. At a dose of 44.5 mJ/cm2, the LER is 2.6nm. FIGURE 6 shows 16nm half-pitch lines patterned on a pitch of 32nm. At a dose of 38.5 mJ/cm2, the LER is 3.7nm (unbiased values). These LER values compare very favorably with existing state-of-the-art CAR resists modified for EUV lithography. Importantly, the MTR technology is at the very beginning of its optimization cycle, with significant further performance enhancements expected as the technology matures. To this end, IM is in the process of scaling operations to accelerate the optimization of the MTR system in preparation for commercial launch.

The roadmap to commercial readiness

Prior to commercial integration into a Fab, it is also critical to address the ‘secondary’ performance metrics previously discussed. It is these tests that often prove a stumbling block to progressing from a promising new material. For an SME such as Irresistible Materials, passing this testing is a challenge as often new infrastructure and a specialist, custom tool set is required to pass stringent tests such as contamination. A resist that meets all lithography criteria could still fail to be adopted if, for example, the solubility of the components has not be synthesised with the required solubility in common fabrication solvents which will be present in the waste system.

For IM’s MTR, a precipitation test using waste drain solvents passed the precipitation test with no precipitate optically visible. These results indicate that the IM resist can be used within a fabrication facility with no precipitation issues. The resist also passes outgassing requirements so that it does not contaminate the lithog- raphy tool. Furthermore, because the resist is not metal based, there are no inherent track contamination issues. Metallic ion migration is a key concern for advanced device manufacturers and IM has implemented several protocols to address metal ion related concerns — the current contaminant metal levels are below 15ppb for each individual metal and will reduce further as production system are optimized.

Another major step in the commercialization roadmap is the ability to produce material in a quality controlled, high-volume manufacturing process at commercially competitive costs. To address this requirement, IM has established a partnership with Nano-C for the high- volume supply of IM’s proprietary resin molecule. Nano-C, Inc. is a leading supplier of specialist small molecules and has recently doubled the footprint at its Massachusetts site as preparations are made to scale production of the IM materials.

Looking towards the future

IM is targeting launch of its initial MTR products in 2020 (to address the industry N5 node),and is presently engaged in a variety of tests/trials with potential end-user and distribution partners as the resist system is optimized, scaled and readied for commercial release. However, IM also recognizes the potential of this resist system to go beyond N5 and has a clear pathway for addressing future industry nodes, to N3 and potentially beyond. Notable upgrade pathways from the gen 1 MTR include optimizing the metastable nature of the proton quenching, increasing opacity, reducing the number of components in the resist to reduce the impact of stochastics, and optimizing the ancillary process.

By Pete Singer

Increasingly complicated 3D structures such finFETs and 3D NAND require very high aspect ratio etches. This, in turn, calls for higher gas flow rates to improve selectivity and profile control. Higher gas flow rates also mean higher etch rates, which help throughput, and  higher rates of removal for etch byproducts.

“Gas flow rates are now approaching the limit of the turbopump,” said Dawn Stephenson, Business Development Manager – Chamber Solutions at Edwards Vacuum. “No longer is it only the process pressure that’s defining the size of the turbopump, it’s now also about how much gas you can put through the turbopump.”

Turbopumps operate by spinning rotors at very high rates of speed (Figure 1). These rotors propel gases and process byproducts down and out of the pump. The rotors are magnetically levitated (maglev) to reduce friction and increase rotor speed.

Figure 1. Spinning rotors propel gases and process byproducts out of the pump.

The challenge starts with processes that have high gas flow rates, over a thousand sccm, and lower chamber pressures, below 100 mTorr.  Such processes include chamber clean steps where high flows of oxygen-containing gases are used to remove and flush the process byproducts from inside the chamber, through Silicon via (TSV) in which SF6is widely used at high gas flowrates for deep silicon reactive ion etch (RIE) and more recently, gaseous chemical oxide removal (COR) which typically uses HF and NH3to remove oxide hard masks.

However, the challenge is intensified with the more general trend to higher aspect ratio etch across all technologies.

Stephenson said the maximum amount of gas you can put through a maglev turbo is determined by two things: the motor power and the rotor temperature. Both of these are affected adversely by the molecular weight of the gas. “The heavier the molecule, the lower the limit. For motor power, if the gas flow rate is increased, the load on the rotor is increased, and then you need more power. Eventually you reach a gas flow at which you exceed the amount of power you have to keep the rotor spinning and it will slow down,” she said.

The rotor temperature is an even bigger limiting factor. “As gas flow rates increase, the number of molecules hitting the rotor are increased. The amount of energy transferred into the rotors is also increased which elevates the temperature of the rotor. Because the rotor is suspended in a vacuum and because it’s levitated, it’s not very easy to remove that heat from the rotor because its primary thermal transfer is through radiation,” she explained.

Pumping heavier gases, particularly ones that have poor thermal conductivity, cause the rotor temperature to rise, leading to what is known as “rotor creep.”Rotor creep is material growth due to high temperature and centrifugal force (stress).  Rotor creep deformation over time narrows clearances between rotor and stator and can eventually lead to contact and catastrophic failure (Figure 2).

Figure 2. Edwards pumps have the highest benchmark for rotor creep life temperature in the industry, due to the use of a premium aluminum alloy as the base material for its mag-lev rotors, combined with a low stress design.

Where it gets even worse are in applications where the turbopump is externally heated to reduce byproduct deposition inside the pump. Such a heated pump will have a higher baseline rotor temperature and significantly lower allowable gas flowrates than an unheated one. This becomes a challenge particularly for the heated turbopumps on semiconductor etch and flat panel display processes using typical reactant gases such as HBr and SF6.  “Those are very heavy gases with low thermal conductivity and the maximum limit of the turbopump is actually quite low,” Stephenson said.

The good news is that Edwards has been diligently working to overcome these challenges. “What we have done to maximize the amount of gas you can put into our turbopumps is to  ensure our rotors can withstand the highest possible temperature design limit for a 10 year creep lifetime.   We use a premium alloy for the base rotor material and then beyond that we have done a lot of work with our proprietary modeling techniques to design a very low stress rotor because the creep is due to two factors: the temperature and the centrifugal stress. Because of those two things combined, we’re able to achieve the highest benchmark for rotor creep life temperature in the industry,” she said.

Furthermore, the company has worked on thermal optimization of the turbopump platform. “That means putting in thermal isolation where needed to try to help keep the rotor and motor cool. At the same time, we also need to keep the gas path hot to stop byproducts from depositing. We have also released a high emissivity rotor coating that helps keep the rotor cool,” Stephenson said. A corrosion resistant, black ceramic rotor coating is used to maximize heat radiation, which helps keep the rotor cool and gives more headroom on gas flowrate before the creep life temperature is reached.

Edwards has also developed a unique real-time rotor temperature sensor: Direct, dynamic rotor temperature reporting eliminates over-conservative estimated max gas flow limits and allows pump operation at real maximum gas flow in real duty cycle while maintaining safety and lifetime reliability.

In summary, enabling higher flows at lower process pressures is becoming a critical capability for advanced Etch applications, and Edwards have addressed this need with several innovations, including optimized rotor design to minimize creep, high emissivity coating, and real time temperature monitoring.