Category Archives: Device Architecture

Cadence Design Systems, Inc. (NASDAQ: CDNS) today launched the Cadence Cloud portfolio, the first broad cloud portfolio for the development of electronic systems and semiconductors. The Cadence Cloud portfolio consists of Cadence-managed and customer-managed environments that enable electronic product developers to use the scalability of the cloud to securely manage the exponential increase in design complexity. With the new portfolio offerings, customers gain access to improved productivity, scalability, security and flexibility, through scalable compute resources available in minutes or hours instead of months or weeks, achieving better overall throughput in the development process.

The announcement was made at the 55th annual Design Automation Conference (DAC) being held in San Francisco at Moscone Center West, June 25-28, 2018. Cadence is located in booth 1308 in the main exhibit hall and booth 1245 in the Design Infrastructure Alley. For more information on the new Cadence Cloud portfolio, please visit www.cadence.com/go/cadencecloud.

Cadence gained extensive cloud experience by hosting design environments for more than 100 customers of varying sizes and architecting many of its products to be massively parallel for improved scalability in the cloud.

“The cloud will fundamentally influence silicon design by giving semiconductor companies the ability to optimize their capital versus operational expenses for computing infrastructure,” said Suk Lee, senior director Design Infrastructure Marketing Division at TSMC. “Cadence has passed our rigorous cloud security audits and is authorized to engage with mutual customers on the Cadence Cloud using TSMC process models and rule decks.”

“While many industries have previously adopted the cloud to address compute-intensive workloads, systems and semiconductor companies have faced unprecedented challenges that have made cloud adoption difficult until now,” said Richard Wawrzyniak, principal analyst for ASIC & SoC at Semico Research Corp. “Some of the challenges included security concerns and the sheer amount of design data and the inherent scalability limitations with electronic design automation tools. The Cadence approach to the cloud addresses historical industry issues, opening the door for customers to adopt the cloud and enter the next generation of chip design development.”

According to a recent report published by Allied Market Research, titled, Global Organic CMOS Image Sensor Market by Image Processing, Array Type, Industry Vertical and Application: Global Opportunity Analysis and Industry Forecast, 2020-2025, the global organic CMOS image sensor market is expected to value at $696.0 million in 2020, and is projected to reach $1,750.0 million by 2025, registering a CAGR of 20.9% from 2021 to 2025.

At present, North America dominates the market, followed by Europe. In 2020, U.S dominated the North America market and rest of Europe led the overall market in Europe. However, in North America, the U.S. currently dominates the market.

The high photoelectric conversion property, better low-light performance and richer colors & textures drive of the organic CMOS image sensor make way for the growth of the market. In addition, introduction of technologies such as 8K resolution and global shutter technology also contribute to the market growth. However, excessive generation of heat in the organic sensor technology hampers this stated growth.

Key Findings of the Organic CMOS Image Sensor Market:

  • The linear image sensors segment generated the highest revenue in the global organic CMOS image sensor market in 2020.
  • In 2020, the 2D Sensors segment was the highest revenue contributor in the image processing segment.
  • Asia Pacific is anticipated to exhibit the highest CAGR during the forecast period.
  • In 2020, North America contributed the highest market share, followed by Europe, Asia Pacific and LAMEA.

The key players profiled in the report include are Fujifilm Corporation, Panasonic Corporation, Sony Corporation, Samsung Electronics, Siemens AG, NikkoIA SAS, Xenics NV, AMS AG, Canon, and OmniVision Technologies, Inc.

The semiconductor industry posted record results in 2017, with revenue exceeding US$400 billion. Overall demand for semiconductor devices was robust throughout the year, driven by the growing adoption of electronics components across all applications, with particular strength in the mobile and data center markets. Semiconductor growth in 2017 was led by the memory segment, with impressive revenue reaching US$126 billion. It represents an increase of over 60% year-over-year. Yole Développement (Yole) Memory Team forecasts the memory market to reach US$177 billion in 2018, with 40% growth.

Under this dynamic ecosystem, Yole and its partners System Plus Consulting and Knowmade, all parts of Yole Group of Companies, deeply scan the memory area. They propose today valuable memory services to deliver world class research, data and insight. Their aim is to ensure its clients are well-versed in all aspects of this competitive industry. Yole Group of Companies leverage decades of industry experience and expertise while partnering with its clients to make sure they are consistently well-informed on this pushy market.

Today two memory research services, DRAM Service and NAND Service have been developed by Yole Group of Companies. Full description of both services are available in a new dedicated Memory section on i-micronews.com. In addition, a selection of technology & market news are daily selected by Yole’s memory team and posted in this section.

Make sure to collect deep insights and significant analyses from leading industry experts, combining over 50-year experience in memory and semiconductor-related fields.

Both DRAM and NAND markets were in a state of undersupply throughout the year, leading to rising prices and record revenue and profitability for the memory suppliers. Demand was very strong, led by mobile and data center / SSD and augmented by emerging growth drivers including AI , IoT and automotive. Supply growth across both DRAM and NAND was constrained, due to a combination of limited wafer growth and technological challenges.

The current macro trends of AI and machine learning, mobility, and connectivity, are favorable to both the DRAM and NAND markets, and will likely result in Memory continuing to increase its share of the overall the semiconductor market.

“Understanding memory supply/demand dynamics and its relationship with pricing is vital to understanding the broader semiconductor market and all associated supply chains”, asserts Emilie Jolivet, Division Director, Semiconductor & Software at Yole.

The DRAM market is constantly evolving and changing. Yole Group is announcing a 22% CAGR for bit demand over the next five years.

“New Chinese suppliers threaten the current market balance, and emerging memory technologies are poised to cannibalize huge chunks of DRAM demand while the demand drivers of the past, including PCs and smartphones lose steam and no longer push industry demand,” comments .Mike Howards, VP of DRAM & Memory research within the Semiconductor & Software division at Yole.
In parallel, NAND market is expected to set another revenue record in 2018, before a flattish 2019. Therefore it continues to expand, with several consecutive quarters of record revenue and profitability for suppliers.

NAND’s competitive landscape remains incredibly dynamic. Samsung is prepping its first fab at its massive Pyeongtaek site; Intel is emerging as a stand-alone supplier with capacity in China; and the sale of Toshiba’s memory business to a consortium led by Bain Capital is finally happening. Meanwhile, a new entrant looms on the horizon: China’s Yangtze Memory Technologies Co. (YMTC), which threatens to disrupt the status-quo as well as multiple other Chinese projects.

“NAND demand remains robust, with strong growth for enterprise SSDs in data centers, increasing adoption of SSDs in laptop PCs, and continued content growth in smartphones and other mobile devices,” asserts Walt Coon, VP of NAND and Memory Research at Yole.“These segments will continue driving the bulk of NAND bit consumption, though several emerging trends are poised to augment future growth, including AI and VR adoption, automotive, and IoT,” he adds.

Memory Research Service from Yole, provides all data related to NAND/DRAM revenue per quarter, NAND/DRAM shipments, pricing per NAND/DRAM type, near and long-term revenue, market share per quarter, CAPEX per company, and a market demand/supply forecast. It also includes a complete analysis and details on the demand side, with a deep dive into client and enterprise SSD, data centers, mobile, automotive, graphics, PC, and more. Each Memory Research Service is composed of both products, the Quarterly Market Monitor and the Monthly Pricing Monitor.

During the next few weeks, Yole’s Memory Team will attend a selection of key trade shows and conferences to present the Memory Research Services. Make sure you will be there and ask for a meeting right now. Mike Howard and Walt Coon will for example be at SEMICON West mid-July and the Flash Memory Summit (Santa Clara, CA, North America – From August 6 to 9) in August. More information: Yole’s Agenda

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, this week released the following statement regarding the Trump Administration’s announcement on tariffs on products imported from China.

“While the U.S. semiconductor industry shares the Trump Administration’s concerns about China’s forced technology transfer and intellectual property (IP) practices, the proposed imposition of tariffs on semiconductors from China, most of which are actually researched, designed, and manufactured in the U.S., is counterproductive and fails to address the serious IP and industrial policy issues in China. We look forward to working with the Administration to explain why imposing tariffs on our products would be harmful to our competitiveness and does not address our challenges with China.”

SIA seeks to strengthen U.S. leadership of semiconductor manufacturing, design, and research by working with Congress, the Administration and other key industry stakeholders to encourage policies and regulations that fuel innovation, propel business and drive international competition. Learn more at www.semiconductors.org.

North America-based manufacturers of semiconductor equipment posted $2.70 billion in billings worldwide in May 2018 (three-month average basis), according to the May Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 0.6 percent higher than the final April 2018 level of $2.69 billion, and is 19.2 percent higher than the May 2017 billings level of $2.27 billion.

“May 2018 monthly global billings of North American equipment manufacturers exceeded last month’s level to set yet another record,” said Ajit Manocha, president and CEO of SEMI. “Demand for semiconductor equipment remains strong on the back of smart, data-centric applications such as artificial intelligence (AI), Internet of Things (IoT), big data, and edge computing.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
December 2017
$2,398.4
28.3%
January 2018
$2,370.1
27.5%
February 2018
$2,417.8
22.5%
March 2018
$2,431.8
16.9%
April 2018 (final)
$2,689.9
25.9%
May 2018 (prelim)
$2,705.8
19.2%

Source: SEMI (www.semi.org), June 2018

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology, will present a process flow for a complementary FET (CFET) device for nodes beyond N3. The proposed CFET can eventually outperform FinFETs and meet the N3 requirements for power and performance. It offers a potential area scaling of both standard cells (SDC) and memory SRAM cells by 50%.

The CFET is a further evolution of the vertically stacked gate all around nanowire transistor. Instead of stacking either n-type or p-type devices, it stacks both on top of each other. Imec’s proposed flow consists of stacking an n-type vertical sheet on a p-type fin. This choice exploits the FinFET process flow and benefits from the potential for strain engineering in the bottom pFET. Based on TCAD analysis, the proposed CFET can meet the N3 targets for power and performance, where it will outperform FinFETs. However, the dominant parasitic resistance of the deep vias needs to be reduced. This can be achieved by introducing advanced Middle of Line (MOL) contacts using e.g. ruthenium.

A design-technology co-optimization (DTCO) analysis reveals that the CFET device used in either an SDC or SRAM cell has the potential of 50% area reduction. The SDC area is mostly driven by accessing the transistor terminals. Consequently, the area gain using CFETs will not lie in the reduction of the active footprint, but rather in the considerable simplification of the transistor terminal access. By fully benefiting from the CFET architecture, it is possible to reduce the SDC to three routing tracks whereas the most advanced FinFET libraries today need six. For SRAM cells, the same area reduction is possible thanks to a new cross-coupling scheme that allows us to scale the cell height from T6 to T4.

“Given its excellent characteristics and scaling potential, the CFET device is an excellent contender for the new device architecture we need for nodes beyond N3, pushing the horizon for Moore’s Law farther out,” stated Julien Ryckaert, distinguished member of the technical staff at imec.”

These results will be presented on June 21 at the VLSI Technology Symposium, in session T13: FET performance and scaling. This research is performed in cooperation with equipment companies TEL Coventor and Lam Research and with imec’s key program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, TOSHIBA Memory, TSMC and Western Digital.

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the research and innovation hub in nanoelectronics and digital technology presented considerable progress in enabling germanium nanowire pFET devices as a practical solution to extend scaling beyond the 5nm node. In a first paper, the research center unveiled an in-depth study of the electrical properties of strained germanium nanowire pFETs. A second paper presents the first demonstration of vertically-stacked gate-all-around highly-strained germanium nanowire pFETs.

“With a number of scaling boosters, the industry will be able to extend FinFET technology to the 7- or even 5nm node,” says An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the FinFET process steps. But one important challenge of using lateral nanowires is the significant decrease of the channel cross-section compared to conventional FinFETs. To improve the drive per footprint, several nanowires have to be stacked, but this comes with a serious penalty of increased parasitic capacitance and resistance. A solution is to replace the silicon nanowires by a high-mobility channel material such as germanium (Ge), providing the necessary current boost per footprint”, adds Steegen, “These new studies show that solution is indeed feasible, reaching the cost, area and performance requirements for nodes beyond 5nm.”

The first study of high-performing strained Ge nanowire pFETs gives insight in the device performance these new devices may offer for high-end analog and high-performance digital solutions. One conclusion is that dedicated optimizations of key process steps make these devices a serious contender for the GAA technology. The second paper reports on Ge GAA FETs with single nanowires, achieving a performance that matches state-of-the-art SiGe and Ge FinFETs. Moreover, for the first time, strained p-type Ge GAA FETs with stacked nanowires were demonstrated on a 14/16nm platform. The GAA nanowire technology appears as a promising high-performance solution for future nodes, provided that the junctions are further optimized.

“These complimentary studies establish germanium GAA nanowire technology as a valid contender for the sustained scaling that will be required to fulfill the requirements for the data-driven IoT-era requiring huge computational power,” concludes Steegen.

These results will be presented on June 20 at the VLSI Technology Symposium, in session T8: Advanced FinFET and GAA. This research is performed in cooperation with imec’s key program partners including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions, TOSHIBA Memory, TSMC and Western Digital.

At this week’s 2018 Symposia on VLSI Technology and Circuits, imec, the world-leading research and innovation hub in nanoelectronics and digital technology, demonstrates for the first time the possibility to fabricate spin-orbit torque MRAM (SOT-MRAM) devices on 300mm wafers using CMOS compatible processes. With an unlimited endurance (>5×1010), fast switching speed (210ps), and power consumption as low as 300pJ, the SOT-MRAM devices manufactured in a 300mm line achieve the same or better performance as lab devices. This next-generation MRAM technology targets replacement of L1/L2 SRAM cache memories in high-performance computing applications.

SOT-MRAM has recently emerged as a non-volatile memory technology that promises a high endurance and low-power, sub-ns switching speed. With these properties, it can potentially overcome the limitations of spin-transfer torque MRAM (STT-MRAM) for L1/L2 SRAM cache memory replacement. But so far, SOT-MRAM devices have only been demonstrated in the lab. Imec has now for the first time proven full-scale integration of SOT-MRAM device modules on 300mm wafers using CMOS-compatible processes.

At the core of the SOT-MRAM device is a magnetic tunnel junction in which a thin dielectric layer is sandwiched between a magnetic fixed layer and a magnetic free layer. Similar as for STT-MRAM operation, writing of the memory is performed by switching the magnetization of this free magnetic layer, by means of a current. In STT-MRAM, this current is injected perpendicularly into the magnetic tunnel junction, and the read and write operation is performed through the same path – challenging the reliability of the device. In an SOT-MRAM device, on the contrary, switching of the free magnetic layer is done by injecting an in-plane current in an adjacent SOT layer – typically made of a heavy metal. Because of the current injection geometry, the read and write path are de-coupled, significantly improving the device endurance and read stability.

Imec has compared SOT and STT switching behavior on one and the same device, fabricated on 300mm wafers. While switching speed during STT-MRAM operation was limited to 5ns, reliable switching down to 210ps was demonstrated during SOT-MRAM operation. The SOT-MRAM devices show unlimited endurance (>5×1010) and operation power as low as 300pJ. In these devices, the magnetic tunnel junction consists of a SOT/CoFeB/MgO/CoFeB/SAF perpendicularly magnetized stack, using beta-phase tungsten (W) for the SOT layer.

“STT-MRAM technology has a high potential to replace L3 cache memory in high-performance computing applications”, says Gouri Sankar Kar, Distinguished Member of Technical Staff at imec. “However, due to the challenging reliability and increased nergy at sub-ns switching speeds, they are unsuitable to replace the faster L1/L2 SRAM cache memories. SOT-MRAM technology will help us to expand MRAM operation into the SRAM application domain. By moving this next-generation MRAM technology out of the lab, we have now demonstrated the maturity of the technology.” Future work will focus on further reducing the energy  consumption, by bringing down current density and by demonstrating field-free switching operation.

These results will be presented at the VLSI Circuits Symposium on June 20 in the session C8 Emerging Memory. Imec’s research into advanced memory is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Micron, Qualcomm, Sony Semiconductor Solutions, TSMC and Western Digital.

Qualcomm Incorporated (NASDAQ: QCOM) today announced that Qualcomm River Holdings B.V., an indirect wholly owned subsidiary of Qualcomm, has extended the offering period of its previously announced cash tender offer to purchase all of the outstanding common shares of NXP Semiconductors N.V. (NASDAQ: NXPI). The tender offer is being made pursuant to the Purchase Agreement, dated as of October 27, 2016, by and between Qualcomm River Holdings B.V. and NXP, as amended (the “Purchase Agreement”). The tender offer is now scheduled to expire at 5:00 p.m., New York City time, on June 22, 2018, unless extended or earlier terminated, in either case pursuant to the terms of the Purchase Agreement.

American Stock Transfer & Trust Company, LLC, the depositary for the tender offer, has advised Qualcomm River Holdings B.V. that as of 5:00 p.m., New York City time, on June 14, 2018, the last business day prior to the announcement of the extension of the offer, 16,319,317 NXP common shares (excluding 21,739 shares tendered pursuant to guaranteed delivery procedures that have not yet been delivered in settlement or satisfaction of such guarantee), representing approximately 4.7% of the outstanding NXP common shares, have been validly tendered pursuant to the tender offer and not properly withdrawn. Shareholders who have already tendered their common shares of NXP do not have to re-tender their shares or take any other action as a result of the extension of the expiration date of the tender offer.

Completion of the tender offer remains subject to additional conditions described in the tender offer statement on Schedule TO filed by Qualcomm River Holdings B.V. with the U.S. Securities and Exchange Commission on November 18, 2016, as amended (the “Schedule TO”). The tender offer will continue to be extended until all conditions are satisfied or waived, or until the tender offer is terminated, in either case pursuant to the terms of the Purchase Agreement by and between Qualcomm River Holdings B.V. and NXP and as described in the Schedule TO.

Micross, headquartered in Orlando, FL announced a new appointment within the company’s senior management team. Marshall (Mac) Blythe has joined Micross in the role of General Manager of Component Modification Services (CMS) located in Hatfield, PA.

Mac brings more than twenty-five years leadership experience in a variety of business development, operations & executive management roles to Micross. His career has been primarily focused in the Electronic Manufacturing Services industry, supporting customers across the Aerospace & Defense, Industrial, Healthcare and Communication sectors.

Mac comes to Micross from Creation Technologies where he served as Vice President, Business Development for Eastern North America. Previously, Mac was President of Accuspec Electronics (now 4Front Solutions) where he successfully led the team to accelerate revenue growth through improving the company’s operational effectiveness, manufacturing productivity and quality. Mac also spent over 12 years at Celestica, where he held key general management and senior sales leadership roles.

Mac earned his M.B.A. from the University of Chicago and holds a BA from UNC, Chapel Hill, NC.

“We are delighted to welcome Mac to the Micross team,” stated Richard Kingdon, CEO of Micross. “We are confident that Mac’s combination of leadership skills and industry experience will both drive Micross’ Component Modification business forward and enhance the effectiveness of our broader organization.”

Micross is the one-source, one-solution provider of Bare Die & Wafers, Advanced Interconnect Technology, Custom Packaging & Assembly, Component Modification Services, Electrical & Environmental Testing and Hi-Rel Products to manufacturers and users of semiconductor devices.