Category Archives: Device Architecture

North America-based manufacturers of semiconductor equipment posted $2.69 billion in billings worldwide in April 2018 (three-month average basis), according to the April Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 10.7 percent higher than the final March 2018 level of $2.43 billion, and is 26.0 percent higher than the April 2017 billings level of $2.13 billion.

“April 2018 monthly billings for North American equipment manufacturers surpassed the October 2000 record high of $2.6 billion,” said Ajit Manocha, president and CEO of SEMI. “Storage, artificial intelligence and big data are driving strong demand for semiconductors, offsetting smartphone sales that have lagged expectations this year.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
November 2017
$2,052.3
27.2%
December 2017
$2,398.4
28.3%
January 2018
$2,370.1
27.5%
February 2018
$2,417.8
22.5%
March 2018 (final)
$2,431.8
16.9%
April 2018 (prelim)
$2,691.4
26.0%

Source: SEMI (www.semi.org), May 2018

GLOBALFOUNDRIES today announced that its 22nm FD-SOI (22FDX®) technology platform has been certified to AEC-Q100 Grade 2 for production. As the industry’s most advanced automotive-qualified FD-SOI process technology, GF’s 22FDX platform includes a comprehensive set of technology and design enablement capabilities tailored to improve the performance and power efficiency of automotive integrated circuits (ICs) while maintaining adherence to strict automotive safety and quality standards.

With the rapid proliferation of automotive electronics content and regulations on energy efficiency and safety, semiconductor device component quality and reliability are more critical than ever. As a part of the AEC-Q100 certification, devices must successfully withstand reliability stress tests for an extended period of time, over a wide temperature range in order to achieve Grade 2 certification. The qualification of GF’s 22FDX process exemplifies the company’s commitment to providing high-performance, high-quality technology solutions for the automotive industry.

“FD-SOI has advantages for companies who are looking for real-time trade-offs in power, performance and cost,” said Dan Hutcheson, CEO and Chairman of VLSI Research. “GF’s automotive-qualified 22FDX technology is exactly what automakers and suppliers need to enable the rapid integration of highly integrated automotive-grade ICs.”

“GLOBALFOUNDRIES has more than 10 years of providing automotive solutions to the industry. We have proven our commitment to semiconductor quality and reliability through a range of certifications and audits every year,” said Dr. Bami Bastani, senior vice president of business units at GF. “The automotive qualification of our 22FDX technology reaffirms our commitment to expanding our FD-SOI capabilities and portfolio to reach new markets and customers. We now have a proven ability to manufacture our 22FDX technology to meet the rigorous quality and performance requirements of the automotive market.”

As a part of the company’s AutoPro™ platform, 22FDX allows customers to easily migrate their automotive microcontrollers and ASSPs to a more advanced technology, while leveraging the significant area, performance and energy efficiency benefits over competing technologies. Moreover, the optimized platform offers high performance RF and mmWave capabilities for automotive radar applications and supports implementation of logic, Flash, non-volatile memory (NVM) in MCUs and high voltage devices to meet the unique requirements of in-vehicle ICs.

GF’s AutoPro platform consists of a broad portfolio of automotive AEC-Q100 qualified technology solutions, backed by robust services package that comply with rigorous ISO automotive quality standards across GF’s fabs in Singapore and, most recently, Fab 1 in Dresden, Germany that achieved ISO-9001/IATF-16949 certification and is now capable of meeting the stringent and evolving needs of the automotive industry.

The 22FDX PDK is available now along with a wide-range of silicon-proven IP. Customers can now start optimizing their chip designs to develop differentiated low power and high performance automotive solutions.

Cadence Design Systems, Inc. (NASDAQ: CDNS) and NI (NASDAQ: NATI) today announced a broad-ranging collaboration to improve the overall semiconductor development and test process of next-generation wireless, automotive and mobile integrated circuits (ICs) and modules. To meet customers’ needs for a streamlined and comprehensive solution, Cadence and NI have pursued projects that integrate key design tool technologies into a common user environment to improve the design, analysis and testing of analog, RF and digital ICs and system-in-package (SiP) modules spanning from pre-silicon design to volume production test. To further enhance RF development, Cadence has also launched the new Virtuoso® RF Solution, which enables RF engineers to design, implement and analyze entire RF modules and RFICs from within the Virtuoso custom IC design platform.

The New Cadence Virtuoso RF Solution and AXIEM 3D Planar EM Software Integration

Traditionally, each major stage in the IC development process has operated in isolation supported by a unique and dedicated set of design tools, models, languages and data formats, which can cause design failures due to the manual translation of data between numerous disjointed tools. To address this issue and streamline the RFIC and RF module design flow, Cadence delivered the following capabilities within the new Virtuoso RF solution:

  • RFIC and RF Module co-design: Provides a robust design environment enabling simultaneous editing of multiple ICs on a complex RF module while streamlining design to manufacturing tasks
  • Single “golden” schematic: Offers schematic-driven layout implementation, EM analysis and simulation and physical verification checks of RFIC and RF module design through a single schematic source, reducing design failures
  • Smart electromagnetic (EM) simulation interface: Includes an integration between the Cadence® Sigrity™ PowerSI® 3D EM Extraction Option and the Virtuoso RF Solution, which automates hours of manual work required to run critical passive component and interconnect EM simulations so users can run multiple in-design experiments

As part of the collaboration between the two companies, the Cadence interface has been extended to include an integration with the AXIEM 3D planar EM simulator, within the Cadence Virtuoso RF Solution design environment. The AXIEM software’s fast solver technology readily addresses passive structures, transmission lines, large planar antenna and patch array problems with more than 100,000 unknowns, providing the accuracy, capacity and speed engineers need to help them ensure design integrity upon the first attempt. It also incorporates NI’s proprietary full-wave planar Method of Moments (MoM) technology that enables discrete- and fast-frequency sweeps.

The integrated Cadence and NI EM solutions equip engineers with a variety of EM analysis methods for designing RFICs and RF modules.

Common Semiconductor Models

Compatible models are critical to ensuring correlated results across different simulation tools. Cadence and NI are jointly working to deliver common transistor models, ensuring consistent simulation behavior of gallium arsenide (GaAs), gallium nitride (GaN) and silicon transistor models between Microwave Office circuit design software and the Cadence Spectre® simulation platform.

“With customers beginning to design the next generation of RF products for 5G, autonomous vehicles and other vertical markets, we saw a need to deliver a comprehensive RF solution that creates more efficiencies and drives innovation,” said Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence. “Based on the trusted Virtuoso custom IC design platform, the new Cadence Virtuoso RF Solution streamlines design and analysis for RFIC and RF modules. The collaboration between Cadence and NI and the integration of our tools can enable customers to seamlessly analyze and simulate their chip and package, reducing design cycle time and improving quality of results.”

“Our customers are continuously seeking new approaches to accelerate their product development cycles,” said Kevin Ilcisin, vice president of strategy and corporate development at NI. “The collaboration with Cadence allows us to embed our AXIEM 3D Planar EM software directly into the Virtuoso RF Solution, enabling customers to easily design analog, mixed-signal, RFIC and RF modules.”

The new Virtuoso RF Solution with the integrated AXIEM 3D planar EM solver technology will be sold and supported exclusively by Cadence to leverage years of development and customer deployment expertise. For more information, please visit www.cadence.com/go/virtuosorfni.

Memory devices employ a wide range of packaging technology from wire-bond leadframe and BGA to TSV.

BY SANTOSH KUMAR, Yole Développement, Lyon-Villeurbanne, France

The memory market is going through a strong growth phase. The total memory market grew by >50% YoY to more than US$125 billion in 2017 from US$79.4 billion in 2016. [1] RAM and NAND dominate the market, representing almost 95 % of standalone memory sales. There is a supply/demand mismatch in the market which is impacting on the ASP of memory devices, and as a result the large memory IDMs are reaping record profits. The memory industry has consolidated with the top five players – Samsung, SKHynix, Micron, Toshiba and Western Digital – accounting for 90% of the market.

The demand for memory is coming from all sectors but the mobile and computing (mainly servers) market is showing particularly strong growth. On average, the DRAM memory capacity per smartphone will rise more than threefold to reach around 6GB by 2022. DRAM cost per smartphone represents >10% of the bill of materials of the phone and is expected to increase further. The NAND capacity per smartphone will increase more than fivefold to reach >150GB by 2022. For servers, the DRAM capacity per unit will increase to a whopping 0.5TB by 2022, and the NAND capacity per SSD for the enterprise market will be in excess of 5TB by 2022. The growth in these markets is led by applications like deep learning, big-data, networking, AR/ VR, and autonomous driving. The automotive market, which traditionally used low density (low-MB) memory, will see the adoption of DRAM memory led by the emerging trend of autonomous driving and in-vehicle infotainment. The NOR flash memory market also saw a resurgence and is expected to grow at an impressive 16% CAGR to reach ~US$4.4 billion by 2022, due to its application in new areas such as AMOLED displays, touch display driver ICs and industrial IoTs.

On the supply side, the consolidation of players, the difficulty in migrating to advanced nodes due to technical challenges, and the need for higher investment to migrate from 2D to 3D NAND, has led to shortfall in both DRAM & NAND flash supply. DRAM players want to retain high ASPs (& high profitability) to justify the huge capex investment for advanced node migration and as such are not inclined to increase capacity. Entry of Chinese memory players will ease the supply side constraint, but it’ll not happen before 2020.

Memory device packaging

There are many variations of memory device packaging. This implies a wide range of packaging technology from the low pin count SOP package to the high pin-count TSV, all depending upon the specific product requirements such as density, performance, cost, etc. We have broadly identified five packaging platforms for memory devices: viz lead frame, wire-bond BGA, flip-chip BGA, WLCSP and TSV, even though in each platform there are many varia- tions and different nomenclature in industry.

The total memory package market is expected to grow at 4.6% CAGR2016-2022 to reach ~US$26 billion by 2022. [1] Wire-bond BGA accounted for more than 80% of the packaging market in dollar terms in 2016. Flip-chips, however, started making inroads in the DRAM memory packaging market and is expected to grow at ~20% CAGR in the next five years to account for more than 10% of the memorypackagingmarket.Currentlytheflip-chipmarket is only around 6% of the total memory packaging market. Flip-chip growth is led by its increased adoption in the DRAM PC/server segment fueled by a high bandwidth requirement.

Currently Samsung has already converted >90% of its DRAM packaging line. SK Hynix have started the conversion and other players will also adopt it in future. At Yole Développement (Yole), we believe that all DDR5 memory for PC/servers will move to flip-chip.

TSV is employed in high bandwidth memory devices requiring high bandwidth with low latency memory chips for high performance computing in various applications. In 2016 the TSV market was <1% of the total memory market. However, it is expected to grow by >30% CAGR to reach ~8% of memory packaging in dollar terms. WLSCP packaging is used in NOR flash and niche memory devices (EEPROMs/EPROM/ROM). It is expected to grow at >10% CAGR, but in terms of value will remain <1% of the market by 2022.

In mobile applications, memory packaging will mainly remain on the wire-bond BGA platform but will start to move into the multi-chip package (ePoP) for high end smartphones.

The main requirement of NAND flash devices is high storage density at low cost. NANDs are stacked using wire bonding to provide high density in a single package. The NAND packaging market is expected to reach ~ US$ 10 billion by 2022. NAND flash packaging will remain on the wire bond BGA platform and will not migrate to flip-chip. Toshiba, however, will start using TSV packaging in NAND devices to increase the data transfer rate for high end applications. Following Toshiba, we believe Samsung and SKHynix will also bring TSV packaged NAND devices into the market.

OSATs account for <20% of the memory packaging business

The total memory packaging market is estimated to have been ~US$20 billion in 2016. There are many OSATs involved in the memory packaging business, and >80% of the packaging (by value) is still done internally by OSATs. The majority of these are small OSATs and have only low-end packaging capability. Global memory IDMs have much experience in packaging, accumulated over years, and have their own internal large capacity. Therefore, there is limited opportunity for OSATs to make inroads into the packaging activity of IDMs. Many Chinese players, however, are entering the memory market with more than US$50 billion investment committed. [1] These new entrants do not have experience in memory assembly / packaging, unlike global IDMs, and they will outsource major packaging activities to OSATs. The flip-chip business for memory packaging will increase to 13% of the total market to reach US$3.5 billion in 2022. This is an opportunity for low-end memory OSATs to invest in flip-chip bumping and assembly capacity. Otherwise they will lose business to the big OSATs with advanced packaging capability.

Conclusion

The memory industry is going through a golden phase with strong demand coming from all sectors, particularly from the mobile and computing (mainly servers) markets.

Memory devices employ a wide range of packaging technology from wire-bond leadframe and BGA to TSV. Wire-bond BGA still accounts for the bulk of the memory packaging market. However, flip-chip technology will start making inroads in DRAM memory packaging and will grow at 20% CAGR (by revenue) over the next five years, accounting for ~13% of the total memory packaging market by 2022. The memory packaging market is mainly controlled by IDMs. OSATs have limited opportunity to impact IDM packaging activity. Many Chinese players, however, are entering the memory business and, unlike global IDMs, these new players lack experience in memory assembly/packaging and they outsource most of their packaging activity to OSATs.

SANTOSH KUMAR is a Senior Technology and Market Research Analyst at Yole Développement in France.

References

1. Memory Packaging Market and Technology Report 2017, Yole Développement

IC Insights recently released its May Update to the 2018 McClean Report.  This Update included a look at the top-25 1Q18 semiconductor suppliers, a discussion of the 1Q18 IC industry market results, and an update of the 2018 capital spending forecast by company.

Overall, the capital spending story for 2018 is becoming much more positive as compared with the forecast presented in IC Insights’ March Update to The McClean Report 2018 (MR18).  In the March Update, IC Insights forecast an 8% increase in semiconductor industry capital spending for this year. However, as shown in Figure 1, IC Insights has raised its expectations for 2018 capital spending by six percentage points to a 14% increase.  If this increase occurs, it would be the first time that semiconductor industry capital outlays exceeded $100 billion.  The worldwide 2018 capital spending forecast figure is 53% higher than the spending just two years earlier in 2016.

Although Samsung says it still does not have a full-year capital spending forecast for this year it did say it will spend “less” in semiconductor capital outlays in 2018 as compared to 2017, when it spent $24.2 billion.  However, as of 1Q18, with regard to its capex, its “foot is still on the gas!”  Samsung spent $6.72 billion in capex for its semiconductor division in 1Q18, slightly higher than the average of the previous three quarters.  This figure is almost 4x the amount the company spent just two years earlier in 1Q16!  Over the past four quarters, Samsung has spent an incredible $26.6 billion in capital outlays for its semiconductor group. Wow!

IC Insights has estimated Samsung’s semiconductor group capital spending will be $20.0 billion this year, $4.2 billion less than it spent in 2017.  However, given the strong start to its spending this year, it appears there is currently more upside than downside potential to this forecast.

With the DRAM and NAND flash memory markets still very strong, SK Hynix is expected to ramp up its capital spending this year to $11.5 billion, 42% greater than the $8.1 billion it spent in 2017. The increased spending by SK Hynix this year will primarily focus on bringing on-line two large memory fabs—M15, a 3D NAND flash fab in Cheongju, South Korea and its expansion of its huge DRAM fab in Wuxi, China.  The Cheongju fab is being pushed to open before the end of this year.  The Wuxi fab is also targeted to open by the end of this year, a few months earlier than its original planned start date of early 2019.

Figure 1

After strong year-over-year growth of 24% in 2017, worldwide semiconductor revenue is forecast to grow for the third consecutive year in 2018 to $450 billion, up 7.7% over 2017, according to a new Semiconductor Applications Forecaster (SAF) from International Data Corporation (IDC). The SAF also forecasts that semiconductor revenues will log a compound annual growth rate (CAGR) of 2.9% from 2017-2022, reaching $482 billion in 2022.

The overall memory market was the key story of last year, due to strong demand, limited supply, and product mix constraints. The DRAM and NAND memory markets grew to $73 billion and $49 billion respectively, reflecting year-over-year growth rates of 77% and 52% for 2017. Excluding DRAM and NAND, the overall semiconductor market grew by 12% year over year. For 2018, non-memory semiconductors are forecast to grow $11 billion to $302 billion. Both DRAM and NAND will continue to grow this year, but are expected to decline from 2019-2021 before recovering slightly in 2022.

The strong memory market resulted in Samsung Electronics capturing the top semiconductor manufacturer spot away from Intel and raised the profile of all the memory manufacturers, which now represent three of the top five semiconductor companies compared to only two the previous year. Revenue concentration continued to increase for the overall market with the top 10 companies making up 60% of the semiconductor market compared to 56% in 2016 and 53% in 2015.

“Market consolidation in the semiconductor industry over the past five years continues to shape the competitive landscape for semiconductor suppliers as each company continues to refine its core markets and make acquisitions to find new and emerging sectors for growth. The pace of change and technology is expected to accelerate as machine learning and autonomous systems enable a more diverse set of architectures to address the opportunity. This will fuel the engine of growth for semiconductor technology over the next decade,” said Mario Morales, program vice president, Semiconductors at IDC.

The automotive market and the industrial markets will continue to be the leading areas of growth for the semiconductor market throughout the forecast period, growing at a 9.6% and 6.8% CAGR from 2017-2022. “The key drivers of electrification, connectivity and infotainment, advanced driver assistance (ADAS), and autonomous driving features will continue to drive the growth of semiconductor content on a per vehicle basis,” said Nina Turner, research manager for Semiconductors at IDC.

Other key findings from IDC’s Semiconductor Application Forecaster (excluding memory) include:

  • Semiconductor revenue for the computing industry segment will decline 4.0% this year and will show a negative CAGR of -0.7% for the 2017-2022 forecast period. Two bright spots for the computing segment are computing and enterprise SSDs, growing in high double digits and 9.8% CAGR respectively for 2017-2022.
  • Semiconductor revenue for the mobile wireless communications segment will grow 5.5% year over year this year with a CAGR of 5.8% for 2017-2022. Semiconductor revenue for 4G mobile phones will experience an annual growth rate of 10.9% in 2018 and a CAGR of 3.1% for 2017-2022. 5G will also drive growth in the later part of the forecast as the technology becomes mainstream by the middle of the next decade.
  • Communications infrastructure semiconductors are forecast to grow at a 1.7% CAGR from 2017-2022 with the strongest growth coming from consumer networks.

Micron Technology, Inc. (Nasdaq:MU), and Intel Corporation today announced production and shipment of the industry’s first 4bits/cell 3D NAND technology. Leveraging a proven 64-layer structure, the new 4bits/cell NAND technology achieves 1 terabit (Tb) density per die, the world’s highest-density flash memory.

The companies also announced development progress on the third-generation 96-tier 3D NAND structure, providing a 50 percent increase in layers. These advancements in the cell structure continue the companies’ leadership in producing the world’s highest Gb/mm2 areal density.

Both NAND technology advancements—the 64-layer QLC and 96-layer TLC technologies —utilize CMOS under the array (CuA) technology to reduce die sizes and deliver improved performance when compared to competitive approaches. By leveraging four planes vs the competitors’ two planes, the new Intel and Micron NAND flash memory can write and read more cells in parallel, which delivers faster throughput and higher bandwidth at the system level.

The new 64-layer 4bits/cell NAND technology enables denser storage in a smaller space, bringing significant cost savings for read-intensive cloud workloads. It is also well-suited for consumer and client computing applications, providing cost-optimized storage solutions.

“With introduction of 64-layer 4bits/cell NAND technology, we are achieving 33 percent higher array density compared to TLC, which enables us to produce the first commercially available 1 terabit die in the history of semiconductors,” said Micron Executive Vice President, Technology Development, Scott DeBoer. “We’re continuing flash technology innovation with our 96-layer structure, condensing even more data into smaller spaces, unlocking the possibilities of workload capability and application construction.”

“Commercialization of 1Tb 4bits/cell is a big milestone in NVM history and is made possible by numerous innovations in technology and design that further extend the capability of our Floating Gate 3D NAND technology,” said RV Giridhar, Intel vice president, Non-Volatile Memory Technology Development. “The move to 4bits/cell enables compelling new operating points for density and cost in Datacenter and Client storage.”

Inorganic semiconductors such as silicon are indispensable in modern electronics because they possess tunable electrical conductivity between that of a metal and that of an insulator. The electrical conductivity of a semiconductor is controlled by its band gap, which is the energy difference between its valence and conduction bands; a narrow band gap results in increased conductivity because it is easier for an electron to move from the valence to the conduction band. However, inorganic semiconductors are brittle, which can lead to device failure and limits their application range, particularly in flexible electronics.

Inorganic semiconducting crystals generally tend to fail in a brittle manner. This is true for zinc sulfide (ZnS); ZnS crystals (A) show catastrophic fracture after mechanical tests under ordinary light-exposure environments (B). However, we found out that ZnS crystals can be plastically deformed up to a deformation strain of εt = 45 % when deformed along the [001] direction in complete darkness even at room temperature (C). Moreover, the optical band gap of the deformed ZnS crystals decreased by 0.6 eV after deformation. Credit: Atsutomo Nakamura

Inorganic semiconducting crystals generally tend to fail in a brittle manner. This is true for zinc sulfide (ZnS); ZnS crystals (A) show catastrophic fracture after mechanical tests under ordinary light-exposure environments (B). However, we found out that ZnS crystals can be plastically deformed up to a deformation strain of εt = 45 % when deformed along the [001] direction in complete darkness even at room temperature (C). Moreover, the optical band gap of the deformed ZnS crystals decreased by 0.6 eV after deformation. Credit: Atsutomo Nakamura

A group at Nagoya University recently discovered that an inorganic semiconductor behaved differently in the dark compared with in the light. They found that crystals of zinc sulfide (ZnS), a representative inorganic semiconductor, were brittle when exposed to light but flexible when kept in the dark at room temperature. The findings were published in Science.

“The influence of complete darkness on the mechanical properties of inorganic semiconductors had not previously been investigated,” study coauthor Atsutomo Nakamura says. “We found that ZnS crystals in complete darkness displayed much higher plasticity than those under light exposure.”

The ZnS crystals in the dark deformed plastically without fracture until a large strain of 45%. The team attributed the increased plasticity of the ZnS crystals in the dark to the high mobility of dislocations in complete darkness. Dislocations are a type of defect found in crystals and are known to influence crystal properties. Under light exposure, the ZnS crystals were brittle because their deformation mechanism was different from that in the dark.

The high plasticity of the ZnS crystals in the dark was accompanied by a considerable decrease in the band gap of the deformed crystals. Thus, the band gap of ZnS crystals and in turn their electrical conductivity may be controlled by mechanical deformation in the dark. The team proposed that the decreased band gap of the deformed crystals was caused by deformation introducing dislocations into the crystals, which changed their band structure.

“This study reveals the sensitivity of the mechanical properties of inorganic semiconductors to light,” coauthor Katsuyuki Matsunaga says. “Our findings may allow development of technology to engineer crystals through controlled light exposure.”

The researchers’ results suggest that the strength, brittleness, and conductivity of inorganic semiconductors may be regulated by light exposure, opening an interesting avenue to optimize the performance of inorganic semiconductors in electronics.

By Walt Custer, Custer Consulting Group

Broad global & U.S. electronic supply chain growth

The first quarter of this year was very strong globally, with growth across the entire electronics supply chain. Although Chart 1 is based on preliminary data, every electronics sector expanded –  with many in double digits. The U.S. dollar-denominated growth estimates in Chart 1 have effectively been amplified by about 5 percent by exchange rates (as stronger non-dollar currencies were consolidated to weaker U.S. dollars), but the first quarter global rates are very impressive nonetheless.

Walt Custer Chart 1

U.S. growth was also good (Chart 2) with Quarter 1 2018 total electronics equipment shipments up 7.2 percent over the same period last year. Since all the Chart 2 values are based on domestic (US$) sales, there is no growth amplification due to exchange rates.

Walt Custer Chart 2

We expect continued growth in Quarter 2 but not at the robust pace as the first quarter.

Chip foundry growth resumes

Taiwan-listed companies report their monthly revenues on a timely basis – about 10 days after month end. We track a composite of 14 Taiwan Stock Exchange listed chip foundries to maintain a “pulse” of this industry (Chart 3).

Walt Custer Chart 3

Chip foundry sales have been a leading indicator for global semiconductor and semiconductor capital equipment shipments. After dropping to near zero in mid-2017, foundry growth is now rebounding.

Chart 4 compares 3/12 (3-month) growth rates of global semiconductor and semiconductor equipment sales to chip foundry sales. The foundry 3/12 has historically led semiconductors and SEMI equipment and is pointing to a coming cyclical upturn. It will be interesting to see how China’s semiconductor industry buildup impacts this historical foundry leading indicator’s performance.

Walt Custer Chart 4

Passive Component Shortages and Price Increases

Passive component availability and pricing are currently major issues. Per Chart 5, Quarter 1 2018 passive component revenues increased almost 25 percent over the same period last year. Inadequate component supplies are hampering many board assemblers with no short-term relief in sight.

Walt Custer Chart 5

Peeking into the Future

Looking forward, the global purchasing managers index (a broad leading indicator) has moderated but is still well in growth territory.

Walt Custer Chart 6

The world business outlook remains positive but requires continuous watching!

Walt Custer of Custer Consulting Group is an  analyst focused on the global electronics industry.

Originally published on the SEMI blog.

By Jay Chittooran

Jonathan Davis 3Testifying before a U.S. interagency panel weighing trade tariffs against China, a representative from the semiconductor manufacturing industry yesterday called for the removal of more than 100 products from the list of proposed tariffs, stressing that an escalation of the U.S.-Sino dispute could trigger a full-blown trade war and hasten deep, unintended damage including higher consumer prices, an expanded U.S. trade deficit, and a slowdown in U.S. economic growth.

Jonathan Davis, global vice president of industry advocacy at SEMI, the global association representing the electronics manufacturing supply chain, threw the industry’s weight behind protections for valuable intellectual property. But Davis argued that “if implemented as proposed, these tariffs will potentially cost tens of millions annually in additional taxes and lost revenue owing to reduced exports, threaten thousands of high-paying U.S. jobs, and not solve U.S. concerns with China.” Davis said the undue harm will ultimately undercut the ability of U.S. chipmakers to sell overseas, stifling innovation and curbing U.S. technological leadership.

In testimony at the hearing before the government panel that included representatives from the U.S. Trade Representative (USTR), Departments of Treasury, Commerce, State and Defense, and the Council of Economic Advisers, Davis explained that more than 100 lines – products defined for the purpose of setting import duties – of the proposed tariffs would hamstring the semiconductor supply chain. The tariff lines include fundamental components of the semiconductor manufacturing process that are oxygen for the chip industry. As part of his testimony, Davis also submitted comments on the impact of the tariffs.

Charles Gray, general counsel at Teradyne, who also testified at the hearing, explained that the tariffs will threaten growth while penalizing U.S. companies with supply chains that touch China. Gray and Davis were among more than 100 industry leaders who provided more than 3,000 comments in the May 15-17 hearing to evaluate the impact and efficacy of the proposed tariffs.

The hearing followed the Trump administration’s heated, longstanding criticism of China for what it considers unfair trade practices, focusing specifically on intellectual property violations. In recent months, the administration has begun implementing trade actions against China that will increase tariffs, restrict cross-border investment, and introduce significant uncertainty for U.S. businesses.

The Section 301 investigation that determined China’s forced transfer of technology and intellectual property discriminated against U.S. firms prompted a proposed 25 percent tariff on $50 billion in U.S. imports from China – a punitive measure that would squarely hit the semiconductor manufacturing industry.

SEMI continues to educate policymakers on the deep damage tariffs would exact on the long-term health of the semiconductor industry and the critical importance of balanced trade to the future of the semiconductor industry.

For more information on trade or how to participate in SEMI’s public policy program, please contact Jay Chittooran, SEMI public policy manager, at [email protected].