Category Archives: Device Architecture

The spread of digital camera applications in vehicles, machine vision, human recognition and security systems, as well as for more powerful camera phones will drive CMOS image sensor sales to an eighth straight record-high level this year with worldwide revenues growing 10% to $13.7 billion, following a 19% surge in 2017, according to IC Insights’ 2018 O-S-D Report—A Market Analysis and Forecast for Optoelectronics, Sensors/Actuators, and Discretes. The new 375-page report shows nothing stopping CMOS image sensors from continuing to set record-high annual sales and unit shipments through 2022 (Figure 1).

Figure 1

Figure 1

CMOS image sensors continue to take marketshare from charge-coupled devices (CCDs) as embedded digital-imaging capabilities expand into a wider range of systems and new end-use applications, says the 2018 O-S-D Report.  With the smartphone market maturing, sales growth in CMOS image sensors slowed to 6% in 2016, but strong demand in other imaging applications played a major factor in boosting revenues by 19% to $12.5 billion last year.  Sales of CCD and other image sensor technologies fell 2% in 2017 to about $1.6 billion after rising 5% in 2016, according to the new IC Insights report.

Overall, CMOS image sensors grabbed 89% of total image sensor sales in 2017 compared to 74% in 2012 and 54% in 2007.  Unit shipments of CMOS imaging devices represented 81% of total image sensors sold in 2017 compared to 64% in 2012 and 63% in 2007.  New CMOS designs keep improving for a variety of light levels (including near darkness at night), high-speed imaging, and greater resolution as well as integrating more functions for specific applications, such as security video cameras, machine vision in robots and cars, human recognition, hand-gesture interfaces, virtual/augmented reality, and medical systems.

In new smartphones, CMOS image sensors are also seeing a new wave of growth with the increase of dual-lens camera systems (using two sensors) for enhanced photography.  Cellular camera phones accounted for 62% of CMOS image sensor sales in 2017, but that marketshare is forecast to slip to 45% in 2022. Automotive CMOS image sensors are projected to grow the fastest among major end-use applications through the five-year forecast shown in the new O-S-D Report, rising by a compound annual growth rate (CAGR) of 38.4% to about 15% of total CMOS image sensor sales in 2022 ($2.8 billion) while camera phone-generated revenues are expected to rise by a CAGR of just 2.2% to $8.6 billion that year.

Spending on RF power semiconductors (for < 4GHz and > 3W) was still moving forward in 2017. The wireless infrastructure segment was flat but other markets – notably the military/defense – are moving forward, according to ABI Research, a market-foresight advisory firm providing strategic guidance on the most compelling transformative technologies. Additionally, Gallium Nitride (GaN) – long seen as the likely promising new “material of choice” for RF power semiconductors – is continuing its march to capture share.

“Gallium Nitride (GaN) has the promise of gaining market share in 2018 and is forecast to be a significant force over the next few years,” noted ABI Research Director Lance Wilson. “It bridges the gap between two older technologies, exhibiting the high-frequency performance of Gallium Arsenide combined with the power handling capabilities of Silicon LDMOS. It is now a mainstream technology which has now achieved measurable market share and in future will capture a significant part of the market.”

Wireless infrastructure while representing about two-thirds of total sales has been anemic recently. Growth for other segments outside of wireless infrastructure are showing mid-single digit CAGR over the forecast period of 2018 to 2023.

The vertical market showing the strongest uptick in the RF power semiconductor adoption business, outside of defense, is Commercial Avionics and Air Traffic Control, which Wilson describes as being now “a significant market.” While the producers of these devices are in the major industrialized countries, this sub-segment market is now so global that end equipment buyers can be from anywhere.

For years, manufacturers have offered computers with increasing amounts of memory packed into smaller devices. But semiconductor companies can’t reduce the size of memory components as quickly as they used to, and current designs are not energy-efficient. Conventional memory devices use transistors and rely on electric fields to store and read out information. An alternative approach being heavily investigated uses magnetic fields to store information. One promising version of magnetic device relies on the magnetoelectric effect which allows an electric field to switch the magnetic properties of the devices. Existing devices, however, tend to require large magnetic and electric fields that are difficult to produce and contain.

One potential solution for this problem is a new switching element made from chromia (Cr2O3), which, one day, may be used in computer memory and flash drives. “The device has better potential for scaling, so it could be made smaller, and would use less energy once it’s suitably refined,” said Randall Victora, a researcher at the University of Minnesota and an author on the paper. The researchers report their findings in Applied Physics Letters, from AIP Publishing.

Computer memory is composed of switching elements, tiny devices that can switch on and off to store bits of information as ones and zeros. Previous researchers discovered that chromia’s magnetoelectric properties means it can be “switched” with only an electric field, but switching requires the presence of a static magnetic field. Building on these elements, Victora and Rizvi Ahmed have created a design for a memory device with a heart of chromia that does not require any externally applied magnetic field to operate.

Their design surrounds the chromia with magnetic material. This provides an effective magnetic field through quantum mechanical coupling to Cr magnetic moments, while allowing devices to be arranged in a way that blocks stray magnetic fields from affecting nearby devices. An element to read out the state of the device, to determine if it’s in one or zero state, is placed on top of the device. This could potentially pack more memory into a smaller space because the interface between the chromia and the magnet is the key to the coupling that makes the device function. As the device shrinks, the greater surface area of the interface relative to its volume improves the operation. This property is an advantage over conventional semiconductors, where increases in surface area as size shrinks lead to greater charge leakage and heat loss.

Next, Victora and Ahmed aim to collaborate with colleagues who work with chromia to build and test the device. If successfully fabricated, then the new device could potentially replace dynamic random access memory in computers.

“DRAM is a huge market. It provides the fast memory inside the computer, but the problem is that it leaks a lot of charge, which makes it very energy-inefficient,” Victora said. DRAM is also volatile, so information disappears once the power source is interrupted, like when a computer crash erases an unsaved document. This device, as described in the paper, would be nonvolatile.

However, such a memory device will likely take years to perfect. One significant barrier is the device’s heat tolerance. Computers generate a lot of heat, and modeling predicts that the device would stop functioning around 30 degrees Celsius, the equivalent of a hot summer day. Optimizing the chromia, perhaps by doping it with other elements, may improve its functioning and make it more suitable to replace existing memory devices.

 

Osram has added to its expertise in semiconductor-based optical security technology by acquiring US-based Vixar Inc. Already a technology leader in infrared LEDs and infrared laser diodes, Osram will have a unique breadth of technological expertise and an expanded product portfolio after bringing on board Vixar’s specialist capabilities in the field of VCSEL. While currently known primarily for identification applications in mobile devices, VCSEL also can be used to recognize gestures and measure distances in medical, industrial and automotive applications. Vixar was founded by pioneers in the VCSEL industry, having first brought VCSEL to the data communication market in the late 1990s, and more recently by founding Vixar in 2005 to pursue sensing applications. Approximately 20 employees of the company, which is based in Plymouth, Minnesota, will transfer to Osram as a result of the acquisition. Vixar is profitable both on an operational and net results level. The parties to the deal have agreed not to disclose financial details. Closing of the transaction is expected in summer.

“The acquisition of Vixar is adding to our expertise, particularly in the fast-growing market for security technologies,” said Olaf Berlien, CEO of OSRAM Licht AG. Osram is a technology leader in infrared optical semiconductors and has already succeeded in bringing to market light sources for fingerprint sensors, iris scanners, and 2D facial recognition. The acquired capabilities will pave the way for further security technologies, including ultra-compact 3D facial recognition. In addition to unlocking smartphones and other consumer electronics devices, such technologies also can be used for high-security access controls in industry.

The way in which VCSEL technology captures 3D environmental data has applications in everything from gesture recognition, augmented reality, robotics and proximity sensors to autonomous driving. VCSEL stands for vertical cavity surface emitting laser and is a special type of laser diode in which the light is emitted perpendicular to the surface of the semiconductor chip. Vixar is a fabless semiconductor company, and has developed a robust volume supply chain consisting of merchant foundries serving the optoelectronic market. Osram’s depth and breadth of semiconductor experience will further strengthen the manufacturing capabilities for the rapidly growing VCSEL market.

Engineers at the University of California, Riverside, have demonstrated prototype devices made of an exotic material that can conduct a current density 50 times greater than conventional copper interconnect technology.

Current density is the amount of electrical current per cross-sectional area at a given point. As transistors in integrated circuits become smaller and smaller, they need higher and higher current densities to perform at the desired level. Most conventional electrical conductors, such as copper, tend to break due to overheating or other factors at high current densities, presenting a barrier to creating increasingly small components.

Microscopy image of an electronic device made with 1D ZrTe3 nanoribbons. The nanoribbon channel is indicated in green color. The metal contacts are shown in yellow color. Note than owing to the nanometer scale thickness the yellow metal contacts appear to be under the green channel while in reality they are on top. Credit: Balandin lab, UC Riverside

Microscopy image of an electronic device made with 1D ZrTe3 nanoribbons. The nanoribbon channel is indicated in green color. The metal contacts are shown in yellow color. Note than owing to the nanometer scale thickness the yellow metal contacts appear to be under the green channel while in reality they are on top. Credit: Balandin lab, UC Riverside

The electronics industry needs alternatives to silicon and copper that can sustain extremely high current densities at sizes of just a few nanometers.

The advent of graphene resulted in a massive, worldwide effort directed at investigation of other two-dimensional, or 2D, layered materials that would meet the need for nanoscale electronic components that can sustain a high current density. While 2D materials consist of a single layer of atoms, 1D materials consist of individual chains of atoms weakly bound to one another, but their potential for electronics has not been as widely studied.

One can think of 2D materials as thin slices of bread while 1D materials are like spaghetti. Compared to 1D materials, 2D materials seem huge.

A group of researchers led by Alexander A. Balandin, a distinguished professor of electrical and computer engineering in the Marlan and Rosemary Bourns College of Engineering at UC Riverside, discovered that zirconium tritelluride, or ZrTe3, nanoribbons have an exceptionally high current density that far exceeds that of any conventional metals like copper.

The new strategy undertaken by the UC Riverside team pushes research from two-dimensional to one-dimensional materials­­– an important advance for the future generation of electronics.

“Conventional metals are polycrystalline. They have grain boundaries and surface roughness, which scatter electrons,” Balandin said. “Quasi-one-dimensional materials such as ZrTe3consist of single-crystal atomic chains in one direction. They do not have grain boundaries and often have atomically smooth surfaces after exfoliation. We attributed the exceptionally high current density in ZrTe3 to the single-crystal nature of quasi-1D materials.”

In principle, such quasi-1D materials could be grown directly into nanowires with a cross-section that corresponds to an individual atomic thread, or chain. In the present study the level of the current sustained by the ZrTe3 quantum wires was higher than reported for any metals or other 1D materials. It almost reaches the current density in carbon nanotubes and graphene.

Electronic devices depend on special wiring to carry information between different parts of a circuit or system. As developers miniaturize devices, their internal parts also must become smaller, and the interconnects that carry information between parts must become smallest of all. Depending on how they are configured, the ZrTe3 nanoribbons could be made into either nanometer-scale local interconnects or device channels for components of the tiniest devices.

The UC Riverside group’s experiments were conducted with nanoribbons that had been sliced from a pre-made sheet of material. Industrial applications need to grow nanoribbon directly on the wafer. This manufacturing process is already under development, and Balandin believes 1D nanomaterials hold possibilities for applications in future electronics.

“The most exciting thing about the quasi-1D materials is that they can be truly synthesized into the channels or interconnects with the ultimately small cross-section of one atomic thread– approximately one nanometer by one nanometer,” Balandin said.

TowerJazz today announced the release of its 300mm 65nm BCD (Bipolar-CMOS-DMOS) process, the most advanced power management platform for up to 16V operation and 24V maximum voltage.  This technology is manufactured in TowerJazz’s Uozu, Japan facility, with best-in-class quality and cycle time, and is based on the Company’s 300mm 65nm automotive qualified flows.

This platform provides significant material competitive advantages for any type of power management chip up to 16V regardless of application, including a wide variety of products such as: PMICs, load switches, DC-DC converters, LED drivers, motor drivers, battery management, analog and digital controllers, and more. IHS Markit Power IC Analyst, Kevin Anderson forecasts a $9.4 billion available market, which this technology addresses, in 2018 with continual growth.

TowerJazz’s 65nm BCD process is leading this low voltage market segment with the highest power efficiency, very small die size, best digital integration capability; and superior cost effectiveness through both the smallest aerial footprint and the lowest mask count.

The process includes four leading edge power LDMOS transistors: 5V, 7V, 12V and 16V operation, each with the best available Rdson and Qgd parameters. In addition to the new aforementioned cost and figure of merit benchmarks, multiple chips can be integrated to a single monolithic IC solution replacing a multiple chip module for an improved system cost structure and system performance.

TowerJazz’s power transistors are fully isolated to withstand high currents, all with an ultra-low Rdson, e.g. less than 1mΩ*mm² for the 5V LDMOS. For products which operate at the megahertz (MHz) switching frequencies, the 65nm BCD power transistors benefit from a very low Qgd down to 2.6mΩ*nC. In addition, very low metal resistance is achieved using a single or dual 3.3um top thick copper. The 65nm BCD also offers aggressive 113Kgate/mm² 5V digital density and an 800Kgate/mm² 1.2V digital library.

“This new 65nm BCD platform establishes TowerJazz as a technology leader in the related growing markets for up to 16V power applications,” said Shimon Greenberg, Vice President and General Manager of Power Management & Mixed-Signal/CMOS Business Unit, TowerJazz. “Best addressing the vast low voltage power management market segment, we are experiencing very high interest from early adopter customers and plan a mass production ramp by the fourth quarter of 2018.”

TowerJazz will be exhibiting at ISPSD, the 30th IEEE International Symposium on Power Semiconductor Devices and ICs on May 13-17, 2018 in Chicago, USA.

The top 10 IC suppliers in the $54.5 billion analog market last year accounted for 59% of the category’s worldwide sales in 2017, according to a recent monthly update to IC Insights’ 2018 McClean Report. Collectively, the top 10 companies generated $32.3 billion in analog IC sales last year compared to $28.4 billion in 2016, which was a 14% increase and a gain of two percentage points in marketshare during 2017, said the 50-page April Update to The McClean Report.  Eight of the top-10 suppliers exceeded the 10% growth rate of the total analog market in 2017, according to the update.

With analog sales of $9.9 billion and 18% marketshare, Texas Instruments was again the leading supplier of analog integrated circuits in 2017.  In 2016, TI’s marketshare was 17% in analog ICs.  The company’s analog sales increased by about $1.4 billion last year—rising 16%—compared to 2016 and were more than twice that of second-ranked Analog Devices (ADI). TI’s 2017 analog revenue represented 76% of its $13.0 billion in total IC sales and 71% of its $13.9 billion total semiconductor revenue, based on IC Insights’ estimates.

3fed36cb-49c2-4a3f-a24c-a5fd1acf60c4

Figure 1

TI was among the first companies to manufacture analog semiconductors on 300mm wafers.  TI has claimed that manufacturing analog ICs on 300mm wafers gives it a 40% cost advantage per unpackaged chip compared to using 200mm wafers.  In 2017, about half of TI’s analog revenue was generated on devices built using 300mm wafers.

Second-place ADI registered a 14% increase in analog IC sales in 2017 to $4.3 billion, according to IC Insights’ supplier ranking. The 2016 and 2017 revenue numbers shown for ADI include sales from Linear Technology, which was acquired by the company in 1Q17 for $15.8 billion.

NXP was the only supplier in the top-10 ranking that experienced a decline (-1%) in its analog sales last year.  Some of NXP’s analog revenue decline can be attributed to the sale of its Standard Products business to a consortium of Chinese investors consisting of JAC Capital and Wise Road Capital.  The $2.75 billion transaction was completed in February 2017.  The Standard Products business was renamed Nexperia and headquartered in the Netherlands.

Among the top 10, ON Semiconductor showed the largest analog sales gain in 2017, with revenues increasing 35% to $1.8 billion, which represented a 3% share of the market.  This follows a 16% rise in its analog sales in 2016. Some of the strong increases in sales during the last two years were a result of ON Semi’s acquisition of Fairchild Semiconductor in September 2016 for $2.4 billion.  ON’s analog business was also boosted in 2017 by record sales of its power management products to the automotive market, specifically for active safety, powertrain, body electronics, and lighting applications.

Mentor, a Siemens business, has announced that several tools in its Calibre® nmPlatform and Analog FastSPICE (AFS™) Platform have been certified by TSMC for the latest versions of TSMC’s 5nm FinFET and 7nm FinFET Plus processes. Mentor also announced it has updated its Calibre nmPlatform tools in support of TSMC’s Wafer-on-Wafer (WoW) stacking technology. These Mentor tools and TSMC’s new processes will enable mutual customers to more quickly deliver silicon innovations in high-growth markets.

“Mentor continues to increase its value to the TSMC ecosystem by offering more features and solutions in support of our most advanced processes,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “By continuing to innovate leading-edge electronic design automation (EDA) technologies for our new processes, Mentor is again proving its commitment to TSMC and our mutual customers.”

Mentor’s enhanced tools for TSMC 5nm FinFET and 7nm FinFET Plus processes

Mentor worked closely with TSMC to certify various tools in Mentor’s Calibre nmPlatform – including Calibre nmDRC™, Calibre nmLVS™, Calibre PERC™, Calibre YieldEnhancer, and Calibre xACT™ – for TSMC’s 5nm FinFET and 7nm FinFET Plus processes. These Calibre solutions now have new measurements and checks including, but not limited to, supporting extreme ultraviolet (EUV) lithography requirements jointly defined with TSMC. Mentor’s Calibre nmPlatform team is also working with TSMC to address physical verification runtime performance by enhancing scalability of multi-CPU runs to improve productivity. Mentor’s AFS platform, including the AFS Mega circuit simulator, is also now certified for TSMC’s 5nm FinFET and 7nm FinFET Plus processes.

Mentor’s enhanced tools for TSMC’s WoW stacking technology

Mentor made enhancements to its Calibre nmPlatform tools in support of the WoW packaging. Enhancements include DRC and LVS signoff for dice with backside through-silicon vias (BTSV), interface alignment and connectivity checks for die-to-die as well as die-to-package stacking. Further enhancements include parasitic extraction on backside routing layers, interposers with through-silicon vias (TSVs), and interface coupling.

Calibre Pattern Matching for TSMC’s 7nm SRAM Array Examination Utility

Mentor worked closely with TSMC to integrate Calibre Pattern Matching into TSMC’s 7nm SRAM Array Examination Utility. This flow helps customers to ensure their SRAM implementations are constructed to meet process requirements. This automation enables customers to tape out successfully. The SRAM Array Examination Utility is available to TSMC’s customers for 7nm production.

“TSMC continues to develop innovative silicon processes that enable our mutual customers to bring to market many of the world’s most advanced ICs,” said Joe Sawicki, vice president and general manager of the Design-to-Silicon Division at Mentor, a Siemens business. “We, at Mentor, are proud to not only lead the way in certifying our platforms for TSMC’s latest processes, we are also proud of our close partnership with TSMC in developing new technologies that help customers achieve production silicon faster.”

To learn more, visit Mentor at booth #408 at TSMC’s Technology Symposium on May 1, 2018 at the Santa Clara Convention Center in Santa Clara, California.

 

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $111.1 billion during the first quarter of 2018, an increase of 20 percent compared to the first quarter of 2017, but 2.5 percent less than the fourth quarter of 2017. Sales for the month of March 2018 came in at $37.0 billion, an increase of 20 percent compared to the March 2017 total of $30.8 billion and 0.7 percent more than the February 2018 total of $36.8 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market has demonstrated impressive growth through the first quarter of 2018, far exceeding sales through the same point in 2017, which was a record year for semiconductor revenues,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales in March increased year-to-year for the 20th consecutive month. All regional markets experienced double-digit growth compared to last year, and all major semiconductor product categories experienced year-to-year growth, with memory products continuing to lead the way.”

Year-to-year sales increased across all regions in March: the Americas (35.7 percent), Europe (20.6 percent), China (18.8 percent), Asia Pacific/All Other (13.3 percent), and Japan (12.4 percent). Month-to-month sales increased in Europe (3.9 percent), China (2.2 percent), Japan (0.5 percent), and Asia Pacific/All Other (0.2 percent), but decreased slightly in the Americas (-2.0 percent).

For comprehensive monthly semiconductor sales data and detailed WSTS Forecasts, consider purchasing the WSTS Subscription Package. For detailed data on the global and U.S. semiconductor industry and market, consider purchasing the 2017 SIA Databook.

Mar 2018

Billions

Month-to-Month Sales                              

Market

Last Month

Current Month

% Change

Americas

8.26

8.09

-2.0%

Europe

3.43

3.57

3.9%

Japan

3.18

3.19

0.5%

China

11.70

11.95

2.2%

Asia Pacific/All Other

10.19

10.22

0.2%

Total

36.76

37.02

0.7%

Year-to-Year Sales                         

Market

Last Year

Current Month

% Change

Americas

5.96

8.09

35.7%

Europe

2.96

3.57

20.6%

Japan

2.84

3.19

12.4%

China

10.06

11.95

18.8%

Asia Pacific/All Other

9.02

10.22

13.3%

Total

30.84

37.02

20.0%

Three-Month-Moving Average Sales

Market

Oct/Nov/Dec

Jan/Feb/Mar

% Change

Americas

8.95

8.09

-9.6%

Europe

3.37

3.57

5.8%

Japan

3.24

3.19

-1.5%

China

12.01

11.95

-0.5%

Asia Pacific/All Other

10.41

10.22

-1.8%

Total

37.99

37.02

-2.5%

Research appearing today in Nature Communications finds useful new information-handling potential in samples of tin(II) sulfide (SnS), a candidate “valleytronics” transistor material that might one day enable chipmakers to pack more computing power onto microchips.

Valleytronics utilizes different local energy extrema (valleys) with selection rules to store 0s and 1s. In SnS, these extrema have different shapes and responses to different polarizations of light, allowing the 0s and 1s to be directly recognized. This schematic illustrates the variation of electron energy in different states, represented by curved surfaces in space. The two valleys of the curved surface are shown. Credit: Berkeley Lab

Valleytronics utilizes different local energy extrema (valleys) with selection rules to store 0s and 1s. In SnS, these extrema have different shapes and responses to different polarizations of light, allowing the 0s and 1s to be directly recognized. This schematic illustrates the variation of electron energy in different states, represented by curved surfaces in space. The two valleys of the curved surface are shown. Credit: Berkeley Lab

The research was led by Jie Yao of the Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) and Shuren Lin of UC Berkeley’s Department of Materials Science and Engineering and included scientists from Singapore and China. Berkeley Lab’s Molecular Foundry, a DOE Office of Science user facility, contributed to the work.

For several decades, improvements in conventional transistor materials have been sufficient to sustain Moore’s Law – the historical pattern of microchip manufacturers packing more transistors (and thus more information storage and handling capacity) into a given volume of silicon. Today, however, chipmakers are concerned that they might soon reach the fundamental limits of conventional materials. If they can’t continue to pack more transistors into smaller spaces, they worry that Moore’s Law would break down, preventing future circuits from becoming smaller and more powerful than their predecessors.

That’s why researchers worldwide are on the hunt for new materials that can compute in smaller spaces, primarily by taking advantage of the additional degrees of freedom that the materials offer – in other words, using a material’s unique properties to compute more 0s and 1s in the same space. Spintronics, for example, is a concept for transistors that harnesses the up and down spins of electrons in materials as the on/off transistor states.

Valleytronics, another emerging approach, utilizes the highly selective response of candidate crystalline materials under specific illumination conditions to denote their on/off states – that is, using the materials’ band structures so that the information of 0s and 1s is stored in separate energy valleys of electrons, which are dependent on the crystal structures of the materials.

In this new study, the research team has shown that tin(II) sulfide (SnS) is able to absorb different polarizations of light and then selectively reemit light of different colors at different polarizations. This is useful for concurrently accessing both the usual electronic – and the material’s valleytronic – degrees of freedom, which would substantially increase the computing power and data storage density of circuits made with the material.

“We show a new material with distinctive energy valleys that can be directly identified and separately controlled,” said Yao. “This is important because it provides us a platform to understand how valley signatures are carried by electrons and how information can be easily stored and processed between the valleys, which are of both scientific and engineering significance.”

Lin, the first author of the paper, said the material is different from previously investigated candidate valleytronics materials because it possesses such selectivity at room temperature without additional biases apart from the excitation light source, which alleviates the previously stringent requirements in controlling the valleys. Compared to its predecessor materials, SnS is also much easier to process.

With this finding, researchers will be able to develop operational valleytronic devices, which may one day be integrated into electronic circuits. The unique coupling between light and valleys in this new material may also pave the way toward future hybrid electronic/photonic chips.

Berkeley Lab’s “Beyond Moore’s Law” initiative leverages the basic science capabilities and unique user facilities of Berkeley Lab and UC Berkeley to evaluate promising candidates for next-generation electronics and computing technologies. Its objective is to build close partnerships with industry to accelerate the time it typically takes to move from the discovery of a technology to its scale-up and commercialization.