Category Archives: Device Architecture

Toshiba Electronic Devices & Storage Corporation (“Toshiba”) has released two new MOSFETs “TPHR7904PB” and “TPH1R104PB” housed in the small low-resistance SOP Advance (WF) package, as new additions to the automotive 40V N-channel power MOSFET series. Mass production starts today.

Fabricated using the latest ninth generation trench U-MOS IX-H process and housed in a small low-resistance package, the new MOSFETs provide low on-resistance and thus help reduce conduction loss. The U-MOS IX-H design also lowers switching noise compared with Toshiba’s previous design (U-MOS IV), helping to reduce EMI (Electromagnetic Interference).

The SOP Advance (WF) package adopts a wettable flank terminal structure, which enables AOI (Automated Optical Inspection) after soldering.

Applications

  • Electric power steering (EPS)
  • Load switches
  • Electric pumps

Features

  • Provides a maximum on-resistance, RDS(ON)max, of 0.79 mΩ from the use of the U-MOS IX-H process and the SOP Advance(WF) package.
  • Low-noise characteristics reduce electromagnetic interference (EMI).
  • Available in a small low-resistance package with a wettable flank terminal structure.

Main Specifications

(Unless otherwise specified, @Ta=25°C)

Part Number

Drain-Source
voltage
VDSS
(V)

Drain
current
(DC)
ID
(A)

Drain-Source
on-resistance

RDS(ON) max.(mΩ)

Built-in
Zener Diode
between
Gate-Source

 Series

@VGS=6V

@VGS=10V
TPH1R104PB 40 120 1.96 1.14 No U-MOS IX
TPHR7904PB 150 1.3 0.79 No U-MOS IX

Veeco Instruments Inc. (NASDAQ: VECO) today announced its GENxcel R&D Molecular Beam Epitaxy (MBE) System earned the 2018 Compound Semiconductor (CS) Industry Innovation Award. Hosted by Compound Semiconductor magazine, the CS Industry Awards celebrate the success of companies across five unique categories. Specifically, the Innovation Award honors the most significant breakthrough in compound semiconductor manufacturing over the last 12 months.

“We are honored to have the GENxcel MBE System recognized by Compound Semiconductor and our industry peers. The recognition is especially meaningful because winners are voted on by our respected colleagues, customers and collaborators,” said Gerry Blumenstock, vice president and general manager of MBE and ALD products at Veeco. “We continue to be committed to creating the most advanced and highest quality tools to support leading-edge compound semiconductor R&D and production.”

The GENxcel R&D MBE system builds on the success of the GENxplor® MBE system designed for compound semiconductor R&D and pilot production markets. The system produces high-quality epitaxial layers on substrates up to 100mm in diameter. The innovative architectural concept of GENxcel reduces the system footprint by 40 percent compared to similar 100mm wafer systems, improves the ease of maintenance, and allows users to easily integrate additional deposition and analysis chambers—specifically Veeco’s new atomic layer deposition (ALD) product line.

The CS Industry Awards is a peer-voted awards program honoring people, processes and products within the compound semiconductor industry. Winners were honored at a ceremony on April 10 in conjunction with the CS International Conference in Brussels, Belgium. For a complete list of 2018 winners, visit www.csawards.net/winners.

Previous Veeco products that have won the CS Industry Innovation Award include the TurboDisc® EPIK700™ Gallium Nitride (GaN) Metal Organic Chemical Vapor Deposition (MOCVD) System in 2015, the GENxplor MBE system in 2014, and the TurboDisc® MaxBright® Multi-Reactor MOCVD System in 2012. To learn more about Veeco’s GENxcel R&D MBE system, please visithttp://www.veeco.com/products/genxcel-randd-mbe-system.

Research included in the April Update to the 2018 edition of IC Insights’ McClean Report shows that the world’s leading semiconductor suppliers significantly increased their marketshare over the past decade. The top-5 semiconductor suppliers accounted for 43% of the world’s semiconductor sales in 2017, an increase of 10 percentage points from 10 years earlier (Figure 1).  In total, the 2017 top-50 suppliers represented 88% of the total $444.7 billion worldwide semiconductor market last year, up 12 percentage points from the 76% share the top 50 companies held in 2007.

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Figure 1

As shown, the top 5, top 10, and top 25 companies’ share of the 2017 worldwide semiconductor market each increased from 10-12 percentage points over the past decade.  With the surge in mergers and acquisitions expected to continue over the next few years (e.g., Qualcomm and NXP), IC Insights believes that consolidation will raise the shares of the top suppliers to even loftier levels.

As shown in Figure 2, Japan’s total presence and influence in the IC marketplace has waned significantly since 1990, with its IC marketshare (not including foundries) residing at only 7% in 2017.  Once-prominent Japanese names missing from the top IC suppliers list are NEC, Hitachi, Mitsubishi, and Matsushita. Competitive pressures from South Korean IC suppliers—especially in the memory market—have certainly played a significant role in changing the look of the IC marketshare figures over the past 27 years. Moreover, depending on the outcome of the sale of Toshiba’s NAND flash division, the Japanese-companies’ share of the IC market could fall even further from its already low level.

Figure 2

Figure 2

With strong competition reducing the number of Japanese IC suppliers, the loss of its vertically integrated businesses, missing out on supplying ICs for several high-volume end-use applications, and its collective shift toward the fab-lite IC business model, Japan has greatly reduced its investment in new semiconductor wafer fabs and equipment.  In fact, Japanese companies accounted for only 5% of total semiconductor industry capital expenditures in 2017 (two points less than the share of the IC market they held last year), a long way from the 51% share of spending they represented in 1990.

ON Semiconductor (Nasdaq: ON) has introduced the industry’s first 1/1.7-inch 2.1 megapixel CMOS image sensor featuring ON Semiconductor’s newly developed 4.2μm Back Side Illuminated (BSI) pixels – the AR0221 delivers class-leading low light sensitivity for industrial applications.

The AR0221 offers exceptional 3-exposure line-interleaved High Dynamic Range (HDR) with a sensor resolution of 1936H x 1096V, supporting frame rates of 1080p at 30 fps and an outstanding Signal-Noise Ratio (SNR) across visible and near-infrared wavelengths. Its 16:9 ratio with vivid colors and high contrast make it ideal for demanding industrial applications.

Gianluca Colli, Vice President and General Manager, Consumer Solution Division of Image Sensor Group at ON Semiconductor, said: “The AR0221 represents the industry’s best CMOS image sensor in this class, thanks to its outstanding low light sensitivity and SNR performance. By including features like windowing, auto black level correction and an onboard temperature sensor, ON Semiconductor has produced an image sensor that will enable a new generation of security and surveillance cameras.”

The sensor offers dual data interfaces in the form of 4-lane MIPI CSI-2 and HiSPi SLVS. Designed to meet industrial-grade specifications, the AR0221 can operate in harsh outdoor environments where operating temperatures can range between -30°C and +85°C. Packaged in a durable, reliable and robust iBGA package with anti-reflection coating on its cover glass, the AR0221 is programmable through a simple two-wire serial interface.

When power generators like windmills and solar panels transfer electricity to homes, businesses and the power grid, they lose almost 10 percent of the generated power. To address this problem, scientists are researching new diamond semiconductor circuits to make power conversion systems more efficient.

The view of the H-diamond MOSFET NOR logic circuit from above (left), and the operation of the NOR logic circuits, showing that the circuit only produces voltage when both inputs are at zero. Credit: Liu et al.

The view of the H-diamond MOSFET NOR logic circuit from above (left), and the operation of the NOR logic circuits, showing that the circuit only produces voltage when both inputs are at zero. Credit: Liu et al.

A team of researchers from Japan successfully fabricated a key circuit in power conversion systems using hydrogenated diamond (H-diamond.) Furthermore, they demonstrated that it functions at temperatures as high as 300 degrees Celsius. These circuits can be used in diamond-based electronic devices that are smaller, lighter and more efficient than silicon-based devices. The researchers report their findings this week in Applied Physics Letters, from AIP Publishing.

Silicon’s material properties make it a poor choice for circuits in high-power, high-temperature and high-frequency electronic devices. “For the high-power generators, diamond is more suitable for fabricating power conversion systems with a small size and low power loss,” said Jiangwei Liu, a researcher at Japan’s National Institute for Materials Science and a co-author on the paper.

In the current study, researchers tested an H-diamond NOR logic circuit’s stability at high temperatures. This type of circuit, used in computers, gives an output only when both inputs are zero. The circuit consisted of two metal-oxide-semiconductor field-effect transistors (MOSFETs), which are used in many electronic devices, and in digital integrated circuits, like microprocessors. In 2013, Liu and his colleagues were the first to report fabricating an E-mode H-diamond MOSFET.

When the researchers heated the circuit to 300 degrees Celsius, it functioned correctly, but failed at 400 degrees. They suspect that the higher temperature caused the MOSFETs to breakdown. Higher temperatures may be achievable however, as another group reported successful operation of a similar H-diamond MOSFET at 400 degrees Celsius. For comparison, the maximum operation temperature for silicon-based electronic devices is about 150 degrees.

In the future, the researchers plan to improve the circuit’s stability at high temperatures by altering the oxide insulators and modifying the fabrication process. They hope to construct H-diamond MOSFET logic circuits that can operate above 500 degrees Celsius and at 2.0 kilovolts.

“Diamond is one of the candidate semiconductor materials for next-generation electronics, specifically for improving energy savings,” said Yasuo Koide, a director at the National Institute for Materials Science and co-author on the paper. “Of course, in order to achieve industrialization, it is essential to develop inch-sized single-crystal diamond wafers and other diamond-based integrated circuits.”

The 2018 Symposia on VLSI Technology & Circuits will deliver a unique perspective into the technological ecosystem of converging industry trends – machine learning, IoT, artificial intelligence, wearable/implantable biomedical applications, big data, and cloud computing – the emerging technologies needed for ‘smart living.’ In a weeklong conference packed with technical presentations, a demonstration session, panel discussions, focus sessions, short courses, and a new “Friday Forum” on machine learning, the microelectronics industry’s premiere international conference covers technology, circuits, and systems with a range and scope unlike any other conference.

Built around the theme of “Technology, Circuits & Systems for Smart Living,” the Symposia programintegrates advanced technology developments, innovative circuit design, and the applications that they enable as part of our global society’s adoption of smart, connected devices and systems that change the way humans interact with each other.

Plenary Sessions (June 19):
The Symposia will open with two technology plenary sessions, including “Memory Technology: The Core to Enable Future Computing Systems” by Scott DeBoer, executive VP for technology development, Micron; and “Revolutionizing Cancer Genomic Medicine by Artificial Intelligence & Supercomputing with Big Data” by Satoru Miyano, director of the Human Genome Center, Institute of Medical Science at University of Tokyo.

The following Circuits plenary sessions include “Hardware-Enabled Artificial Intelligence” by Dr. Bill Dally, chief scientist & senior VP, Nvidia; and “Semiconductor Technologies Accelerate Our Future Vision: ‘ANSHIN Platform'” by Tsuneo Komatsuzaki, advisor, SECOM.

Focus Sessions (June 19, 20 & 21):
As part of the Symposia’s ongoing program integration, a series of joint focus sessions will be held to present contributed papers from the Technology and Circuits Symposia on June 20 and 21. Topics will include: “Heterogeneous System Integration,” “Power Devices & Circuits,” “New Devices & Systems for AI,” and “Design & Technology Co-Optimization (DTCO) in Advanced CMOS Technology.”

On June 19, the Technology focus sessions will include: “Back-End Compatible Devices & Advanced Thermal Management“ and “Sensors and Devices for IoT, Medicine, & Smart Living.” The Circuits focus sessions, held on June 21, include “Machine Learning Circuits & SoCs,” and “Advanced Wireline Techniques.”

Evening Panel Sessions (June 18 & 19):
A joint panel discussion, bringing together leading experts from Technology & Circuits programs will be held June 18 to answer the question, “Is the CPU Dying or Dead? Are Accelerators the Future of Computation?”

As Moore’s Law slows down and processor architecture innovations move away from single thread performance, the future of computing seems to be moving away from the general purpose CPU. Is the era of the CPU over? Will future CPUs simply coordinate activity among accelerators and other specialized processing units? The panel will examine future computing workloads as well as the innovative technology and circuit solutions that enable them, from moving computation closer to memory, and developing bio-inspired systems.

The Technology evening panel session panel discussion, held on June 19 will examine “Storage Class Memories: Who Cares? DRAM is Scaling Fine, NAND Stacking is Great.” Memory – DRAM and NAND scaling – though difficult, has persisted due to rapid innovations and continued engineering. Although there are new economic and fundamental challenges posed to continued memory scaling, a new class of memories – Storage Class memories, appears to bridge the latency gap that exists in the memory hierarchy and promises to improve system performance. Now the real question becomes – who really cares now? System architects, DRAM/NAND manufacturers? End users? The panel will discuss the challenges and opportunities of storage class memories in the environment where DRAM and NAND scaling continue.

The question to be addressed by the Circuits evening panel session, also held on June 19, is “What’s The Next Big Thing After Smartphones?” Although smartphones have driven the industry for more than a decade, the pace of innovation is slowing, and market saturation is occurring. What will be the next big thing? The Internet of Things? Automotive electronics? Virtual reality? Something else? A set of panelists with diverse expertise will discuss the possibilities.

Thursday Luncheon (June 21):
Continuing the Symposia’s tradition of thought-provoking presentations centered around the conference theme is the Thursday luncheon talk, entitled “The Hardware of The Mind, from Turing to Today,” by Grady Booch, chief scientist for software engineering at IBM Research. As scientists continue to the computing power of the human mind, they strive to bridge the gap between the physicality of silicon and the exquisite wonder of the brain. This presentation examines the journey of the hardware of the mind – from the Iliad, to da Vinci, to Edison, to Turing, to today – including an examination of how the growing understanding of the brain transforms the engineering of silicon, and how the laws of physics as well as the laws of humanity constrain that journey.

Full Day Short Courses (June 18):
The Technology Short Course – “Device & Integration Technologies for Sub-5nm CMOS & the Next Wave of Computing” will cover a range of topics, including CMOS technology beyond the 5nm node, MOL/BEOL interconnects, atomic-level analysis for FinFET & Nanowire design, 3D integration for image sensors, neuromorphic AI hardware, memory technologies for AI/machine learning, and sensors & analog devices for next generation computing.

The first Circuits Short Course – “Designing for the Next Wave of Cloud Computing” will address advanced computer architectures, GPU applications and FPGA acceleration, the evolution of memory and in-memory computation, and advanced packaging, power delivery and cooling for cloud computing, as well as the impact of quantum computing.

The second Circuits Short Course – “Bio-Sensors, Circuits & Systems for Wearable & Implantable Medical Devices” will cover circuits and systems for mobile healthcare, analog front-ends for bio-sensors, digital phenotyping using wearable sensors, bi-directional neural interfacing, body-area networking and body-coupled communications, ultrasound-on-a-chip, as well as a CMOS-based implantable retinal prosthesis.

Demonstration Session (June 18):
Following a successful launch last year in Kyoto, the popular demonstration session will again be part of the Symposia program, providing participants an opportunity for in-depth interaction with authors of selected papers from both Technology and Circuits sessions. These demonstrations will illustrate technological concepts and analyses through table-top presentations that show device characterization, chip operational results, and potential applications for circuit-level innovations.

Friday Forum (June 22):
New to the Symposia program this year will be the Friday Forum – a full-day series of presentations focusing on how technology and circuit designers engage in and drive the future of AI/machine learning systems, a subject area that continues to evolve as an impactful driver of the integrated systems that are part of the Symposia’s “Smart Living” theme. “Machine Learning Today & Tomorrow: A Technology, Circuits & Systems View” will provide the foundations and performance metrics for machine learning systems, an examination of advanced and emerging circuit architectures for next-generation systems, as well as highlighting tools and datasets for benchmarking and evaluating service-oriented architecture (SoA) machine learning systems.

The annual Symposium on VLSI Technology & Circuits will be held at the Hilton Hawaiian Village in Honolulu, Hawaii from June 18-22, 2018, with Short Courses held on June 18 and a special Friday Forum dedicated to machine learning/AI topics on June 22. The two conferences have been held together since 1987, providing an opportunity for the world’s top device technologists, circuit and system designers to exchange leading edge research on microelectronics technology, with alternating venues between Hawaii and Japan. A single registration enables participants to attend both Symposia.

POET Technologies Inc. (“POET”) (TSX Venture:PTK) (OTCQX:POETF), a designer, developer and manufacturer of optoelectronic devices, including light sources, passive wave guides and Photonic Integrated Circuits (PIC), today announced a master collaboration agreement with SilTerra, a Malaysia-based semiconductor wafer foundry, for the co-development of certain fabrication processes and the manufacturing of POET’s Optical Interposer Platform. The partnership is expected to accelerate the path to commercial production of the Optical Interposer, which will enable optical engines for single-mode transceiver modules and other high bandwidth devices.

Together, the companies will bring-up critical waveguide processes previously developed by POET for its Optical Interposer, and implement the process flows on newly purchased equipment at SilTerra’s world-class 8″ silicon foundry in Kulim, Malaysia. In support of this activity, SilTerra has agreed to assist financially with the purchase of specialized semiconductor fabrication and testing equipment, as well as to share certain costs associated with facilities enhancements and installation of equipment for manufacturing the Optical Interposer. Additionally, the collaboration includes a wafer purchase agreement for the manufacturing of prototype, initial production and volume production wafers.

POET’s Chief Executive Officer, Dr. Suresh Venkatesan, commented, “Following several months of preliminary collaborative work together, this agreement with SilTerra represents a significant milestone toward our goal of commercializing POET’s Optical Interposer Platform. The combined resources and investments of the two companies enables us to establish a unique manufacturing process as well as a reliable supply of wafers for our Optical Interposer. SilTerra offers POET a truly unique combination of advanced 90 nanometer lithography, cost-effective 8″ silicon processing copper metallization and MEMS capabilities, all of which are needed for our Optical Interposer. As a result of this partnership, POET has now secured a key element in the commercialization process allowing us to establish more engagements with prospective customers.”

Firdaus Abdullah, SilTerra’s Chief Executive Officer stated, “SilTerra is delighted to be working with POET in what we regard as a key strategic engagement to address the increasing need for cost-effective solutions for Data Center Interconnects through the innovative use of silicon in photonics.  POET’s Optical Interposer is a major advance over other approaches to optical interconnects and facilitates the co-packaging of electronics and photonics devices in a single Multi-Chip-Module (MCM). POET’s “Photonics-in-a-package” solution has the potential to address even larger markets in the future for the integration and co-optimization of ASIC’s and DSP’s with photonics at the interposer and chip level.  We at SilTerra look forward to a long and prosperous relationship between our two companies and our teams.”

The Master Collaboration Agreement between POET Technologies and SilTerra Malaysia Sdn Bhd was signed on April 6, 2018 and includes provisions for multiple co-development projects, consignment by POET of newly purchased equipment to be installed in SilTerra’s Malaysian foundry, various support services to be provided by SilTerra and the purchase of wafers containing Optical Interposer devices from SilTerra over an initial three-year term.

The GaN power business was worth about US$12 million in 2016, but at Yole, analysts project that the market will reach US$460 million by 2022, with an impressive 79% CAGR. Amongst the numerous applications, the market research company mentions Lidar, wireless power and envelope tracking. They are high-end low/medium voltage applications. Today GaN technology is the only existing solution to meet their specific requirements.

“The GaN power market remains small compared to the US$30 billion silicon power semiconductor market,” said Dr. Hong Lin, Technology & Market Analyst at Yole Développement (Yole). “However, it has an enormous potential in the short term due to its suitability for high performance and high frequency solutions.”

Although today only a few players are showing commercial GaN activities, many firms have GaN activities. Therefore, the power GaN supply chain prepares for production. During the 2016-2017 period, Yole’s analysts identified lot of investments that are clearly supporting development and implementation of GaN devices.

Yole differentiates GaN power supply chain into two main models: IDM and foundry. Both models will co-exist while there are different needs on the market, for example in consumer and industrial applications, explain Yole’s analysts in the Power GaN report (1).

GaN manufacturers continue developing new products and provide samples to costumers, as is the case with EPC and its wireless charging line. Indeed EPC is still the current market leader today. Other players including GaN systems sell also low voltage GaN transistors.

System Plus Consulting, part of Yole Group of Companies, reveals a detailed comparison of GaN-on-Silicon transistors in its new report, GaN-on-Silicon Transistor Comparison. The company analyzes the existing GaN-on-Silicon offers. This overview is the state of the art of GaN-on-Silicon HEMT. Indeed it highlights the differences between the design and manufacturing processes, the impacts at epitaxy, device and packaging level and related production costs. Devices analyzed by System Plus Consulting have been developed by the leading companies: EPC, Texas Instruments, Panasonic, GaN Systems and Transphorm.

“The current GaN device market is mainly dominated by devices <200V. 600V devices are expected to take off and keep growing. But the <200V market share will increase again when GaN begins to replace MOSFETs in different applications and enables new applications,” comments Dr. Elena Barbarini, Project Manager, Power Electronics and Compound Semiconductors at System Plus Consulting. And she adds: “GaN-on-Silicon has been a promising solution since the very beginning as its potential of CMOS compatibility and reduced cost”.

Both companies Yole and System Plus Consulting will attend a selection of key conferences during the next months.

At CS International, Dr. Hong Lin will present the latest results focused on the GaN industry. She will describe the GaN-on-Silicon landscape including power electronics, RF and lighting market segments. “GaN on Si Market and industry development” presentation will take place on April 10 at 3:35 PM. During the conference, Yole also proposes another presentation focused on the microLED technologies.

By Jamie Girard, Sr. Director, Public Policy, SEMI

Although many months past due, Congress on March 23 finalized the federal spending for the remainder of fiscal year (FY) 2018, only hours before a what would have been the third government shutdown of the year. Congressional spending has been allocated in fits and starts since the end of FY 2017 last September, with patchwork deals keeping things running amid pervasive uncertainty. While this clearly isn’t an ideal way to fund the federal government, the end result will make many in the business of research and development pleased with the addition of more resources for science and innovation.

There was grave concern over the future of federal spending with the release of the president’s FY 2018 budget, which would have cut the National Science Foundation (NSF) budget by 11 percent and National Institutes of Standards & Technology (NIST) spending by 30 percent. Relief came with early drafts from Congress that whittled those cuts down to between 2-9 percent. But the real boost was a February bipartisan Congressional agreement that lifted self-imposed spending caps and introduced a generous dose of non-defense discretionary spending, increasing NSF spending 3.9 percent over the previous year and the NIST budget an astounding 25.9 percent over FY 2017 levels.

SEMI applauds this much-needed support for basic research and development (R&D) at these agencies after their budgets were cut or flat-funded for multiple cycles. It is well understood that federal R&D funding is critical to U.S. competitiveness and future economic prosperity. With the stakes that high, full funding of R&D programs at the NSF and NIST should be a bipartisan national priority backed by a strong and united community of stakeholders and advocates in the business, professional, research, and education communities.

With the work for FY 2018 completed, Congress will now turn to FY 2019 spending – already behind schedule due to the belated completion of the previous year’s budget. With 2018 an election year, Congress will likely begin work on the FY 2019 budget in short order, but probably won’t complete its work prior to the November elections.  SEMI will continue to work with lawmakers to support the R&D budgets at the agencies and their important basic science research. If you’d like to know how you can be more involved with SEMI’s public policy work, please contact Jamie Girard, Sr. Director, Public Policy at [email protected].

A further step has been taken along the road to manufacturing solar cells from lead-free perovskites. High quality films based on double perovskites, which show promising photovoltaic properties, have been developed in collaboration between Linköping University, Sweden, and Nanyang Technological University in Singapore.

The lead-free double perovskite solar cells (yellow, in the front) compared with the lead-based device (dark, in the background). The next step is tune the color of the double perovskites into dark, so that they can absorb more light for efficient solar cells. Credit: Thor Balkhed

The lead-free double perovskite solar cells (yellow, in the front) compared with the lead-based device (dark, in the background). The next step is tune the color of the double perovskites into dark, so that they can absorb more light for efficient solar cells. Credit: Thor Balkhed

Research groups around the world have recognised the potential of perovskites as one of the most promising materials for the development of cheap, environmentally friendly and efficient solar cells. In just a few years, the power conversion efficiency has increased from a few percent to over 22%. The perovskites currently available for use in solar cells, however, contain lead, and Feng Gao, senior lecturer at LiU, was appointed in the autumn of 2017 as Wallenberg Academy Fellow to develop lead-free double perovskites, in which a monovalent metal and a trivalent metal replace the divalent lead.

In the laboratory at the Division of Biomolecular and Organic Electronics, LiU, postdoc researchers Weihua Ning and Feng Wang have successfully manufactured single-layer thin films of densely packed crystals of double perovskites. The films are of extremely high quality and can be used as the active layer in solar cells, in which sunlight is absorbed and charge carriers created.

“Our colleagues at Nanyang Technological University in Singapore have shown that the charge carriers demonstrate long diffusion lengths in the material, which is necessary if the material is to be appropriate for application in solar cells,” says Feng Gao.

The power conversion efficiency of the solar cells is still low – only around 1% of the energy in sunlight is converted to electricity – but neither Feng Gao or Weihua Ning are worried.

“No, we have taken the first major step and developed a method to manufacture the active layer. We have several good ideas of how to proceed to increase the efficiency in the near future,” says Feng Gao.

Weihua Ning nods in agreement.

Researchers have calculated that over 4,000 different combinations of materials can form double perovskites. They will also use theoretical calculations to identify the combinations that are most suitable for use in solar cells.

This breakthrough for research in double perovskites is also a result of the joint PhD programme in Materials- and nanoscience/technology at Linköping University and Nanyang Technological University.

“This publication is a spin-off of the discussions in relation to the joint PhD programme between NTU-LiU. Two PhD students, one on each side, have been recruited to work on this project. This is an excellent start for the program.” says Professor Tze Chien Sum from NTU.

“We complement each other very well, the group led by Professor Sum in NTU are experts in photophysics and we are experts in materials science and device physics,” says Feng Gao.

Tre results is published in the prestigious scientific journal Advanced Materials.