Category Archives: Device Architecture

ON Semiconductor (Nasdaq: ON) today announced it has recognized 20 companies with supplier excellence awards. Selected from among the company’s extensive list of preferred global suppliers, the 2017 award winners represent partners who have demonstrated a deep commitment to ensuring high quality and supply continuity in an evolving semiconductor market.

elected from more than 3,000 active production suppliers, the finalists gathered for a two-day awards event and executive conference in Hong Kong, China, with the focus of anticipating the future of semiconductor growth and accelerating customer needs.

“As a top 20 global semiconductor design and manufacturing company, ON Semiconductor creates innovative semiconductor and general electronic component solutions to solve our customers’ design challenges and reduce their time to market,” said Jeffrey Wincel, vice president and chief procurement officer at ON Semiconductor. “All the suppliers recognized today demonstrated a similar commitment to collaboration and partnership. These strong relationships are key in delivering on our business strategy, including the areas of product innovation, customer satisfaction and growth.”

Full list of award winners:

Front End (FE) Direct Material Supplier: Konfoong Materials International Company, LTD.
Back End (BE) Direct Material Supplier: Chang Wah Technology Co., Ltd.
FE Site Supplier: Plansee SE
BE Site Supplier: KETECA Singapore (Pte) Ltd
BE External Manufacturing: King Yuan Electronics Co. Ltd.
FE External Manufacturing: JiangYin ChangDian Advanced Packaging Co., LTD
Corporate Services Supplier: DHL Supply Chain
Technology Leader Award: Mentor Graphics
BE Subcon Quality Award: GEM Services, Inc.
BE Perfect Quality Award: Indium Corporation
BE Perfect Quality Award: Henkel
FE Perfect Quality Platinum Award: Shin-Etsu Handotai Co., Ltd
FE Perfect Quality Platinum Award: Brewer Science, Inc.
FE Perfect Quality Platinum Award: JSR Micro, Inc.
FE Perfect Quality Platinum Award: JX Nippon Mining & Metals
FE Perfect Quality Gold Award: Cabot Microelectronics Corporation
FE Perfect Quality Gold Award: Grikin Advanced Materials Co., Ltd.
FE Perfect Quality Award: Tanaka Kikinzoku Kogyo K.K.
FE Perfect Quality Award: Tosoh SMD, Inc.
Pinnacle Award: Global Wafers

 

Following three years of extensive research, Hebrew University of Jerusalem (HU) physicist Dr. Uriel Levy and his team have created technology that will enable our computers–and all optic communication devices–to run 100 times faster through terahertz microchips.

Until now, two major challenges stood in the way of creating the terahertz microchip: overheating and scalability.

However, in a paper published this week in Laser and Photonics Review, Dr. Levy, head of HU’s Nano-Opto Group and HU emeritus professor Joseph Shappir have shown proof of concept for an optic technology that integrates the speed of optic (light) communications with the reliability–and manufacturing scalability–of electronics.

Optic communications encompass all technologies that use light and transmit through fiber optic cables, such as the internet, email, text messages, phone calls, the cloud and data centers, among others. Optic communications are super fast but in microchips they become unreliable and difficult to replicate in large quanitites.

Now, by using a Metal-Oxide-Nitride-Oxide-Silicon (MONOS) structure, Levy and his team have come up with a new integrated circuit that uses flash memory technology–the kind used in flash drives and discs-on-key–in microchips. If successful, this technology will enable standard 8-16 gigahertz computers to run 100 times faster and will bring all optic devices closer to the holy grail of communications: the terahertz chip.

As Dr. Uriel Levy shared, “this discovery could help fill the ‘THz gap’ and create new and more powerful wireless devices that could transmit data at significantly higher speeds than currently possible. In the world of hi-tech advances, this is game-changing technology,”

Meir Grajower, the leading HU PhD student on the project, added, “It will now be possible to manufacture any optical device with the precision and cost-effectiveness of flash technology”.

Coming soon to a chip near you…

Thousands of miles of fiber-optic cables crisscross the globe and package everything from financial data to cat videos into light. But when the signal arrives at your local data center, it runs into a silicon bottleneck. Instead of light, computers run on electrons moving through silicon-based chips — which, despite huge advances, are still less efficient than photonics.

To break through this bottleneck, researchers are trying to integrate photonics into silicon devices. They’ve been developing lasers — a crucial component of photonic circuits — that work seamlessly on silicon. In a paper appearing this week in APL Photonics, from AIP Publishing, researchers from the University of California, Santa Barbara write that the future of silicon-based lasers may be in tiny, atomlike structures called quantum dots.

Such lasers could save a lot of energy. Replacing the electronic components that connect devices with photonic components could cut energy use by 20 to 75 percent, Justin Norman, a graduate student at UC Santa Barbara, said. “It’s a substantial cut to global energy consumption just by having a way to integrate lasers and photonic circuits with silicon.”

Silicon, however, does not have the right properties for lasers. Researchers have instead turned to a class of materials from Groups III and V of the periodic table because these materials can be integrated with silicon.

Initially, the researchers struggled to find a functional integration method, but ultimately ended up using quantum dots because they can be grown directly on silicon, Norman said. Quantum dots are semiconductor particles only a few nanometers wide — small enough that they behave like individual atoms. When driven with electrical current, electrons and positively charged holes become confined in the dots and recombine to emit light — a property that can be exploited to make lasers.

The researchers made their III-V quantum-dot lasers using a technique called molecular beam epitaxy. They deposit the III-V material onto the silicon substrate, and its atoms self-assemble into a crystalline structure. But the crystal structure of silicon differs from III-V materials, leading to defects that allow electrons and holes to escape, degrading performance. Fortunately, because quantum dots are packed together at high densities — more than 50 billion dots per square centimeter — they capture electrons and holes before the particles are lost.

These lasers have many other advantages, Norman said. For example, quantum dots are more stable in photonic circuits because they have localized atomlike energy states. They can also run on less power because they don’t need as much electric current. Moreover, they can operate at higher temperatures and be scaled down to smaller sizes.

In just the last year, researchers have made considerable progress thanks to advances in material growth, Norman said. Now, the lasers operate at 35 degrees Celsius without much degradation and the researchers report that the lifetime could be up to 10 million hours.

They are now testing lasers that can operate at 60 to 80 degrees Celsius, the more typical temperature range of a data center or supercomputer. They’re also working on designing epitaxial waveguides and other photonic components, Norman said. “Suddenly,” he said, “we’ve made so much progress that things are looking a little more near term.”

Xcerra today announced that it has entered into a preferred supplier agreement with Elmos, a supplier of semiconductor and sensor devices to the automotive industry. Under the terms of the multiyear agreement Xcerra will be the exclusive supplier of semiconductor testers to Elmos, except in the rare case the test requirements cannot be supported by Xcerra.

Guido Meyer chief operating officer of Elmos, commented, “We have a strong focus on achieving the highest quality and production efficiency. Xcerra has consistently proven their ability to deliver to our requirements. With this agreement we further strengthen the relationship between the two companies and we are committing our test engineering resources to focus on Xcerra testers.”

David Tacelli, president and chief executive officer of Xcerra, commented, “Our passion is to help our customers succeed in the market place. Multiyear preferred supplier agreements like the one we have signed with Elmos serve as recognition that our focus on delivering the highest efficiency of test solutions are having a positive impact on our customers’ success. We look forward to playing a role in supporting Elmos’s growth.”

BY GUIDO GROESENEKEN, imec fellow

To be able to guarantee the reliability of transistors, we have been conducting research for some years now at imec to see what happens when transistors operate properly and when they fail. We’ve been doing this in terms of circuits, devices and materials – and sometimes right down to the level of atoms. The insights that we gather from this work help us to provide the right feedback to the process technol- ogists, who in turn are able to make the transistors more reliable. It is particularly interesting to note that in recent years the knowledge we have gained about these failure mechanisms can also be applied to other areas. These insights no longer only serve to solve problems, but are the basis for innovative and surprising solutions in very diverse domains.
Last year, imec spent a lot of time working on self- learning chips, data security codes, FinFET biosensors and computer systems that can correct themselves. These are innovations that draw on the knowledge present in imec’s reliability group.

Self-learning chips

For example, take the self-learning or neuromorphic chip that gave imec such extensive coverage in the media in 2017. The development of this chip is based, among other things, on our knowledge of “resistive RAM” or RRAM memories, which use the breakdown of an oxide to switch a memory bit on or off (0 or 1). This oxide breakdown – which was previously (and still is) a reliability problem – occurs because a conductive path is created through the oxide, known as a filament. However, the work conducted by imec’s reliability group has demonstrated that not only can you create a filament or make it disappear, but that there are intermediate levels as well, which means that the strength of the filament can be controlled. And that is precisely what happens in our brains: the connec- tions between neurons can become stronger or weaker according to the occurrence they are processing or the learning process they use, etc. This means that these RRAM filaments can be used in chips that work like our brains. It was this insight that provided us with the foundation for the development of imec’s neuromorphic chip, which – as has been demonstrated – can even compose music.

Data security

Since recently we are also working closely with COSIC, an imec research group at KU Leuven that specializes in computer security and cryptography. Also here we can draw on our knowledge of transistor breakdown mechanisms. These can be used to create and read out a fingerprint that is unique for each chip and that cannot be predicted, hence the name ‘physically unclonable functions’ (or PUFs). This unique fingerprint makes it possible to ascertain the identity of chips in data exchanges and thus to prevent hacking by means of rogue chips.

The phenomenon of ‘Random Telegraph Noise’, which has long been known in the area of transistor reliability, could also be used as a security fingerprint. Random telegraph noise is a name for sudden jumps in voltage or current levels as the result of the random trapping of charges in traps within the gate insulation of a transistor. This phenomenon is unpredictable and random, and hence it could also be perfectly usable as PUF. What was once a problem for us – the breakdown of oxides or the existence of random telegraph noise – is now at the base of major new solutions for computer security.

Biosensors

A third example of discipline-overlapping innovation brings us to the world of life sciences. FinFET transistors are essential for the current and future generations of computer chips. As a result of the research carried out in our group, we have now found out a great deal about the way the work, including their failure mechanisms, etc. So much so that we can now explore the possibility to use them as biosensors. What happens is that biomolecules have a certain charge and when that charge comes into the vicinity of a FinFET, the current in the FinFET will be influ- enced. As a result, there is the potential that the presence of a single biomolecule can be detected by such a FinFET.

Self-healing chips

And, finally, we are also working with system architects to produce reliable chips, even with transistors that are no longer reliable. Extremely small transistors with dimen- sions smaller than 5 nanometers can be very variable and the way they behave is unpredictable. For that reason we are working with system architects on solutions such as self- healing chips, based among other things on the existing models of the failure mechanisms that we provide them with. These self-healing chips will contain monitors that detect local errors. A smart controller then interprets this information and decides how to solve the problem, after which actuators are directed by the controller to carry out the task required.

What about scaling?

Numerous methods are currently being investigated to ensure that transistors can still be miniaturized and improved for as long as possible, as propounded in Moore’s Law. To do so, the classic transistor architecture has already been replaced by a FinFET architecture and in the future this will evolve even to nanosheets or nanowires. Materials other than silicon, with greater mobility, are also being looked at, such as III-V materials (germanium for pMOS and InGaAs for nMOS).

In the choice made for these future architecture, it is extremely important to also look right from the start to the failure mechanisms and reliability of the new solutions.

As an example, last year, our reliability team focused extensively on III-V transistors. Although these transistors score well in terms of mobility, their stability is still one of the main challenges remaining before we are able to take the next step and start manufacturing. The insulation layers in III-V transistors contain a lot of traps that cause this insta- bility in transistor characteristics. Understanding this phenomenon is essential if we are to find a solution for it. So, a breakthrough in this area is needed urgently and our results, which were published in a recent IEDM paper, are certainly a step in the right direction. In the invited paper by Jacopo Franco these instabilities are first analyzed in detail. Then, based on this analysis, practical guidelines are given for the development of III-V gate stacks that offer sufficient reliability.

It’s very difficult to look ahead even further into the future, because as the end of Moore’s Law approaches, increasing numbers of different technologies and concepts are already on the radar (quantum computers, 2D materials, neuro- morphic computers, spinwave logic, etc.). However, none of these concepts has yet made a real breakthrough. But in my view 2017 was the year in which the industry began to take a strong interest in quantum computers, with major investments from important players such as Google and Intel. Imec also plans to play a major role in this field, with the launch of a new program on quantum computing, gathering the extensive expertise available. In the past, quantum computing has been considered more as a purely academic field of research – something of value for physi- cists at universities, but not for engineers and companies. So perhaps the breakthrough of industrial quantum computing will be the next milestone in the history of electronics. Or perhaps this milestone will come from a totally unexpected angle – by combining knowledge and people from entirely different disciplines, creating totally new ideas and concepts. Only the future will tell us!

Data is only as good as humans’ ability to analyze and make use of it.

In materials research, the ability to analyze massive amounts of data–often generated at the nanoscale–in order to compare materials’ properties is key to discovery and to achieving industrial use. Jeffrey M. Rickman, a professor of materials science and physics at Lehigh University, likens this process to candy manufacturing:

“If you are looking to create a candy that has, say, the ideal level of sweetness, you have to be able to compare different potential ingredients and their impact on sweetness in order to make the ideal final candy,” says Rickman.

For several decades, nanomaterials–matter that is so small it is measured in nanometers (one nanometer = one-billionth of a meter) and can be manipulated at the atomic scale–have outperformed conventional materials in strength, conductivity and other key attributes. One obstacle to scaling up production is the fact that scientists lack the tools to fully make use of data–often in the terabytes, or trillions of bytes–to help them characterize the materials–a necessary step toward achieving “the ideal final candy.”

What if such data could be easily accessed and manipulated by scientists in order to find real-time answers to research questions?

The promise of materials like DNA-wrapped single-walled carbon nanotubes could be realized. Carbon nanotubes are a tube-shaped material which can measure as small as one-billionth of a meter, or about 10,000 times smaller than a human hair. This material could revolutionize drug delivery and medical sensing with its unique ability to penetrate living cells.

A new paper takes a step toward realizing the promise of such materials. Authored by Rickman, the article describes a new way to map material properties relationships that are highly multidimensional in nature. Rickman employs methods of data analytics in combination with a visualization strategy called parallel coordinates to better represent multidimensional materials data and to extract useful relationships among properties. The article, “Data analytics and parallel-coordinate materials property charts,” has been published in npj Computational Materials, a Nature Research journal.

“In the paper,” says Rickman, “we illustrate the utility of this approach by providing a quantitative way to compare metallic and ceramic properties–though the approach could be applied to any materials you want to compare.”

It is the first paper to come out of Lehigh’s Nano/Human Interface Presidential Engineering Research Initiative, a multidisciplinary research initiative that proposes to develop a human-machine interface to improve the ability of scientists to visualize and interpret the vast amounts of data that are generated by scientific research. It was kickstarted by a $3-million institutional investment announced last year.

The leader of the initiative is Martin P. Harmer, professor of materials science and engineering. In addition to Rickman, other senior faculty members include Anand Jagota, department chair of bioengineering; Daniel P. Lopresti, department chair of computer science and engineering and director of Lehigh’s Data X Initiative; and Catherine M. Arrington, associate professor of psychology.

“Several research universities are making major investments in big data,” says Rickman. “Our initiative brings in a relatively new aspect: the human element.”

According to Arrington, the Nano/Human Interface initiative emphasizes the human because the successful development of new tools for data visualization and manipulation must necessarily include a consideration of the cognitive strengths and limitations of the scientist.

“The behavioral and cognitive science aspects of the Nano/Human Interface initiative are twofold,” says Arrington. “First, a human-factors research model allows for analysis of the current work environment and clear recommendations to the team for the development of new tools for scientific inquiry. Second, a cognitive psychology approach is needed to conduct basic science research on the mental representations and operations that may be uniquely challenged in the investigation of nanomaterials.”

Rickman’s proposed method uses parallel coordinates, which is a method of visualizing data that makes it possible to spot outliers or patterns based on related metric factors. Parallel coordinates charts can help tease out those patterns.

The challenge, says Rickman, lies in interpreting what you see.

“If plotting points in two dimensions using X and Y axes, you might see clusters of points and that would tell you something or provide a clue that the materials might share some attributes,” he explains. “But, what if the clusters are in 100 dimensions?”

According to Rickman, there are tools that can help cut down on numbers of dimensions and eliminate non-relevant dimensions to help one better identify these patterns. In this work, he applies such tools to materials with success.

“The different dimensions or axes describe different aspects of the materials, such as compressibility and melting point,” he says.

The charts described in the paper simplify the description of high-dimensional geometry, enable dimensional reduction and the identification of significant property correlations and underline distinctions among different materials classes.

From the paper: “In this work, we illustrated the utility of combining the methods of data analytics with a parallel coordinates representation to construct and interpret multidimensional materials property charts. This construction, along with associated materials analytics, permits the identification of important property correlations, quantifies the role of property clustering, highlights the efficacy of dimensional reduction strategies, provides a framework for the visualization of materials class envelopes and facilitates materials selection by displaying multidimensional property constraints. Given these capabilities, this approach constitutes a powerful tool for exploring complex property interrelationships that can guide materials selection.”

Returning to the candy manufacturing metaphor, Rickman says: “We are looking for the best methods of putting the candies together to make what we want and this method may be one way of doing that.”

New frontier, new approaches

Creating a roadmap to finding the best methods is the aim of a 2½-day, international workshop called “Workshop on the Convergence of Materials Research and Multi-Sensory Data Science” that is being hosted by Lehigh University in partnership with The Ohio State University.

The workshop–which will take place at Bear Creek Mountain Resort in Macungie, PA from June 11-13, 2018–will bring together scientists from allied disciplines in the basic and social sciences and engineering to address many issues involved in multi-sensory data science as applied to problems in materials research.

“We hope that one outcome of the workshop will be the forging of ongoing partnerships to help develop a roadmap to establishing a common language and framework for continued dialogue to move this effort of promoting multi-sensory data science forward,” says Rickman, who is Principal Investigator on an National Science Foundation (NSF) grant, awarded by the Division of the Materials Research in support of the workshop.

Co-Principal Investigator, Nancy Carlisle, assistant professor in Lehigh’s Department of Psychology, says the conference will bring together complementary areas of expertise to allow for new perspectives and ways forward.

“When humans are processing data, it’s important to recognize limitations in the humans as well as the data,” says Carlisle. “Gathering information from cognitive science can help refine the ways that we present data to humans and help them form better representations of the information contained in the data. Cognitive scientists are trained to understand the limits of human mental processing- it’s what we do! Taking into account these limitations when devising new ways to present data is critical to success.”

Adds Rickman: “We are at a new frontier in materials research, which calls for new approaches and partners to chart the way forward.”

The Semiconductor Industry Association (SIA) today released the following statement from President & CEO John Neuffer in response to the Section 301 action taken by the Trump Administration to address China’s trade practices.

“The U.S. semiconductor industry shares the Trump Administration’s concerns regarding unfair and discriminatory trade practices that put at risk American intellectual property in China.

“We are reviewing the Administration’s Section 301 findings and proposed actions, and encourage an outcome that protects U.S. intellectual property in a manner that avoids a costly trade conflict. We welcome the opportunity to provide input on proposed tariffs, and hope to work with the Administration to avoid tariffs that would harm competitive U.S. industries and their consumers.

“Intellectual property is the lifeblood of the semiconductor industry. Semiconductors are America’s fourth-largest export and are fundamental to the strength of our economy. U.S. semiconductor companies invest nearly one-fifth of their revenue in research and development to stay at the forefront of innovation. They should be able to compete in foreign markets without putting their critical IP at risk.

“At the same time, we welcome China’s participation in the global semiconductor value chain as long as it conforms with its international obligations and is consistent with market-based principles. In the end, strong protections for intellectual property serve the long-term interests of both the United States and China.”

North America-based manufacturers of semiconductor equipment posted $2.41 billion in billings worldwide in February 2018 (three-month average basis), according to the February Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.  The billings figure is 1.7 percent higher than the final January 2018 level of $2.37 billion, and is 22.2 percent higher than the February 2017 billings level of $1.97 billion.

“February billings remain at a level indicating another positive year for semiconductor equipment spending,” said Ajit Manocha, president and CEO of SEMI. “We expect 2018 to mark the fourth consecutive year of spending growth, which last occurred in the 1990s.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
September 2017
$2,054.8
37.6%
October 2017
$2,019.3
23.9%
November 2017
$2,052.3
27.2%
December 2017
$2,398.4
28.3%
January 2018 (final)
$2,370.1
27.5%
February 2018 (prelim)
$2,411.4
22.2%

Source: SEMI (www.semi.org), March 2018

Research included in the March Update to the 2018 edition of IC Insights’ McClean Report shows that fabless IC suppliers accounted for 27% of the world’s IC sales in 2017—an increase from 18% ten years earlier in 2007.  As the name implies, fabless IC companies do not operate an IC fabrication facility of their own.

Figure 1 shows the 2017 fabless company share of IC sales by company headquarters location.  At 53%, U.S. companies accounted for the greatest share of fabless IC sales last year, although this share was down from 69% in 2010 (due in part to the acquisition of U.S.-based Broadcom by Singapore-based Avago). Broadcom Limited currently describes itself as a “co-headquartered” company with its headquarters in San Jose, California and Singapore, but it is in the process of establishing its headquarters entirely in the U.S. Once this takes place, the U.S. share of the fabless companies IC sales will again be about 69%.

Figure 1

Figure 1

Taiwan captured 16% share of total fabless company IC sales in 2017, about the same percentage that it held in 2010.  MediaTek, Novatek, and Realtek each had more than $1.0 billion in IC sales last year and each was ranked among the top-20 largest fabless IC companies.

China is playing a bigger role in the fabless IC market.  Since 2010, the largest fabless IC marketshare increase has come from the Chinese suppliers, which captured 5% share in 2010 but represented 11% of total fabless IC sales in 2017.  Figure 2 shows that 10 Chinese fabless companies were included in the top-50 fabless IC supplier list in 2017 compared to only one company in 2009. Unigroup was the largest Chinese fabless IC supplier (and ninth-largest global fabless supplier) in 2017 with sales of $2.1 billion. It is worth noting that when excluding the internal transfers of HiSilicon (over 90% of its sales go to its parent company Huawei), ZTE, and Datang, the Chinese share of the fabless market drops to about 6%.

Figure 2

Figure 2

European companies held only 2% of the fabless IC company marketshare in 2017 as compared to 4% in 2010. The loss of share was due to the acquisition of U.K.-based CSR, the second-largest European fabless IC supplier, by U.S.-based Qualcomm in 1Q15 and the purchase of Germany-based Lantiq, the third-largest European fabless IC supplier, by Intel in 2Q15.  These acquisitions left U.K.-based Dialog ($1.4 billion in sales in 2017) and Norway-based Nordic ($236 million in sales in 2017) as the only two European-based fabless IC suppliers to make the list of top-50 fabless IC suppliers last year.

The fabless IC business model is not so prominent in Japan or in South Korea.  Megachips, which saw its 2017 sales jump by 40% to $640 million, was the largest Japan-based fabless IC supplier.  The lone South Korean company among the top-50 largest fabless suppliers was Silicon Works, which had a 15% increase in sales last year to $605 million.

Bringing together a technical program that encompasses ‘big integration’ of a number of critical industry trends – machine learning, IoT, artificial intelligence, wearable/implantable biomedical applications, big data, and cloud computing – the 2018 Symposia on VLSI Technology & Circuits will showcase a convergence of technologies needed for ‘smart living.’ As the microelectronics industry’s premiere international conference covering technology, circuits, and systems, the Symposia continues to define the evolution of innovations that will shape the future of our increasingly connected world.

The Symposia theme of “Technology, Circuits & Systems for Smart Living” connects the related plenary presentations, panel discussions, focus sessions, short courses, along with a new Friday Forum on machine learning to provide a unique synergy between advanced technology developments, innovative circuit design, and the applications that they enable – as part of our global society’s transition to a new frontier of smart, connected devices and systems that change the way humans interact with technology – and with each other.

“This year’s Technology program is focused on the critical building blocks needed to realize a truly integrated IoT,” said Mukesh Khare, Symposium on VLSI Technology general chair. “Advanced memory technologies for AI and machine learning, the next wave of advanced computing (supercomputing/cloud/neuromorphic), the cutting edge of CMOS scaling (beyond 5nm/nanowire devices), and the advanced low-power sensors needed to connect them all are just some of the highlights of the Technology program.”

“The Circuits program will examine how the next wave of computing systems need to be designed to realize the potential of AI, machine learning, SOC technology, wearable/implantable biomedical systems, and the IoT,” explained Gunther Lehmann, Symposium on VLSI Circuits general chair. “A demonstration session that showcases real-life applications is designed to enable conference participants to see these innovations first hand.”

The Symposia will also include a series of joint focus sessions that include invited and contributed papers on topics of mutual interest to both technology and circuit attendees. As part of the unique Symposia program, these joint Technology & Circuits focus sessions enable participants to engage in meaningful interaction with their colleagues in different disciplines. In addition, there will be a joint evening panel session by leading industry experts to address critical issues surrounding major industry developments.

Capping off the joint Symposia program will be a series of nine presentations comprising the Friday Forum on machine learning, a subject area that continues to evolve as an impactful driver of the integrated systems that are part of the Symposia’s “Smart Living” theme.

The annual Symposium on VLSI Technology & Circuits will be held at the Hilton Hawaiian Village in Honolulu, Hawaii from June 19-21, 2018, with Short Courses held on June 18 and a special Friday Forum dedicated to machine learning/AI topics on June 22. The two conferences have been held together since 1987, providing an opportunity for the world’s top device technologists, circuit and system designers to exchange leading edge research on microelectronics technology, with alternating venues between Hawaii and Japan. A single registration enables participants to attend both Symposia.

The Symposium on VLSI Technology is sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics, in cooperation with the IEEE Solid State Circuits Society.

The Symposium on VLSI Circuits is sponsored by the IEEE Solid State Circuits Society and the Japan Society of Applied Physics, in cooperation with the Institute of Electronics, Information and Communication Engineers.