Category Archives: Device Architecture

By Ando Yoichiro, SEMI Japan

In Tokyo, Shanghai, Moscow, London, Paris or New York – wherever you are in the world –Japanese vehicles passing by on the roadways are a common sight. Three big reasons are their high quality, reliability and engineering. But Japan’s automakers are also legendary for their industry breakthroughs. A few highlights:

  • In 1981, Honda introduced the first commercially available map-based car navigation system. The carmaker’s Electro Gyro-Cator used a gyroscope to detect rotation and other movements of the car.
  • In 1990, Mazda equipped its COSMO Eunos with the world’s first built-in GPS-navigation system.
  • In 1997, Toyota launched the world’s first mass-produced hybrid car — Prius.
  • In 1997, Toyota unveiled the world’s first production laser adaptive cruise control on its Celsior.
  • In 2009, Mitsubishi rolled out the world’s first mass-produced electric car – i-MiEV.

Off the roadways and often unheralded, it is supply chain companies including Japanese semiconductor makers that were a key engine of these innovations as they continue their rich history of driving automotive advances. Here’s a closer look at some of the key players and why they matter.

Who Makes Automotive Semiconductors?

Unlike other semiconductors, automotive chips are manufactured not only by integrated device manufacturers (IDMs) but also by captive fabs and automotive components makers such as Toyota and Denso.

Denso, headquartered in Aichi prefecture, started in 1949 as a spin-off of Toyota’s electric components unit. Since 2009, the company has been the world’s largest automotive components supplier. Because Denso’s chips are mostly consumed internally, the company’s manufacturing revenue is not publicly available, but analysts estimate Denso’s chip business exceeds 200 billion JPY or USD $1.9 billion.

Denso fab (source: Denso)

Denso fab (source: Denso)

Denso manufactures semiconductor components at two locations. Its Kota plant in Aichi prefecture manufactures power and logic chips, and the company’s Iwate (Iwate prefecture) facility, acquired from Fujitsu in 2012, produces semiconductor wafers and sensors.

Denso is developing SiC wafers for its power chips and plans to manufacture SiC inverters by 2020. Recently, the company announced joint research on Ga2O3 for power devices with FLOSFIA, a tech startup spun off from Kyoto University. In 2017, Denso established a semiconductor IP design company, NSITEXE, in Tokyo to design semiconductor IP cores – the semiconductor components that are key to autonomous driving.

Toyota has been manufacturing semiconductor chips at its Hirose Plant since 1989. The semiconductor fab design and manufacturing technologies originated at Toshiba and moved to Toyota under a technology transfer agreement signed in 1987. In the power semiconductor arena, Toyota is jointly developing SiC devices with Denso and Toyota Central Research and Development Labs.

Other car and component makers like Honda, Nissan, Hitachi Automotive Systems, Aishin Seiki and Calsonic Kansei are also developing and designing semiconductor chips.

Microcontroller Units                                     

Microcontrollers (MCUs) were first employed in automobiles in the late 1970s to electronically control engines for higher fuel efficiency. Today, up to 80 MCUs are typically used in a car for powertrain controls (engine, fuel management and fuel injection), body controls (seat, door, window, air conditioning and lighting), safety controls (brake, EPS, suspensions, air bags and anti-collision) and infotainment.

In December 2015, the microcontroller unit (MCU) supply chain experienced a major consolidation with the nearly $12 billion acquisition of Freescale Semiconductor by NXP Semiconductors, catapulting NXP to the top of the MCU market. NXP and Freescale were ranked second and third in global market share, after Renesas Electronics, at the time.

Renesas held 40 percent global market share before its Ibaraki fab suffered severe earthquake damage in 2011 and hemorrhaged share after the loss of production capacity.  Renasas continues to recapture market share at a rapid clip, with a growth rate of 5.2 percent and 24.6 percent, respectively, in the first two quarters of 2017, and claims it still leads the global MCU market for automotive applications with 30 percent share (source: Diamond Online, August 2017).

Renesas was established as a joint venture of Hitachi and Mitsubishi and later merged with NEC Electronics. Consequently, Resesas’s MCUs, designed with Hitachi’s SH MCU cores, recently began a gradual shift to Arm cores. Renasas MCUs designed at 40nm or less nodes have been manufactured at TSMC, a Taiwan foundry, since 2012.

Renesas’s microcontrollers in a car (source: EE News Europe Automotive)

Renesas’s microcontrollers in a car
(source: EE News Europe Automotive)

CMOS Image Sensors

CMOS image sensors serve as eyes of cars, performing camera functions on-chip. Today, automobiles typically are fitted with about 10 CMOS image sensors, a number forecast to grow to almost 20 by 2020 (source: Monoist, 2016). The sensor was originally used as a backup monitor but deployments grew with the advent of Advanced Driver-Assistance Systems (ADAS). The CMOS image sensor market is estimated to reach $2.3 billion USD by 2021, according to IC Insights. Sony is the global CMOS image sensor market leader, and ON Semiconductor and OmniVision Technology are big players in this growing segment.

In 2016, Denso started using Sony’s CMOS image sensors to detect pedestrians during night driving. Sony manufactures CMOS sensors at Kumamoto TEC and Nagasaki TEC on Kyusyu Island. In 2017, Sony acquired Toshiba’s Oita plant to increase the capacity to respond to the growing demand for backside illumination CMOS image sensors for higher resolution images at a low-light environments.

Sony’s 7.42 megapixel CMOS image sensor for automotive cameras (source: Sony Corporation)

Sony’s 7.42 megapixel CMOS image sensor for automotive cameras
(source: Sony Corporation)

Power Devices

Power semiconductors provide electrical control functions such as rectification, voltage regulation (boost/step-down), and DA/AD conversion. The automotive industry’s migration from fossil fuel vehicles to hybrid and electric vehicles is driving strong demand for power devices. The leading power device makers are competing to develop higher performance devices on new materials such as SiC and GaN.

For the past five years, the Japan government has funded SiC power device research and development (R&D) projects and, in 2016, the National Institute of Advanced Industrial Science and Technology (AIST) and Sumitomo Electric Industries built a 150mm SiC wafer line at AIST’s Super Clean Room Facility in Tsukuba, Ibaraki. The facility supports volume manufacturing, reliability testing and quality assurance.

Rohm is driving the Japan SiC power device industry. Rohm manufactures SiC power devices on 75mm, 100mm and 150mm wafers. In 2009, Rohm acquired a German SiC wafer maker, SiCrystal, which started supplying 150mm wafers to Rohm in 2013. Rohm also acquired Renesas Electronics’s Shiga plant (200mm line) in 2016 to manufacture SiC power and other discrete devices.

Fuji Electric manufactures various power products including SiC power devices. Fully 30 percent of its products ship to the automotive industry. In 2013, the company built a new SiC line in its Matsumoto plant that includes both wafer process and packaging facilities. Fuji Electric now develops high-performance SiC devices on the latest 150mm SiC wafer technology.

Toyota and Denso round out the Japan SiC power device industry. Denso markets its 150mm SiC technology under the “REVOSIC” brand. In 2013, Toyota built a SiC R&D facility at its Hirose plant for future SiC captive manufacturing.

SiC power semiconductors to improve vehicle’s fuel efficiency by 10 percent (target) (source: Toyota Motor Corp.)

SiC power semiconductors to improve vehicle’s fuel efficiency by 10 percent (target)
(source: Toyota Motor Corp.)

SEMICON will Update You on Automotive Semiconductor Market

Heavy investments in the development of autonomous vehicles and the continuing expansion of the electric car market promise to bolster the automotive semiconductor market in the coming years and beyond. In light of Japan’s leading automotive chip manufacturing industry, SEMICON Japan and all other SEMICON shows in 2018 will spotlight this important segment.

Originally published on the SEMI blog.

SEMICON West, the flagship U.S. event for connecting the electronics manufacturing supply chain, has opened registration for the July 10-12, 2018, exposition at the Moscone Center in San Francisco, California. Building on a year of record-breaking industry growth, SEMICON West 2018 will highlight the engines of future industry expansion including smart transportation, smart manufacturing, smart medtech, smart data, big data, artificial intelligence, blockchain and the Internet of Things (IoT). Click here to register.

Themed BEYOND SMART, SEMICON West 2018 sets it sights on the growing impact of cognitive learning technologies and other industry disruptors with programs and new Smart Pavilions including Smart Manufacturing and Smart Transportation to showcase interactive technologies for immersive, virtual experiences. Each Pavilion will feature a Meet the Experts Theater with an intimate setting for attendees to engage informally with industry thought leaders.

Smart Workforce Pavilion: Connecting Next-Generation Talent with the Microelectronics Industry

The SEMI Smart Workforce Pavilion at SEMICON West 2018 leverages the largest microelectronic manufacturing event in North America to draw the next generation of innovators. Reliant on a highly skilled workforce, the industry today is saddled with thousands of job openings and fierce competition for workers, bringing renewed focus to strengthening its talent pipeline. Educational and engaging, the Pavilion connects the microelectronics industry with college students and entry-level professionals interested in career opportunities.

In the Workforce Pavilion “Meet the Experts” Theater, industry engineers will share insights and inspiration about their personal working experiences and career advisors will offer best practices. Recruiters from top companies will be available for on-the-spot interviews, while career coaches offer mentoring, tips on cover letter and resume writing, job-search guidance, and more. Visitors will learn more about the industry’s vital role in technological innovation in today’s connected world.

This year, SEMI will also host High Tech U (HTU) in conjunction with the SEMICON West Smart Workforce Pavilion. The highly-interactive program supported by Advantest, Edwards, KLA-Tencor and TEL exposes high school students to STEM education pathways and stimulates excitement about careers in the industry.

Free registration with three-day access and shuttle service to SEMICON West are available to all college students. Students are encouraged to register for the mentor program, attend keynotes and tour the exposition hall to see everything the industry has to offer.  To learn more, visit Smart Workforce Pavilion and College Track to preview how students can enter to win a $500 hiring bonus!

Three Ways to Experience the Expo

Attendees can tailor their SEMICON West experience to meet their specific interests. The All-In pass covers every program and event, while the Thought-Leadership and Expo-Only packages offer scaled pricing and program options. Attendees can also purchase select events and programs à la carte, including exclusive IEEE-sponsored sessions, the SEMI Market Symposium, and the STEM Rocks After-hours Party, a fundraising event to support the SEMI Foundation.

CEA-Leti, a French technology research institute of the CEA and Inac, a joint fundamental research institute between the CEA and the University Grenoble Alpes, today announced a breakthrough towards large-scale fabrication of quantum bits, or qubits, the elementary bricks of future quantum processors. They demonstrated on a 300 mm pre-industrial platform a new level of isotopic purification in a film deposited by chemical vapor deposition (CVD). This enables creating qubits in thin layers of silicon using a very high purity silicon isotope, 28Si, which produces a crystalline quality comparable to thin films usually made of natural silicon.

“Using the isotope 28Si instead of natural silicon is crucial for the optimization of the fidelity of the silicon spin qubit,” said Marc Sanquer, a research director at Inac. “The fidelity of the spin qubit is limited to small values by the presence of nuclear spins in natural silicon. But spin qubit fidelity is greatly enhanced by using 28Si, which has zero nuclear spin. We expect to confirm this with qubits fabricated in a pre-industrial CMOS platform at CEA-Leti.” 

Qubits are the building blocks of quantum information. They can be made in a broad variety of material systems, but when it comes to the crucial issue of large-scale integration, the range of possible choices narrows significantly. Silicon spin qubits have a small size and are compatible with CMOS technology. They therefore present advantages for large-scale integration compared to other types of qubits.

Since 2012, when the first qubits that relied on electron spins were reported, the introduction of isotopically purified 28Si has led to significant enhancement of the spin coherence time. The longer spin coherence lasts, the better the fidelity of the quantum operations.

Quantum effects are essential to understanding how basic silicon micro-components work, but the most interesting quantum effects, such as superposition and entanglement, are not used in circuits. The CEA-Leti and Inac results showed that these effects can be implemented in CMOS transistors operated at low temperature.

CEA-Leti and Inac previously reported preliminary steps for demonstrating a qubit in a process utilizing a natural silicon-on-insulator (SOI) 300 mm CMOS platform1. The qubit is an electrically controlled spin carried by a single hole in a SOI transistor. In a paper published in npj Quantum Information2., CEA-Leti and Inac reported that an electron spin in a SOI transistor can also be manipulated by pure electrical signals, which enable fast and scalable spin qubits.

“To progress towards a practical and useful quantum processor, it is now essential to scale up the qubit,” said Louis Hutin, a research engineer in CEA-Leti’s Silicon Components Division. “This development will have to address variability, reproducibility and electrostatic control quality for elementary quantum bricks, as is done routinely for standard microprocessors.”

To help CEA-Leti and Inac leverage nuclear spin free silicon in the CMOS platform, a silicon precursor was supplied by Air Liquide, using an isotopically purified silane of very high isotopic purity with a 29Si isotope content of less than 0.00250 percent, prepared by the Institute of Chemistry of High-Purity Substances at the Russian Academy of Sciences. The 29Si isotope is present at 4.67 percent in natural silicon and is the only stable isotope of silicon that carries a nuclear spin limiting the qubit coherence time.

A secondary ion mass spectrometry (SIMS) analysis done on the CVD-grown layer using this purified silane precursor showed29Si concentration less than 0.006 percent, and 30Si less than 0.002 percent, while 28Si concentration was more than 99.992 percent. These unprecedented levels of isotopic purification for a CVD-grown epilayer on 300 mm substrates are associated with surfaces that are smooth at the atomic scale, as verified by atomic force microscopy (AFM), haze and X-ray reflectometry measurements.

Leveraging their scientific and technological expertise, and the specific opportunities associated with the 300 mm silicon platform on the Minatec campus, CEA-Leti and Inac will continue to contribute to the scientific, technological and industrial dynamic on quantum technologies, enhanced by the implementation of the EC’s FET Flagships initiative in this domain.

  1. “A CMOS silicon spin qubit”, arXiv:1605.07599 Nature Communications 7, Article number: 13575 (2016) doi:10.1038/ncomms13575
  1. “Electrically driven electron spin resonance mediated by spin-valley-orbit coupling in a silicon quantum dot”, Nature PJ Quantum Information (2018) 4:6; doi:10.1038/s41534-018-0059-1

Everspin Technologies, Inc. (NASDAQ: MRAM), a developer and manufacturer of discrete and embedded magnetoresistive random access memory (MRAM), today announced it has entered into a multi-year worldwide licensing agreement with Alps Electric Co., LTD (Alps), a manufacturer of 3D magnetic sensors. Under the agreement, Alps and Everspin will mutually grant licenses to magnetoresistive-based 3D sensor patent portfolios for magnetoresistive sensor products. The terms of the agreement include an up-front license fee to Everspin as well as future royalties. Specific financial terms of the agreement are not being disclosed.

With an extensive portfolio of over 500 worldwide patents and applications covering its magnetoresistive technology, this agreement expands Everspin’s existing group of memory and sensor licensees. Everspin was recognized by IEEE in its Patent Power 2017 report as having one of the world’s top 20 most valuable patent portfolios for semiconductor manufacturing.

Kevin Conley, President and CEO of Everspin, stated, “Everspin’s magnetoresistive patent portfolio is valuable to a number of significant market applications beyond our core focus in magnetoresistive memory. This agreement demonstrates that value as well as our ability to monetize these assets and generate an additional revenue stream for Everspin.”

An unexpected phenomenon known as zero field switching (ZFS) could lead to smaller, lower-power memory and computing devices than presently possible. The image shows a layering of platinum (Pt), tungsten (W), and a cobalt-iron-boron magnet (CoFeB) sandwiched at the ends by gold (Au) electrodes on a silicon (Si) surface. The gray arrows depict the overall direction of electric current injected into the structure at the back of the gold (Au) contact and coming out the front gold contact pad.

This is an illustration of an unexpected phenomenon known as zero field switching (ZFS) that could lead to smaller, lower-power memory and computing devices than presently possible. The image shows a layering of platinum (Pt), tungsten (W), and a cobalt-iron-boron magnet (CoFeB) sandwiched at the ends by gold (Au) electrodes on a silicon (Si) surface. The gray arrows depict the overall direction of electric current injected into the structure at the back of the gold (Au) contact and coming out the front gold contact pad. The CoFeB layer is a nanometer-thick magnet that stores a bit of data. A "1" corresponds to the CoFeB magnetization pointing up (up arrow), and a "0" represents the magnetization pointing down (down arrow). Credit: Gopman/NIST

This is an illustration of an unexpected phenomenon known as zero field switching (ZFS) that could lead to smaller, lower-power memory and computing devices than presently possible. The image shows a layering of platinum (Pt), tungsten (W), and a cobalt-iron-boron magnet (CoFeB) sandwiched at the ends by gold (Au) electrodes on a silicon (Si) surface. The gray arrows depict the overall direction of electric current injected into the structure at the back of the gold (Au) contact and coming out the front gold contact pad. The CoFeB layer is a nanometer-thick magnet that stores a bit of data. A “1” corresponds to the CoFeB magnetization pointing up (up arrow), and a “0” represents the magnetization pointing down (down arrow). Credit: Gopman/NIST

The CoFeB layer is a nanometer-thick magnet that stores a bit of data. A “1” corresponds to the CoFeB magnetization pointing up (up arrow), and a “0” represents the magnetization pointing down (down arrow). The “0” or “1” can be read both electrically and optically, as the magnetization changes the reflectivity of light shining on the material through another phenomenon known as the magneto-optical Kerr effect (MOKE).

In the device, electric current can flip the data state between 0 and 1. Previous devices of this type have also required a magnetic field or other more complex measures to change the material’s magnetization. Those earlier devices are not very useful for building stable, non-volatile memory devices.

A breakthrough occurred in a research collaboration between The Johns Hopkins University and NIST. The team discovered that they could flip the CoFeB magnetization in a stable fashion between the 0 and 1 states by sending only electric current through the Pt and W metal layers adjacent to the CoFeB nanomagnet. They did not need a magnetic field. This ZFS (zero-field switching) effect was a surprise and had not been theoretically predicted.

In their work, the researchers created a special kind of electric current known as a “spin” current. The electrons that carry electric current possess a property known as spin which can be imagined as a bar magnet pointing in a specific direction through the electron. Increasingly exploited in the emerging field known as “spintronics,” spin current is simply electric current in which the spins of the electrons are pointing in the same direction. As an electron moves through the material, the interaction between its spin and its motion (called a spin-orbit torque, SOT) creates a spin current where electrons with one spin state move perpendicular to the current in one direction and electrons with the opposite spin state move in the opposite direction. The resulting spins that have moved adjacent to the CoFeB magnetic layer exert a torque on that layer, causing its magnetization to be flipped. Without the spin current the CoFeB magnetization is stable against any fluctuations in current and temperature. This unexpected ZFS effect poses new questions to theorists about the underlying mechanism of the observed SOT-induced switching phenomenon.

Details of the spin-orbit torque are illustrated in the diagram. The purple arrows show the spins of the electrons in each layer. The blue curved arrow shows the direction in which spins of that type are being diverted. (For example, in the W layer, electrons with spin to the left in the x-y plane are diverted to move upward toward the CoFeB and the electron spins to the right are diverted to move down toward the Pt.) Note the electron spins in the Pt with spin to the right (in the x-y plane), however, are diverted to move upward toward the W and the electron spins with spin to the left are diverted to move downward toward the Si. This is opposite to the direction the electron spins in the W are moving, and this is due to differences in the SOT experienced by electrons moving through Pt and those moving through W. In fact, it is this difference in the way the electrons move through each of these two conductors that may be important to enabling the unusual ZFS effect.

The research team, including NIST scientists Daniel Gopman, Robert Shull, and NIST guest researcher Yury Kabanov, and The Johns Hopkins University researchers Qinli Ma, Yufan Li and Professor Chia-Ling Chien, report their findings today in Physical Review Letters.

Ongoing investigations by the researchers seek to identify other prospective materials that enable zero-field-switching of a single perpendicular nanomagnet, as well as determining how the ZFS behavior changes for nanomagnets possessing smaller lateral sizes and developing the theoretical foundation for this unexpected switching phenomenon.

The ConFab — an executive invitation-only conference now in its 14th year — brings together influential decision-makers from all parts of the semiconductor supply chain for three days of thought-provoking talks and panel discussions, networking events and select, pre-arranged breakout business meetings.

In the 2018 program, we will take a close look at the new applications driving the semiconductor industry, the technology that will be required at the device and process level to meet new demands, and the kind of strategic collaboration that will be required. It is this combination of business, technology and social interactions that make the conference so unique and so valuable. Browse this slideshow for a look at this year’s speakers, keynotes, panel discussions, and special guests.

Visit The ConFab’s website for a look at the full, three-day agenda for this year’s event.

KEYNOTE: How AI is Driving the New Semiconductor Era

Rama Divakaruni_June_2014presented by Rama Divakaruni, Advanced Process Technology Research Lead, IBM

The exciting results of AI have been fueled by the exponential growth in data, the widespread availability of increased compute power, and advances in algorithms. Continued progress in AI – now in its infancy – will require major innovation across the computing stack, dramatically affecting logic, memory, storage, and communication. Already the influence of AI is apparent at the system-level by trends such as heterogeneous processing with GPUs and accelerators, and memories with very high bandwidth connectivity to the processor. The next stages will involve elements which exploit characteristics that benefit AI workloads, such as reduced precision and in-memory computation. Further in time, analog devices that can combine memory and computation, and thus minimize the latency and energy expenditure of data movement, offer the promise of orders of magnitude power-performance improvements for AI workloads. Thus, the future of AI will depend instrumentally on advances in devices and packaging, which in turn will rely fundamentally on materials innovations.

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Synopsys, Inc. (Nasdaq: SNPS) today announced it is hosting an advanced-technology panel on “EUV, High-NA, Metallurgy and FinFET++ – Where We Go from Here for Next-Generation Design” at the Synopsys Users Group (SNUG®) Silicon Valley event on Thursday, March 22, at the Santa Clara Convention Center in Santa Clara, California.

The panel will bring together prominent industry leaders from ASML, Inc., Samsung Foundry, and Qualcomm, Inc. (representing the perspectives of manufacturing, foundry, and end-user design, respectively) to discuss the challenges, opportunities and technology roadmaps inherent in driving system-on-chip (SoC) solutions beyond the 5nm process node. EDA representatives from Synopsys will include Dr. Henry Sheng, group director of R&D in the Silicon Design Group, and Dr. Victor Moroz, Synopsys Fellow in the Silicon Engineering Group.

Since 1991, SNUG has represented a global design community focused on innovating from Silicon to Software. Today, as the electronics industry’s largest user conference, SNUG brings together nearly 10,000 Synopsys tool and technology users across North America, Europe, Asia, and Japan. In addition to peer-reviewed technical papers and insightful keynotes from industry leaders, the exclusive SNUG events provide a unique opportunity to connect with Synopsys executives, design ecosystem partners, and members of the local design community.

Synopsys, Inc. (Nasdaq: SNPS) today announced that Dr. John Rogers, principal engineer of imaging optics in the Optical Solutions Group at Synopsys, has been promoted to Fellow by SPIE, the international society for optics and photonics. Each year, SPIE recognizes distinguished individuals in the field of optics and optoelectronics through its Fellows program. The promotion recognizes Rogers’ technical achievements in optical design and engineering, as well as his extensive service and contributions to the optics community. Rogers will formally accept the honor at the SPIE Optics + Photonics Conference in San Diego, Calif. in August 2018.

Rogers is a recognized authority in the fields of optical design and aberration theory, particularly for optical systems with rotationally nonsymmetric and freeform elements. He was an early advocate of vector aberration theory, now known as nodal aberration theory. His 1986 paper “Practical Tilted Mirror Systems” showed for the first time that a tilted and/or decentered optical system could be arranged to have aberration patterns that mimic those of a rotationally symmetric system. He also has designed a wide range of significant and complex optical systems, including three-dimensional imaging for clinical dental applications, ophthalmic surgical systems, biocular and binocular systems, FLIR systems, and head-up and helmet-mounted displays.

Rogers has given extensive service to the optics community for educational activities and support for several technical societies. Currently, he is a reviewer for JOSA A, Optics Express and Optics Letters. In 2014 and 2017, he was co-chair for the International Optical Design Conference. In 2016, he was a guest speaker for the Optical Society of Southern California, and from 1992 to 1997, he was convener for the ISO TC172 SC1 WG2, which produced the ISO 10110 optical drawing standard. From 1984 to 1988, he was assistant professor at the Institute of Optics, University of Rochester.

Rogers has also given significant service to SPIE. He has served as a conference chair, committee member and contributor to many SPIE conferences. He is also a reviewer for Optical Engineering and has served as a guest editor as well. His talks at various SPIE conferences have often attracted large audiences.

He has authored or co-authored 37 journal and conference papers, has contributed articles for two books and holds 13 U.S. patents. He received a Ph.D. in Optics from University of Arizona, an M.S. in Optics from University of Arizona and a B.S. in Mathematics from Virginia Polytechnic Institute.

“John’s pioneering contributions to design strategies for tilted, decentered and freeform surfaces has significantly advanced the field of optical design and has helped to drive the development of advanced design features in the optical software that Synopsys supplies,” said George Bayz, vice president of Synopsys’ Optical Solutions Group. “We congratulate John on his many achievements and on his election to SPIE Fellow.”

IC Insights’ latest market, unit, and average selling price forecasts for 33 major IC product segments for 2018 through 2022 is included in the March Update to the 2018 McClean Report (MR18).  The Update also includes an analysis of the major semiconductor suppliers’ capital spending plans for this year.

The biggest adjustments to the original MR18 IC market forecasts were to the memory market; specifically the DRAM and NAND flash segments.  The DRAM and NAND flash memory market growth forecasts for 2018 have been adjusted upward to 37% for DRAM (13% shown in MR18) and 17% for NAND flash (10% shown in MR18).

The big increase in the DRAM market forecast for 2018 is primarily due to a much stronger ASP expected for this year than was originally forecast.  IC Insights now forecasts that the DRAM ASP will register a 36% jump in 2018 as compared to 2017, when the DRAM ASP surged by an amazing 81%.  Moreover, the NAND flash ASP is forecast to increase 10% this year, after jumping by 45% in 2017.  In contrast to strong DRAM and NAND flash ASP increases, 2018 unit volume growth for these product segments is expected to be up only 1% and 6%, respectively.

At $99.6 billion, the DRAM market is forecast to be by far the largest single product category in the IC industry in 2018, exceeding the expected NAND flash market ($62.1 billion) by $37.5 billion.  Figure 1 shows that the DRAM market has provided a significant tailwind or headwind for total worldwide IC market growth in four out of the last five years.

The DRAM market dropped by 8% in 2016, spurred by a 12% decline in ASP, and the DRAM segment became a headwind to worldwide IC market growth that year instead of the tailwind it had been in 2013 and 2014.  As shown, the DRAM market shaved two percentage points off of total IC industry growth in 2016.  In contrast, the DRAM segment boosted total IC market growth last year by nine percentage points. For 2018, the expected five point positive impact of the DRAM market on total IC market growth is forecast to be much less significant than it was in 2017.

Figure 1

Figure 1

Qualcomm Incorporated (NASDAQ: QCOM) received a Presidential Order to immediately and permanently abandon the proposed takeover of Qualcomm by Broadcom Limited (NASDAQ: AVGO). Under the terms of the Presidential Order, all of Broadcom’s director nominees are also disqualified from standing for election as directors of Qualcomm.

Qualcomm was also ordered to reconvene its 2018 Annual Meeting of Stockholders on the earliest possible date, which based on the required 10-day notice period, is March 23, 2018. Stockholders of record on January 8, 2018 will be entitled to vote at the meeting.

Broadcom’s official statement after receiving the order was to strongly disagree that its proposed acquisition of Qualcomm raises any national security concerns.

“This should be viewed as a very positive event not only for Qualcomm but also for the market as a whole,” said Stuart Carlaw, Chief Research Officer at ABI Research. “The combined entity would have had dangerously dominant positions in some core markets such as location technologies, Wi-Fi, Bluetooth, RF hardware and automotive semiconductors. A diverse supplier ecosystem will be key to supporting the IoT as well as vertical market developments such as smart mobility and smart manufacturing.”

The Presidential Order is available at: https://www.whitehouse.gov/presidential-actions/presidential-order-regarding-proposed-takeover-qualcomm-incorporated-broadcom-limited/.