Category Archives: Device Architecture

North America-based manufacturers of semiconductor equipment posted $2.05 billion in billings worldwide in November 2017 (three-month average basis), according to the November Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in November 2017 was $2.05 billion. The billings figure is 1.6 percent higher than the final October 2017 level of $2.02 billion, and is 27.2 percent higher than the November 2016 billings level of $1.61 billion.

“November billings for North American equipment manufacturers increased modestly for the first time in four months,” said Dan Tracy, Senior Director, Industry Research and Statistics, at SEMI. “Year-to-date equipment spending is well on track to set a historical high, and we expect that positive momentum to continue into next year as new fabs in China begin to equip.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)
Year-Over-Year
June 2017
$2,300.3
34.1%
July 2017
$2,269.7
32.9%
August 2017
$2,181.8
27.7%
September 2017
$2,054.8
37.6%
October 2017 (final)
$2,019.3
23.9%
November 2017 (prelim)
$2,052.2
27.2%

Source: SEMI (www.semi.org), December 2017

 

Toshiba Corporation (TOKYO: 6502), Toshiba Memory Corporation and Western Digital Corporation (NASDAQ: WDC) have entered into a global settlement agreement to resolve their ongoing disputes in litigation and arbitration, strengthen and extend their relationship, and enhance the mutual commitment to their ongoing flash memory collaboration.

As part of this agreement, TMC and Western Digital will participate jointly in future rounds of investment in Fab 6, the memory fabrication facility now under construction at Yokkaichi, including the upcoming investment round announced by Toshiba in October 2017. Fab 6 will be entirely devoted to the mass production of BiCS FLASH, the next-generation of 3D flash memory, starting next year. TMC and Western Digital similarly intend to enter into definitive agreements in due course under which Western Digital will participate in the new flash wafer fabrication facility which will be constructed in Iwate, Japan.

The parties will strengthen their flash memory collaboration by extending the terms of their joint ventures. Flash Alliance will be extended to December 31, 2029 and Flash Forward to December 31, 2027. Flash Partners was previously extended to December 31, 2029.

The parties’ agreement to resolve all outstanding disputes ensures that all parties are aligned on Toshiba’s sale of TMC to K.K. Pangea, a special purpose acquisition company formed and controlled by a consortium led by Bain Capital Private Equity, LP (“Bain Capital”). The parties have agreed on mutual protections for their assets and confidential information in connection with the sale of TMC, and on collaborating to ensure the future success of TMC as a public company following an eventual IPO.

Commenting on the agreement reached today, Dr. Yasuo Naruke, Senior Executive Vice President of Toshiba Corporation and President and CEO of TMC said: “We are very pleased to have reached this outcome, which clearly benefits all involved. With the concerns about litigation and arbitration removed, we look forward to renewing our collaboration with Western Digital, and accelerating TMC’s growth to meet growing global demand for flash memory. Toshiba also remains on track to complete our transaction with the consortium led by Bain Capital by the end of March 2018. This will ensure that TMC has the resources it needs to continue to innovate and deliver for a fast-growing flash memory market, particularly in areas driven forward by advances in AI and IoT.”

Western Digital Chief Executive Officer Steve Milligan stated: “Western Digital’s core priorities have always been to protect the JVs and ensure their success and longevity, guarantee long-term access to NAND supply, protect our interests in the JVs, and create long-term value for our stakeholders. We are very pleased that these agreements accomplish these critical goals, allow Toshiba to achieve its objectives, and also enable us to continue delivering on the power of our platform. I want to thank the hardworking teams at Western Digital and TMC for the dedication they have exhibited over the past several months, operating the JVs without interruption, and we look forward to building upon the success of our 17 year partnership.”

Yuji Sugimoto, Managing Director, Head of Japan for Bain Capital said: “Bain Capital is pleased that Toshiba and Western Digital have resolved all outstanding legal disputes. The settlement represents the best possible outcome for all parties, clearing the way for the Bain Capital-led consortium to complete its acquisition of TMC as planned. We look forward to supporting TMC to achieve its strategic objectives while enhancing these important JVs with Western Digital.”

As part of the global settlement agreement, Toshiba, TMC and Western Digital have agreed to withdraw all pending litigation and arbitration actions.

IXYS Corporation (NASDAQ:IXYS), a global manufacturer of power semiconductors and integrated circuits (ICs) for energy efficiency, power management, transportation, medical, and motor control applications, today announced a new power semiconductor product line: 200V Ultra-Junction X3-Class HiPerFET Power MOSFETs. The current ratings range from 36A to 300A; a broad selection of devices are available in a number of international standard packages.

Fabricated using a charge compensation principle and IXYS’ own process technology, these new MOSFETs exhibit the lowest on-state resistances in the industry (3.5 milliohms in the SOT-227 package and 4 milliohms in the TO-264, for example). Along with gate charges as low as 21 nanocoulombs, these devices enable highest power densities and energy efficiencies in a wide variety of high-speed power conversion applications.

The fast body diodes of the devices are optimized and have low reverse recovery charge and time, thereby suppressing transients and enabling low-noise, high-efficiency power switching. Their low reverse recovery charge and time also boost efficiencies. In addition, these new MOSFETs are avalanche capable and exhibit a superior dv/dt performance (up to 20V/ns).

Targeted applications include synchronous rectification, battery chargers for light electric vehicles (LEVs), motor control (48V-110V systems), DC-DC converters, uninterruptible power supplies, electric forklifts, inverters, power solid state relays, and Class-D audio amplifiers.

The new 200V X3-Class Power MOSFETs with HiPerFET body diodes are available in the following international standard size packages: TO-3P, TO-220 (overmolded or standard), TO-247, PLUS247, TO-252, TO-263, TO-264, TO-268HV, SOT-227. Some example part numbers include IXFP36N20X3, IXFA72N20X3, IXFH90N20X3 and IXFN300N20X3, with current ratings of 36A, 72A, 90A and 300A, respectively.

Additional product information can be obtained by visiting the IXYS website at http://www.ixys.com or by contacting the company directly.

QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, display bridge and programmable logic solutions, announced that it has collaborated with Mentor, a Siemens business, to provide a seamless design and development environment for its embedded FPGA (eFPGA) technology. Specifically, Mentor’s Precision Synthesis software has been optimized to support the QuickLogic ArcticProTM architecture used in the company’s eFPGA IP.

QuickLogic will distribute this new version of Precision Synthesis as part of its Aurora development tool suite to provide high performance synthesis technology to eFPGA designers in their next SoC with embedded FPGA IP. The combination of the two tool sets will deliver a seamless development environment supporting a complete design flow, from RTL to programming bitstream, for the embedded FPGA portion of the design.

The tools from both companies have been tuned for implementation efficiency and design performance to enable the effective targeting of designs to the eFPGA IP. By embedding eFPGA technology, SoC developers gain post-manufacturing design flexibility to support design fixes, upgrades, market variants, and rapidly evolving standards or market requirements.

“We are pleased to collaborate with Mentor to give our customers complete design flow support for our eFPGA technology,” said Mao Wang, director of product marketing at QuickLogic Corporation. “Mentor has done an excellent job in enabling their Precision Synthesis software to generate an optimized synthesis netlist for the QuickLogic ArcticPro-based eFPGA architecture.”

“QuickLogic’s eFPGA IP has the potential to be a transformative technology for our SoC customers, and we are looking forward to delivering an outstanding synthesis solution for their Aurora development tools and a continued growth in our partnership,” said Ellie Burns, director of marketing, Calypto Systems Division at Mentor.

Mentor’s Precision Synthesis and QuickLogic Aurora development tools supporting QuickLogic’s eFPGA technology are both available now from QuickLogic Corporation.

Industry enters the age of WOW


December 13, 2017

By Christian G. Dieseldorff, Industry Research & Statistics Group, SEMI, Milpitas, California

The semiconductor industry has been there before, with large increases in investments followed by dramatic downturns. While the most dramatic downturns, 2001 and 2009, were due to, in a large part, acro-economic factors, the industry has typically observed one to two years of increased investment spending followed by a down period. This time around, the industry will achieve a “WOW” with three consecutive years of fab investment growth, a pattern not observed since the mid-1990s.

Why are things different this time?  A diverse array of technology drivers promise more robust long-term growth, such as Mobile applications, Internet of Things (IoT), Automotive & Robotics, Industrial, Augmented Reality & Virtual Reality (AR&VR), Artificial Intelligence (AI), and 5G networking. Each of these new technologies inspires a big “WOW” as the industry embarks on the beginning of a promising journey of growth.

Driven by these technologies, on average the semiconductor revenue CAGR from 2016 to 2021 is forecasted to be 6 percent (in comparison to the previous 2011-2016 CAGR of 2.3 percent). For the first time in the industry’s history, semiconductor revenues will exceed the US$400 billion revenue milestone in 2017. Demand for chips is high, pricing is strong for memory, and the competition is fierce. All of this is spurring increased fab investments, with many companies investing at previously unseen levels for new fab construction and fab equipment. See Figure 1.

Figure 1

Figure 1

The World Fab Forecast report, published on December 4, 2017, by SEMI, is modeling that fab equipment spending in 2017 will total US$57 billion or 41 percent year-over-year (YoY) growth. In 2018, spending is expected to shoot up another 11 percent at US$63 billion. The two spending jumps in 2017 and 2018 are contributing to the “WOW” factor and to two consecutive years of record fab investments. Following historic large investments, some slowdown is expected for 2019.

Many companies, such as Intel, Micron, Toshiba (and Western Digital), and GLOBALFOUNDRIES, have increased fab investments in 2017 and 2018; however, the strong increases we see in both years are not caused by these companies but by one company and primarily one region. See Figure 2.

Figure 2

Figure 2

The first jump – a Big WOW – in 2017 is the surge of investments in Korea, due mainly to Samsung. Samsung is expected to increase its fab equipment spending by 128 percent in 2017 from US$8 billion to US$18 billion. No single company has invested so much in a single year in its fabs and much of its spending is in Korea. SK Hynix also increased fab equipment spending, by about 70 percent, to US$5.5 billion, its largest spending level in its history.  While the bulk of Samsung’s and SK Hynix’s spending remains in Korea, some will also go to China, and in the case of Samsung to the United States. Both Samsung and SK Hynix are expected to maintain high levels of investments for 2018.

The second jump – another WOW – is investment growth for 2018 in China. China is expected to begin equipping the many fabs that were constructed in 2017. In the past, non-Chinese companies made the majority of the fab investments in China but for the first time in 2018, Chinese-owned companies will approach parity, spending nearly as much on fab equipment as non-Chinese device manufacturers.

Between 2013 and 2017, fab equipment spending in China by Chinese-owned companies typically ranged between US$1.5 billion to US$2.5 Billion per year, while non-Chinese companies invested between US$2.5 billion to US$5 billion per year. In 2018, Chinese-owned companies are expected to invest about US$5.8 billion, while non-Chinese will invest US$6.7 billion. Many new companies such as Yangtze Memory Technology, Fujian Jin Hua, Hua Li, and Hefei Chang Xin Memory are investing heavily in the region.

New fabs being built

Historic highs in equipment spending in 2017 and 2018 reflect growing demand. This spending follows unprecedented growth in construction spending for new fabs also detailed in SEMI’s World Fab Forecast report. Construction spending will reach all-time highs with China construction spending taking the lead: US$6 billion in 2017 and US$6.6 billion in 2018, shattering another record – no region has ever spent more than US$6 billion in a single year for construction. More new fabs mean another wave of spending on equipping fabs in the next few years. See Figure 3.

Fab-forecast-Chart3

Figure 3

Considering all of these “WOW” factors, there is good reason to feel positive about the semiconductor industry. Even with a slowdown, the industry has and will continue to enjoy a positive outlook for long-term growth. In the meantime, hold on tight and enjoy the “WOW.”

More details are available in SEMI’s just-published World Fab Forecast, December 4, 2017, edition which covers quarterly data (spending, capacity, technology nodes, wafer sizes, and product types) per fab until end of 2018.

Throughout 2017, DRAM manufacturers faced pressure to boost output of their devices—particularly high-performance DRAM used in data center servers, and low-power high-density DRAM used in smartphones and other mobile products. Strong, ongoing demand put significant upward pressure on DRAM average selling prices.  This trend continued into 4Q17 and is expected to drive quarterly DRAM sales to an all time high mark of $21.1 billion (Figure 1), capping an incredible year of growth in which DRAM sales set a new all time high sales mark each quarter. The forecast $21.1 billion sales level in 4Q17 would be an increase of 65% compared to the $12.8 billion DRAM market of 4Q16.

Figure 1

Figure 1

Annual DRAM market growth of 74% is forecast for 2017, which would be the highest growth rate since the 78% increase in 1994—23 years ago—and 61 points more than the 13% average DRAM market growth rate from 1993-2017 (Figure 2).  The expected 74% DRAM market growth in 2017 will mark the fourth time since 1993 that the DRAM market has increased by more than 50%.  This near-historic high market spike in 2017 was brought on by several factors, including constrained supply attributed to a lack of major fab expansion plans, yield difficulties with leading-edge (≤20nm) processes, demand for high performance (graphics) DRAM from gaming systems and data center-based server applications, and increased average content for mobile DRAM used in smartphones.

Figure 2

Figure 2

There is an increasing need for high-speed but inexpensive data storage in smartphone handsets for multi-tasking, which is boosting the average DRAM content in a smartphone.  The Apple iPhone 8 features 2GB of DRAM and the iPhone X has 3GB of DRAM.  The Samsung Galaxy S8 is sold with 4GB of DRAM (6GB in China).  Huawei’s P10 Plus, and HTC’s U11 come with 6GB of DRAM.  The One Plus 5 model and the first smartphone from Razer, a Singapore-based company that is primarily known for its video game equipment, have 8GB of DRAM.

With virtual and augmented reality and artificial intelligence becoming prominent features on new smartphones and apps, DRAM content in high-end smartphones shows no signs of slowing.  Meanwhile, DRAM growth for smartphones is also stemming from less developed countries, where much of the population is moving from feature phones to their first smartphone—literally transitioning from zero to 1GB of mobile DRAM.

Based on historical trends, the DRAM industry will likely experience a decline (possibly a big market decline) in its growth rate in the not-too-distant future as prices begin to tumble with significant capacity additions and an increase in DRAM output expected over the next year or two.  Announcements by Samsung and SK Hynix in the second half of 2017 confirmed that new DRAM capacity is set to come online in 2018, which likely will ease the upward trend of DRAM ASPs next year.  Samsung has stated its semiconductor capital expenditure budget for 2017 will be an enormous $26.0 billion, and SK Hynix has announced plans to build a new manufacturing line at its massive facility in Wuxi, China.  Micron has gone on record as saying it doubts that it will ever need to build another new DRAM fab, but it is hard to imagine that Micron will sit still as its two fiercest rivals capture additional marketshare.  (For the record, Micron and Intel are developing Crosspoint memory as a potential replacement for DRAM).

In a major step toward making a quantum computer using everyday materials, a team led by researchers at Princeton University has constructed a key piece of silicon hardware capable of controlling quantum behavior between two electrons with extremely high precision. The study was published Dec. 7 in the journal Science.

The researchers demonstrated the ability to control with precision the behavior of two silicon-based quantum bits, or qubits, paving the way for making complex, multi-qubit devices using technology that is less expensive and easier to manufacture than other approaches. Credit: David Zajac, Princeton University

The researchers demonstrated the ability to control with precision the behavior of two silicon-based quantum bits, or qubits, paving the way for making complex, multi-qubit devices using technology that is less expensive and easier to manufacture than other approaches. Credit: David Zajac, Princeton University

The team constructed a gate that controls interactions between the electrons in a way that allows them to act as the quantum bits of information, or qubits, necessary for quantum computing. The demonstration of this nearly error-free, two-qubit gate is an important early step in building a more complex quantum computing device from silicon, the same material used in conventional computers and smartphones.

“We knew we needed to get this experiment to work if silicon-based technology was going to have a future in terms of scaling up and building a quantum computer,” said Jason Petta, a professor of physics at Princeton University. “The creation of this high-fidelity two-qubit gate opens the door to larger scale experiments.”

Silicon-based devices are likely to be less expensive and easier to manufacture than other technologies for achieving a quantum computer. Although other research groups and companies have announced quantum devices containing 50 or more qubits, those systems require exotic materials such as superconductors or charged atoms held in place by lasers.

Quantum computers can solve problems that are inaccessible with conventional computers. The devices may be able to factor extremely large numbers or find the optimal solutions for complex problems. They could also help researchers understand the physical properties of extremely small particles such as atoms and molecules, leading to advances in areas such as materials science and drug discovery.

Building a quantum computer requires researchers to create qubits and couple them to each other with high fidelity. Silicon-based quantum devices use a quantum property of electrons called “spin” to encode information. The spin can point either up or down in a manner analogous to the north and south poles of a magnet. In contrast, conventional computers work by manipulating the electron’s negative charge.

Achieving a high-performance, spin-based quantum device has been hampered by the fragility of spin states — they readily flip from up to down or vice versa unless they can be isolated in a very pure environment. By building the silicon quantum devices in Princeton’s Quantum Device Nanofabrication Laboratory, the researchers were able to keep the spins coherent — that is, in their quantum states — for relatively long periods of time.

To construct the two-qubit gate, the researchers layered tiny aluminum wires onto a highly ordered silicon crystal. The wires deliver voltages that trap two single electrons, separated by an energy barrier, in a well-like structure called a double quantum dot.

By temporarily lowering the energy barrier, the researchers allow the electrons to share quantum information, creating a special quantum state called entanglement. These trapped and entangled electrons are now ready for use as qubits, which are like conventional computer bits but with superpowers: while a conventional bit can represent a zero or a 1, each qubit can be simultaneously a zero and a 1, greatly expanding the number of possible permutations that can be compared instantaneously.

“The challenge is that it’s very difficult to build artificial structures small enough to trap and control single electrons without destroying their long storage times,” said David Zajac, a graduate student in physics at Princeton and first-author on the study. “This is the first demonstration of entanglement between two electron spins in silicon, a material known for providing one of the cleanest environments for electron spin states.”

The researchers demonstrated that they can use the first qubit to control the second qubit, signifying that the structure functioned as a controlled NOT (CNOT) gate, which is the quantum version of a commonly used computer circuit component. The researchers control the behavior of the first qubit by applying a magnetic field. The gate produces a result based on the state of the first qubit: If the first spin is pointed up, then the second qubit’s spin will flip, but if the first spin is down, the second one will not flip.

“The gate is basically saying it is only going to do something to one particle if the other particle is in a certain configuration,” Petta said. “What happens to one particle depends on the other particle.”

The researchers showed that they can maintain the electron spins in their quantum states with a fidelity exceeding 99 percent and that the gate works reliably to flip the spin of the second qubit about 75 percent of the time. The technology has the potential to scale to more qubits with even lower error rates, according to the researchers.

“This work stands out in a worldwide race to demonstrate the CNOT gate, a fundamental building block for quantum computation, in silicon-based qubits,” said HongWen Jiang, a professor of physics and astronomy at the University of California-Los Angeles. “The error rate for the two-qubit operation is unambiguously benchmarked. It is particularly impressive that this extraordinarily difficult experiment, which requires a sophisticated device fabrication and an exquisite control of quantum states, is done in a university lab consisting of only a few researchers.”

SUNY Polytechnic Institute (SUNY Poly) Professor of Nanoengineering Bin Yu has been named a Fellow of the National Academy of Inventors (NAI), the organization announced Tuesday. Election to NAI Fellow status is one of the highest professional accolades bestowed solely to academic inventors who have demonstrated a prolific spirit of innovation in creating or facilitating outstanding inventions that have made a tangible impact on quality of life, economic development, and the welfare of society.

“I am proud to congratulate Dr. Yu on his selection as Fellow of the NAI, which is a strong reflection of his research that has helped to advance cutting-edge nanotechnologies,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “Dr. Yu’s numerous patents and continued SUNY Poly-based research in exciting areas such as nanomaterials and advanced nano-devices continues to hold promise for further developments that can enhance energy efficiency and boost computing speeds to improve the technologies that our society relies on each day.”

Those elected to the rank of NAI Fellow are named inventors on U.S. patents and were nominated by their peers for outstanding contributions to innovation, as well as for patents and licensing, innovative discovery and technology, and providing significant impact on society.

Dr. Yu has a number of significant accomplishments in the areas of nano electronic devices, nano-based sensors, nano-based energy harvesting, emerging data storage devices, next-generation interconnects, and smart nano-manufacturing, including work as the lead researcher for the world’s first 10 nm gate-length 3D transistor FinFET (IEEE-IEDM’2002), and for the world’s first THz silicon logic switch (IEEE-IEDM’2001).

Dr. Yu is the recipient of multiple awards and honors, including the NASA Innovation Award and IBM Faculty Award, and was ranked #3 by the National Science Foundation for Supported Investigators with Most Patents in 2011; as an inventor, he holds more than 300 awarded U.S. patents.

“I am honored that I have been selected to become a National Academy of Inventors Fellow, a powerful recognition of the work undertaken at SUNY Poly which can help to advance technology based on a wide variety of applied nanostrucutures,” said Dr. Yu. “I congratulate my fellow inductees and appreciate the acknowledgement of the importance of these research contributions that have led to more than 300 U.S. patents. I look forward to continuing to pursue efforts utilizing SUNY Poly’s state-of-the-art resources and capabilities for research related to nano-inspired technologies targeted for the next-generation of computing, sensing, and energy generation, as well as research related to emerging nanomaterials for smart nanomanufacturing.”

Dr. Yu has published books and book chapters on topics ranging from graphene-based electronics to 2D layered semiconductor-based emerging solar photovoltaics. He has also served as Editor of IEEE Electron Device Letters from 2001-2007, Associate Editor of IEEE Transactions on Nanotechnology from 2007-2010, and is currently an Editorial Board Member for Nano-Micro Letters and an Editorial Advisory Board Member for Nanoelectronics and Spintronics, among other leadership positions. Dr. Yu has been invited as a speaker to more than 100 highlight/invited talks, seminars, and tutorials to international conferences, universities, industry national labs, and professional societies. He is also an Institute of Electrical and Electronics Engineers (IEEE) Fellow and IEEE Electronic Device Society Distinguished Lecturer. More information about Dr. Yu’s background can be found here.

With the election of the 2017 class there are now 912 NAI Fellows, representing over 250 research universities and governmental and non-profit research institutes. The 2017 Fellows are named inventors on nearly 6,000 issued U.S. patents, bringing the collective patents held by all NAI Fellows to more than 32,000 issued U.S. patents.

Included among all NAI Fellows are more than 100 presidents and senior leaders of research universities and non-profit research institutes; 439 members of the National Academies of Sciences, Engineering, and Medicine; 36 inductees of the National Inventors Hall of Fame; 52 recipients of the U.S. National Medal of Technology and Innovation and U.S. National Medal of Science; 29 Nobel Laureates; 261 AAAS Fellows; 168 IEEE Fellows; and 142 Fellows of the American Academy of Arts & Sciences, among other awards and distinctions.

In April 2018 the 2017 NAI Fellows will be inducted as part of the Seventh Annual NAI Conference of the National Academy of Inventors at the Mayflower Hotel, Autograph Collection in Washington, D.C., and Andrew H. Hirshfeld, U.S. Commissioner for Patents, will provide the keynote address for the induction ceremony.

The 2017 class of NAI Fellows was evaluated by the 2017 Selection Committee, which included 18 members comprising NAI Fellows, U.S. National Medals recipients, National Inventors Hall of Fame inductees, members of the National Academies of Sciences, Engineering, and Medicine and senior officials from the USPTO, National Institute of Standards and Technology, Association of American Universities, American Association for the Advancement of Science, Association of Public and Land-grant Universities, Association of University Technology Managers, and National Inventors Hall of Fame, among other organizations.

Power electronics, which do things like modify voltages or convert between direct and alternating current, are everywhere. They’re in the power bricks we use to charge our portable devices; they’re in the battery packs of electric cars; and they’re in the power grid itself, where they mediate between high-voltage transmission lines and the lower voltages of household electrical sockets.

Power conversion is intrinsically inefficient: A power converter will never output quite as much power as it takes in. But recently, power converters made from gallium nitride have begun to reach the market, boasting higher efficiencies and smaller sizes than conventional, silicon-based power converters.

Commercial gallium nitride power devices can’t handle voltages above about 600 volts, however, which limits their use to household electronics.

At the Institute of Electrical and Electronics Engineers’ International Electron Devices Meeting this week, researchers from MIT, semiconductor company IQE, Columbia University, IBM, and the Singapore-MIT Alliance for Research and Technology, presented a new design that, in tests, enabled gallium nitride power devices to handle voltages of 1,200 volts.

That’s already enough capacity for use in electric vehicles, but the researchers emphasize that their device is a first prototype manufactured in an academic lab. They believe that further work can boost its capacity to the 3,300-to-5,000-volt range, to bring the efficiencies of gallium nitride to the power electronics in the electrical grid itself.

That’s because the new device uses a fundamentally different design from existing gallium nitride power electronics.

“All the devices that are commercially available are what are called lateral devices,” says Tomás Palacios, who is an MIT professor of electrical engineering and computer science, a member of the Microsystems Technology Laboratories, and senior author on the new paper. “So the entire device is fabricated on the top surface of the gallium nitride wafer, which is good for low-power applications like the laptop charger. But for medium- and high-power applications, vertical devices are much better. These are devices where the current, instead of flowing through the surface of the semiconductor, flows through the wafer, across the semiconductor. Vertical devices are much better in terms of how much voltage they can manage and how much current they control.”

For one thing, Palacios explains, current flows into one surface of a vertical device and out the other. That means that there’s simply more space in which to attach input and output wires, which enables higher current loads.

For another, Palacios says, “when you have lateral devices, all the current flows through a very narrow slab of material close to the surface. We are talking about a slab of material that could be just 50 nanometers in thickness. So all the current goes through there, and all the heat is being generated in that very narrow region, so it gets really, really, really hot. In a vertical device, the current flows through the entire wafer, so the heat dissipation is much more uniform.”

Narrowing the field

Although their advantages are well-known, vertical devices have been difficult to fabricate in gallium nitride. Power electronics depend on transistors, devices in which a charge applied to a “gate” switches a semiconductor material — such as silicon or gallium nitride — between a conductive and a nonconductive state.

For that switching to be efficient, the current flowing through the semiconductor needs to be confined to a relatively small area, where the gate’s electric field can exert an influence on it. In the past, researchers had attempted to build vertical transistors by embedding physical barriers in the gallium nitride to direct current into a channel beneath the gate.

But the barriers are built from a temperamental material that’s costly and difficult to produce, and integrating it with the surrounding gallium nitride in a way that doesn’t disrupt the transistor’s electronic properties has also proven challenging.

Palacios and his collaborators adopt a simple but effective alternative. The team includes first authors Yuhao Zhang, a postdoc in Palacios’s lab, and Min Sun, who received his MIT PhD in the Department of Electrical Engineering and Computer Science (EECS) last spring; Daniel Piedra and Yuxuan Lin, MIT graduate students in EECS; Jie Hu, a postdoc in Palacios’s group; Zhihong Liu of the Singapore-MIT Alliance for Research and Technology; Xiang Gao of IQE; and Columbia’s Ken Shepard.

Rather than using an internal barrier to route current into a narrow region of a larger device, they simply use a narrower device. Their vertical gallium nitride transistors have bladelike protrusions on top, known as “fins.” On both sides of each fin are electrical contacts that together act as a gate. Current enters the transistor through another contact, on top of the fin, and exits through the bottom of the device. The narrowness of the fin ensures that the gate electrode will be able to switch the transistor on and off.

“Yuhao and Min’s brilliant idea, I think, was to say, ‘Instead of confining the current by having multiple materials in the same wafer, let’s confine it geometrically by removing the material from those regions where we don’t want the current to flow,'” Palacios says. “Instead of doing the complicated zigzag path for the current in conventional vertical transistors, let’s change the geometry of the transistor completely.”

Leti, a research institute of CEA Tech, demonstrated significant improvements in the field of memory systems at IEDM 2017 this week.

These include reconfiguring Static Random-Access Memory (SRAM) into Content-Addressable Memory (CAM), improving non-volatile crossbar memories and using advanced Tunnel Field-Effect Transistors (TFET). Another breakthrough presents a high-density SRAM bitcell on Leti’s CoolCubeTM 3D platform, which reduces the area required for memory by 30 percent, while maintaining full device functionality. This breakthrough points the way to easing the major memory bottleneck in more complex systems on chip (SoC), where up to 90 percent of the SoC area might be taken by SRAM.

The breakthroughs were reported Dec. 5 at IEDM 2017 in a paper titled “Advanced Memory Solutions for Emerging Circuits and Systems.”

A key obstacle to shrinking SRAM on SoCs is bitcell-area limitations linked to required performance and yield, both of which become more challenging as technology scales. Lowering system power consumption is also limited by memory, as the SRAM performance and its stability scale less successfully than logic performance at lower voltages. Other memories like CAM might be affected even more by voltage scaling.

“All of these obstacles become particularly important for the Internet of Things, where ultralow-power consumption and the cost of individual nodes are crucial, and SRAM limitations have a big impact on both,” said Bastien Giraud, one of the paper authors.

Leti approached these challenges with a CoolCubeTM SRAM design focusing on the development of a compact and functional four-transistor bitcell, along with other innovations:

  • Reconfiguring memory between the CAM and SRAM, depending on the application
  • Optimizing memory using TFET, focusing on the exploitation of its negative differential-resistance effect to build ultralow-power SRAM, Flip Flops (FF) and refresh-free Dynamic Random Access Memory (DRAM)
  • A new compensation technique for crosspoint memory that reduces the voltage drop and leads to larger memory arrays.

Leti said its proposed CAM/SRAM outperforms memories, with operations at 1.56GHz and 0.13fJ/bit energy per search. In addition, the proposed TFET designs are competitive in terms of area, performance and static power consumption. Leti’s proposed compensation technique in crosspoint memory also enables the design of cost-efficient large memory arrays, while reducing the impact of temporal and spatial variations.

Short-term applications include crossbar circuits for storage-class memory and flexible SOCs with SRAM/CAM re-configurability.

“In the longer term, Leti’s CoolCubeTM technology will be able to deliver very high-density SRAM,” Giraud said. “Enabling TFET-based DRAM and integrating TFET standard cells into CMOS designs will allow circuit designers to take advantage of the best features of both technologies.”