Category Archives: Device Architecture

The technologies to watch identified by TechInsights analysts at the beginning of the year have not been disappointing.

BY STACY WEGNER, Ottawa, Canada, and JEONGDONG CHOE, Ottawa, Canada

TechInsights analysts have been keeping an intent watch on where technology has progressed, how it’s changing, and what new developments are emerging. At the end of the first quarter, our analysts shared their insights and thoughts about what to keep an eye on as the year unfolds. In this article, they provide an update on what 2017 has delivered so far.

Intelligent, connected devices

As we wrote earlier this year, in 2016, wearables were extremely interesting mainly because there was so much uncertainty around whether or not the market would be viable. Some, no, many, say the wearables market will cool off and possibly just expire. At TechInsights, we do will not speculate about whether this market is going to survive. We will report what we find and analyze what is currently being sold. Apple, Samsung, and Huawei have all released smartwatches for what would parallel a “flagship” in the mobile market (FIGURE 1). Fitness bands are becoming even ”smarter” and combining sensors where possible. Perhaps one of the most notable developments is Nokia’s acquisition and complete integration of Withings into its existing brands.

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We are witnessing the “rise of the machines,” in products from scales and hair brushes to rice cookers. Primarily these devices offer consumers convenience. For example, with a connected scale, instead of recording your weight manually, the smart scales do the job for you, syncing with various health apps so you can track your weight over time. The connected hair brush provides insights into your hair’s manageability, frizziness, dryness, split ends and breakage to provide a hair quality score. Brushing patterns, pressure applied and brush stroke counts are analyzed to measure effectiveness of brushing habits and a personal diagnosis is provided with tips and real-time product recommendations. The most common connected devices include refrigerators, lights, washing machines, thermostats, and televisions.

One dominant example is the ever-popular Amazon Echo, which has taken on a life of its own and is generating spin-off markets and competition. In July, it was reported that Amazon’s Alexa voice platform passed 15,000 skills — the voice-powered apps that run on devices like the Echo speaker, Echo Dot, newer Echo Show and others. The figure is up from the 10,000 skills Amazon officially announced in February. Amazon’s Alexa is building out an entire voice app ecosystem putting it much further ahead than its nearest competitor. The success seen with Echo has motivated other companies like Google, Lenovo, LG, Samsung and Apple to release compet- itive speakers, however it is estimated that Amazon is expected to control 70 percent of the market this year. In addition, Amazon and Microsoft recently announced a partnership to better integrate their digital assistants. This cross-platform integration provides users with access to Cortana features that Alexa is missing, and vice versa. Finally, the high- performance far-field microphones found in Amazon Echo products may soon find their way to other hardware companies as Amazon announced that the technology is available to those who want to integrate into the Alexa Experience. With its new reference solution, it’s never been easier for device makers to integrate Alexa and offer their customers the same voice experiences.

In the mobile market overall, we are seeing a strong emergence of devices targeted for the very hot market of India. The mobile devices for this market range from supporting 15 or more cellular bands to as few as five cellular bands, and that is for smart- phones. At TechInsights, we will be analyzing OEMs in India like Micromax, Intex, and Lava to see how they approach dealing with strong competitors like Samsung and Xiaomi.

Memory devices

In early 2017, 32L and 48L 3D NAND products were common and all the NAND players were eager to develop next generation 3D NAND products such as 64L and 128L. 3D NAND has been jumping into 64L (FIGURE 2). Samsung, Western Digital, Toshiba, Intel, and Micron already revealed CS or mass-products on the market. SK Hynix also showed their 72L NAND die as a CS product. In the second half of this year, we will see 64L and 72L NAND products on the commercial market. For n+1 generation with 96L or 128L, we expect that two-stacked cell array architecture for 3D NAND would be adopted in 2018. Micron/Intel will keep their own FG based 3D NAND cell structure for the next generation.

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Referring to DRAM, all the major players already used their advanced process technology for cell array integration such as an advanced ALD for high-k dielectrics, low damage plasma etching and honeycomb capacitor structure. Buried WL, landing pad and plug for a capacitor node, and MESH structure are still main stream. Samsung 18nm DRAM products for DDR4 and LPDDR4X are on the market. SK Hynix and Micron will reveal the same tech node DRAM products in this year. n+1 gener- ation with 15nm or 16nm node will be next in 2018. Once 6F2 15nm DRAM cell technology is successful, 4F2 DRAM products such as a capacitorless DRAM might be delayed. In 2018, 18nm and 15nm DRAM technology will be used for GDDR6 and LPDDR5.

When it comes to emerging memory, 3D XPoint memory technology is a hot potato (FIGURE 3). The XPoint products from Intel are on the market as an Optane SSD with 16GB and 32GB. Performance including retention, reliability and speed are not matched as expected, but they used a double stacked memory cell between M4 and M5 on the memory array. It’s a PCM with GST based material. An OTS with Se-As-Ge-Si is added between the PCM and the electrode (WL or BL). We expect to see multiple (triple or quadruple) stacked XPoint memory architecture within a couple years. For other emerging memory such as STT-MRAM, PCRAM and ReRAM, we’re waiting on some commercial products from Adesto (CBRAM 45nm, RM33 series) and Everspin (STT-MRAM pMTJ 256Mb, AUP-AXL-M128).

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Conclusion

The technologies to watch identified by TechInsights analysts at the beginning of the year have not been disappointing. As our analysts continue to examine and reveal the innovations others can’t inside advanced technology, we will continue to share our findings on these and new technologies as they emerge, including how they are used, how they impact the market, and how they will be changed by the next discovery or invention.

SEMI announced today that the Industry Strategy Symposium (ISS) 2018, will take place January 15-18 at Half Moon Bay’s Ritz-Carlton Hotel, with the theme “Smart, Intuitive & Connected: Semiconductor Devices Transforming the World.”  ISS is the year’s first executive check-in, bringing together leading analysts, researchers, economists, and technologists for insights on the forces impacting the semiconductor industry. The annual symposium offers executives a unique platform for identifying growth opportunities and gaining industry intelligence to help them ensure that their business plans and forecasts are based on up-to-the-minute market conditions. Registration for ISS is now open.

Major developments are transforming the extended supply chain — artificial intelligence, intelligent vehicles, augmented and virtual reality, and limitless connectivity within the cloud. Through collaboration across an expanding ecosystem and advanced technical innovations, today’s electronics are incorporating features that defy convention, while constantly raising performance and lowering power consumption, with smaller footprints,  reduced device sizes, and increasingly packaging heterogeneously integrated components.

The ISS 2018 will feature insightful keynote addresses, panel discussions, and presentations spanning four key session topics:

  • Economic Trends: Get an insider’s view from Alpha Capital Partners, BCA Research, Gartner, IHS Markit and SEMI.
  • Market Perspective: Autonomous cars, virtual reality, and cloud connectivity — where’s the growth? Hear perspectives from Amazon Web Services, Mentor (a Siemens Business), Nissan Research Center Silicon Valley and Oculus.
  • Technology: Emerging applications and major advances in equipment, materials, design, and packaging. Get insights from executives at ASM, ASML, IC Knowledge, imec, Intel, and Versum Materials.
  • Societal Disruptions by Technology: Robotics, artificial intelligence, social media — hear from representatives of Accenture, IBM, McKinsey & Co., Tufts University and VLSI Research, among others.

The industry is going through a major growth cycle and the challenges remain to stay strong ahead of the cycles. SEMI Industry Strategy Symposium 2018 will give industry professionals the knowledge needed to succeed. To learn more and to register, visit http://www.semi.org/en/ISS

The RC delay issues started a few nodes ago, and the problems are becoming worse.

BY ZSOLT TOKEI, imec, Leuven, Belgium

With the 7nm technology node in the development phase and the 5nm node moving into development, transistor scaling gets ever more complex. On top of that, the performance benefits gained at the front-end-of-line (i.e., the transistors) can easily be undone if the back-end-of-line can’t come along. BEOL processing involves the creation of stacked layers of Cu wires that electrically interconnect the transistors in the chip. Today, high-end logic chips easily have 12 to 15 levels of Cu wires. With each technology node, this Cu wiring scheme becomes more complex, mainly because there are more transistors to connect with an ever tighter pitch. Shrinking dimensions also means the wires have a reduced cross-sectional area, which drives up the resistance-capacitance product (RC) of the interconnect system. And this results in strongly increasing signal delay. The RC delay issues started a few nodes ago, and the problems are becoming worse. For example, a delay of more than 30% is expected when moving from the 10nm to the 7nm node.

The current BEOL flow

Cu-based dual damascene has been the workhorse process flow for interconnects since its introduction in the mid 1990s. A simple dual damascene flow starts with the deposition of a low-k dielectric material on a structure. These low-k films are designed to reduce the capacitance and the delay in the ICs. In a next step, this dielectric layer is covered with an oxide and a resist, and vias and trenches are formed using lithography and etch steps. These vias connect one metal layer with the layer above or below. Then, a metallic barrier layer is added to prevent Cu atoms from migrating into the low-k materials (FIGURE 1). The barrier layers are deposited with physical vapor deposition, using materials such as tantalum and tantalum nitride, and subsequently coated by a Cu seed barrier. In a final step, this structure is electroplated by Cu in a chemical mechanical polishing (CMP) step.

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A 5nm technology full dual damascene module

The semiconductor industry is hugely in favor of extending the current dual damascene technology as long as possible before moving to a new process. And this starts with incremental changes to the current technology, which should suffice for further scaling to at least the 5nm technology node. Researchers at imec have demonstrated a full dual damascene module for the 5nm technology node. At this node, the BEOL process becomes extremely complex, and interconnects are designed at very tight pitches. For example, a 50% area scaling in logic and 60% scaling of an SRAM cell from 7nm to 5nm results in a gate pitch at around 42nm and an intermediate first routing metal at 32nm pitch (or 16nm half pitch, which is half the distance between identical features). In these BEOL layers, trenches are created which are then filled with metal in a final metallization step. In order to create electrically functional lines, perpendicular block layers to the trenches are added, where metal traces are not formed. One of the many challenges to scaling the interconnects relates to the patterning options. Patterning these tight pitch layers is no longer possible by using single immersion lithography and direct etch steps. Only multi-patterning – which is known to be very costly and complex – is possible either by immersion or by EUV or by a combination of immersion and EUV exposures to form a single metal layer. At IITC, imec showed a full integration flow using multi-patterning, which enables the patterning of tight-pitch metal-cut (the blocks), and effectively scaling the trench critical dimension to 12nm at 16nm half pitch. The researchers also looked at the reliability, for example at electromigration issues caused by the movement of atoms in the interconnect wires. They demonstrated the ability of imec’s Cu metallization scheme at 16nm critical dimension with extendibility to 12nm width, and investigated full ruthenium (Ru) metallization as copper replacement.

Scaling the BEOL beyond the 5nm node

For the technology nodes below the 5nm, the team of imec is investigating a plethora of options and comparing their merits. Options include new materials for conductors and dielectrics, barrier layers, vias, and new ways to deposit them; innovative BEOL architectures for making 2.5D/3D structures; new patterning schemes; co-optimization of system and technology, etc.

For example, to achieve manufacturable processes and at the same time control the RC delay, scaling boosters, such as fully self-aligned vias, are increasingly being used. Via alignment is a critical step in the BEOL process, as it defines the contact area between subsequent interconnect levels. Any misalignment impacts both resistance and reliability. Imec’s team has shown the necessity of using a fully self-aligned via to achieve overlay specifications, and proposed a process flow for 12nm half pitch structures.

Also, self-assembled monolayers (SAMs) open routes to new dielectric and conductor schemes. SAMs composed of sub-1nm organic chains and terminated with desired functional groups can help engineering thin-film dielectric and metal interfaces, and can strongly inhibit interfacial diffusion. The use of SAMs has been a topic of research for the past ten years. Imec has now moved this promising concept from lab to fab, and combined SAMs with a barrier/liner/metallization scheme on a full wafer. The researchers investigated the implica- tions on the performance and scaling ability of this process flow, and demonstrated a ~18% reduction in the RC of 22nm half-pitch dual damascene intercon- nects, due to a better interface and thinner barrier.

For conventional BEOL metallization, a barrier layer is coated by a Cu seed barrier, and this structure is electroplated with low-resistive Cu, which acts as the conductor. But when moving to sub-10nm interconnects, the resistivity of Cu continues to increase. At the same time, the diffusion barrier – which is highly resistive and difficult to scale – is taking up more space, thereby increasing the overall resistance of the barrier/Cu structure. Therefore, alternative metals are being investigated that could possibly serve as a replacement for Cu and do not require a diffusion barrier. Among the potential candidates, such as Co, Ni, Mo, etc., platinum-group metals, especially ruthenium (Ru), have shown great promise due to their low bulk resistivity and resistance to oxidation. They also have a high melting point which can result in better electromigration behavior (FIGURE 2). Imec has realized Ru nanowires with 58nm2 cross section area. The nanowires exhibit low resistivity and robust wafer-level reliability. For example, a very high current carrying capacity with fusing currents as high as 720MA/cm2 was demonstrated.

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At the 2017 IITC conference, this author was invited to take part in a panel discussion, organized by Applied Materials, to discuss the latest developments in metallization at single-digit nodes, the challenges and bottlenecks arising at these very small dimensions, and new application-driven requirements. Distinguished speakers from the technical field reviewed viable solutions for extending the current technology and alternative options were discussed. From the discussion it is clear that the biggest immediate benefit can be found in the area of conductors – both from the material side as well as design. Indeed, it is driving the replacement of copper at specific metallization levels. Other avenues – such as dielectric innovations, functionality in the BEOL or 2D materials – remain interesting options for the R&D pipeline.

As an option that is further out, spin wave propagation in conductors is an alternative signaling to traditional electron based propagation.

Adding additional functionality in the BEOL

In the future, more and more technology options may get dictated by the requirements of systems or even applications. This could result in a separate technology for e.g. high-performance computing, low-power mobile communication, chips for use in medical applications, or dedicated chips for IoT sensors. Along the same lines, imec is investigating the benefits of introducing additional functionality in the BEOL.

More specifically, imec is evaluating the possibility of integrating thin-film organic transistors – with typically low-leakage level – into the BEOL interconnect circuitry of Si FinFETs. The potential advantages of fabricating them together are mainly a reduced power consumption and improved area saving. A variety of circuits can fully utilize the benefits of this hybrid processing, including portable applications, eDRAM, displays and FPGA applications. As a concrete example, imec researchers are currently merging imec’s expertise in BEOL technologies and in thin-film-based flat panel displays, thereby opening opportunities for new applications…

MagnaChip Semiconductor Corporation(NYSE: MX), a designer and manufacturer of analog and mixed-signal semiconductor products, announced today it now offers a 0.35 micron 700V Ultra-High Voltage process technology (UHV) that reduces mask counts, manufacturing time and cost for power-related AC-DC products. This UHV process technology offers 700V nLDMOS, 700V JFET, and 5.5V CMOS devices that are suitable for manufacturing AC-DC converter ICs and LED driver ICs.

The demand for AC-powered products in home appliances continues to increase, creating the need for highly efficient and cost-competitive AC-DC converter ICs, AC-DC chargers and LED driver ICs.  MagnaChip’s 0.35 micron 700V UHV process technology is a suitable match to manufacture these types of power-related products.

MagnaChip provides various types of UHV technology to meet the diverse demands of the customers. HP35ULB700, the newly developed UHV process, eliminates five photolithography steps through process simplification compared with MagnaChip’s previous generation of UHV technology, making it possible to reduce manufacturing cost and to accelerate the time to market. Among the devices offered in HP35ULB700 are 700V low Ron nLDMOS, 500V nLDMOS, 700V JFET, 5.5V CMOS, BJT, 700V resistor, BP cap, and MIM and fuse. All these devices enable the integrated solution of AC-DC converter ICs and LED driver ICs. The 700V low Ron nLDMOS devices offer improved specific-on-resistance of 150 mohm·cm2. In addition, the devices enable various design schemes, including the possibility to separate or connect the source and the bulk in nLDMOS.

YJ Kim, MagnaChip’s Chief Executive Officer, commented, “Our  0.35 micron 700V UHV technology  provides our foundry customers with a high-performance, highly efficient manufacturing process for AC-DC converter ICs and LED driver ICs for various LED lighting applications.” Mr. Kim added, “To meet the diverse customer requirements, MagnaChip will continue to develop new UHV technologies such as customer-specific UHV processes with additional option devices.”

Broadcom Limited (NASDAQ: AVGO) (“Broadcom”), a semiconductor device supplier to the wired, wireless, enterprise storage, and industrial end markets, today announced a proposal to acquire all of the outstanding shares of Qualcomm Incorporated (NASDAQ: QCOM) (“Qualcomm”) for per share consideration of $70.00 in cash and stock.

Under Broadcom’s proposal, the $70.00 per share to be received by Qualcomm stockholders would consist of $60.00 in cash and $10.00 per share in Broadcom shares. Broadcom’s proposal represents a 28% premium over the closing price of Qualcomm common stock on November 2, 2017, the last unaffected trading day prior to media speculation regarding a potential transaction, and a premium of 33% to Qualcomm’s unaffected 30-day volume-weighted average price. The Broadcom proposal stands whether Qualcomm’s pending acquisition of NXP Semiconductors N.V. (“NXP”) is consummated on the currently disclosed terms of $110 per NXP share or the transaction is terminated. The proposed transaction is valued at approximately $130 billion on a pro forma basis, including $25 billion of net debt, giving effect to Qualcomm’s pending acquisition of NXP on its currently disclosed terms.

“Broadcom’s proposal is compelling for stockholders and stakeholders in both companies. Our proposal provides Qualcomm stockholders with a substantial and immediate premium in cash for their shares, as well as the opportunity to participate in the upside potential of the combined company,” said Hock Tan, President and Chief Executive Officer of Broadcom. “This complementary transaction will position the combined company as a global communications leader with an impressive portfolio of technologies and products. We would not make this offer if we were not confident that our common global customers would embrace the proposed combination. With greater scale and broader product diversification, the combined company will be positioned to deliver more advanced semiconductor solutions for our global customers and drive enhanced stockholder value.”

Tan continued, “We have great respect for the company founded 32 years ago by Irwin Jacobs, Andrew Viterbi and their colleagues, and the revolutionary technologies they developed. Following the combination, Qualcomm will be best positioned to build on its legacy of innovation and invention. Given the common strengths of our businesses and our shared heritage of, and continued focus on, technology innovation, we are confident we can quickly realize the benefits of this compelling transaction for all stakeholders. Importantly, we believe that Qualcommand Broadcom employees will benefit from substantial opportunities for growth and development as part of a larger company.”

Thomas Krause, Broadcom Chief Financial Officer, added, “The Broadcom business continues to perform very well. Broadcom has completed five major acquisitions since 2013, and has a proven track record of rapidly deleveraging and successfully integrating companies to create value for our stockholders, employees and customers. Given the complementary nature of our products, we are confident that any regulatory requirements necessary to complete a combination with Qualcomm will be met in a timely manner. We look forward to engaging immediately in discussions with Qualcomm so that we can sign a definitive agreement and complete this transaction expeditiously.”

 

“The combined Qualcomm/Broadcom operation would represent the third largest global semiconductor supplier. The Qualcomm shareholders are likely to be split with many viewing this opportunity as a solution to the worsening relations with Apple, whom Broadcom has a good relationship with. The potential merger raises significant questions surrounding the difficult takeover of NXP by Qualcomm and much is still to be discerned regarding the value of the Qualcomm patent holdings and its associated lucrative high-margin revenue stream,” said Stuart Carlaw, Chief Research Officer at ABI Research.

Researchers at UC Berkeley and UC Riverside have developed a new, ultrafast method for electrically controlling magnetism in certain metals, a breakthrough that could lead to greatly increased performance and more energy-efficient computer memory and processing technologies.

In this schematic of a magnetic memory array, an ultrafast electrical pulse switches a magnetic memory bit.

In this schematic of a magnetic memory array, an ultrafast electrical pulse switches a magnetic memory bit.

The findings of the group, led by Berkeley electrical engineering and computer sciences (EECS) professor Jeffrey Bokor, are published in a pair of articles in the journals Science Advances (Vol. 3, No. 49, Nov. 3, 2017) and Applied Physics Letters (Vol. III, No. 4, July 24, 2017).

Computers use different kinds of memory technologies to store data. Long-term memory, typically a hard disk or flash drive, needs to be dense in order to store as much data as possible. But the central processing unit (CPU) — the hardware that enables computers to compute — requires its own memory for short-term storage of information while operations are executed. Random Access Memory (RAM) is one example of such short-term memory.

Reading and writing data to RAM needs to be extremely fast in order to keep up with the CPU’s calculations. Most current RAM technologies are based on charge (electron) retention, and can be written at rates of billions of bits per second (or bits/nanosecond). The downside of these charge-based technologies is that they are volatile, requiring constant power or else they will lose the data.

In recent years, magnetic alternatives to RAM, known as Magnetic Random Access Memory (MRAM), have reached the market. The advantage of magnets is that they retain information even when memory and CPU are powered off, allowing for energy savings. But that efficiency comes at the expense of speed. A major challenge for MRAM has been to speed up the writing of a single bit of information to less than 10 nanoseconds.

“The development of a non-volatile memory that is as fast as charge-based random-access memories could dramatically improve performance and energy efficiency of computing devices,” says Bokor. “That motivated us to look for new ways to control magnetism in materials at much higher speeds than in today’s MRAM.”

“Inspired by recent experiments in the Netherlands on ultrafast magnetic switching using sub-picosecond duration laser pulses, we built special circuits to study how magnetic metals respond to electrical pulses as short as a few trillionths of a second,” or picoseconds, says coauthor Yang Yang (M.S.’13 Ph.D.’17 MSE). “We found that in a magnetic alloy made up of gadolinium and iron, these fast electrical pulses can switch the direction of the magnetism in less than 10 picoseconds. That is orders of magnitude faster than any other MRAM technology.”

“The electrical pulse temporarily increases the energy of the iron atom’s electrons,” says Richard Wilson, currently an assistant professor of mechanical engineering at UC Riverside who began his work on this project as a postdoctoral researcher in EECS at Berkeley.  “This increase in energy causes the magnetism in the each of the iron and gadolinium atoms to exert torque on one another, and eventually leads to a reorientation of the metal’s magnetic poles. It’s a completely new way of using electrical currents to control magnets.”

After their initial demonstration of electrical writing in the special gadolinium-iron alloy, the research team sought ways to expand their method to a broader class of magnetic materials.  “The special magnetic properties of the gadolinium-iron alloy are what makes this work,” says Charles-Henri Lambert, a Berkeley EECS postdoc. “Therefore, finding a way to expand our approach for fast electrical writing to a broader class of magnetic materials was an exciting challenge.”

Addressing that latter challenge was the subject of a second study, published in Applied Physics Letters in July.  “We found that when we stack a single-element magnetic metal such as cobalt on top of the gadolinium-iron alloy, the interaction between the two layers allows us to then manipulate the magnetism of the cobalt on unprecedented time-scales as well,” says Jon Gorchon, a postdoctoral research in the Materials Sciences Division at Lawrence Berkeley Lab and in EECS at UC Berkeley.

“Together, these two discoveries provide a route toward ultrafast magnetic memories that enable  a new generation of high-performance, low power computing processors with high-speed, non-volatile memories right on chip, ” Bokor says.

Additional team members include Akshay Pattabi, a Berkeley EECS Ph.D. candidate, and Berkeley EECS professor Sayeef Salahuddin. The research was supported by grants from the National Science Foundation and the U.S. Department of Energy.

Xilinx, Inc. (NASDAQ: XLNX) today announced the appointment of two new members to the Company’s Board of Directors, increasing its total size to eleven. Mary Louise (ML) Krakauer, an independent director who will also serve on the Board’s Compensation Committee, joins the Board alongside Victor Peng, the Company’s chief operating officer. Both Ms. Krakauer and Mr. Peng bring decades of executive management experience and industry expertise to Xilinx.

“We are delighted to have ML and Victor join the Board of Directors,” said Dennis Segers, chairman of the board of Xilinx. “ML comes to us through an extensive search, and she brings deep executive and operational experience to the Board. Her expertise in human capital management, in particular, will enhance the effectiveness of our Compensation Committee. The Board also continues to focus on our previously announced CEO succession plan. Victor’s appointment reflects the continued expansion of his role and responsibilities at Xilinx, and we look forward to adding to our Board his unique combination of Company knowledge, technical expertise and leadership skills that have made him an outstanding executive.”

Ms. Krakauer retired as the executive vice president, chief information officer of Dell Corporation in January 2017, where she was responsible for global IT, including all operations and integration activity. She also served as the executive vice president, chief information officer of EMC Corporation in 2016. Prior to that she served as executive vice president, Business Development, Global Enterprise Services for EMC in 2015 and as executive vice president, Global Human Resources for EMC from 2012 to 2015, where she was responsible for executive, leadership, and employee development, compensation and benefits, staffing, and all of the people-related aspects of acquisition integration.  Previously, she held leadership roles at Hewlett-Packard Corporation, Compaq Computer Corporation, and Digital Equipment Corporation. Ms. Krakauer serves on the board of Mercury Systems, Inc., a Nasdaq-listed commercial provider of secure sensor and safety critical mission processing subsystems.

Mr. Peng joined Xilinx in 2008, and became the Company’s chief operating officer in April of this year, with responsibility for global sales, global operations and quality, product development, and product and vertical marketing. Prior to that, he served as the Company’s executive vice president and general manager of Products, a position he held since July 2014. Mr. Peng has over 30 years of experience defining and bringing to market leadership FPGAs, All Programmable SoCs, GPUs, high performance microprocessors and chip sets, and microprocessor IP products. Mr. Peng previously held executive roles at AMD, ATI, and MIPS Technologies.

Researchers at the U.S. Department of Energy’s (DOE) National Renewable Energy Laboratory (NREL) established a new world efficiency record for quantum dot solar cells, at 13.4 percent.

Colloidal quantum dots are electronic materials and because of their astonishingly small size (typically 3-20 nanometers in dimension) they possess fascinating optical properties. Quantum dot solar cells emerged in 2010 as the newest technology on an NREL chart that tracks research efforts to convert sunlight to electricity with increasing efficiency. The initial lead sulfide quantum dot solar cells had an efficiency of 2.9 percent. Since then, improvements have pushed that number into double digits for lead sulfide reaching a record of 12 percent set last year by the University of Toronto. The improvement from the initial efficiency to the previous record came from better understanding of the connectivity between individual quantum dots, better overall device structures and reducing defects in quantum dots.

The latest development in quantum dot solar cells comes from a completely different quantum dot material. The new quantum dot leader is cesium lead triiodide (CsPbI3), and is within the recently emerging family of halide perovskite materials. In quantum dot form, CsPbI3 produces an exceptionally large voltage (about 1.2 volts) at open circuit.

“This voltage, coupled with the material’s bandgap, makes them an ideal candidate for the top layer in a multijunction solar cell,” said Joseph Luther, a senior scientist and project leader in the Chemical Materials and Nanoscience team at NREL. The top cell must be highly efficient but transparent at longer wavelengths to allow that portion of sunlight to reach lower layers. Tandem cells can deliver a higher efficiency than conventional silicon solar panels that dominate today’s solar market.

This latest advance, titled “Enhanced mobility CsPbI3 quantum dot arrays for record-efficiency, high-voltage photovoltaic cells,” is published in Science Advances. The paper was co-authored by Erin Sanehira, Ashley Marshall, Jeffrey Christians, Steven Harvey, Peter Ciesielski, Lance Wheeler, Philip Schulz, and Matthew Beard, all from NREL; and Lih Lin from the University of Washington.

The multijunction approach is often used for space applications where high efficiency is more critical than the cost to make a solar module. The quantum dot perovskite materials developed by Luther and the NREL/University of Washington team could be paired with cheap thin-film perovskite materials to achieve similar high efficiency as demonstrated for space solar cells, but built at even lower costs than silicon technology–making them an ideal technology for both terrestrial and space applications.

“Often, the materials used in space and rooftop applications are totally different. It is exciting to see possible configurations that could be used for both situations,” said Erin Sanehira a doctoral student at the University of Washington who conducted research at NREL.

Dialog Semiconductor plc (XETRA:DLG), a provider of highly integrated power management, AC/DC power conversion, charging, and low power connectivity technology, announced today that it has completed the acquisition of privately-held Silego Technology Inc. (“Silego”), a provider of Configurable Mixed-signal ICs (CMICs).

Headquartered in Santa Clara, California with approximately 235 employees worldwide, Silego is the pioneer and market leader in CMICs that integrate multiple analog, logic, and discrete component functionality into a single chip. Silego’s product portfolio will strengthen Dialog’s presence in markets including IoT, computing and automotive.

“The acquisition of Silego brings a highly complementary technology to Dialog. What Silego has developed is truly unique – a mixed-signal platform which customers can configure to their design requirements on the fly, drastically reducing the time to bring their products to market,” said Jalal Bagherli, CEO of Dialog. “With global scale and customer access, Dialog is the right platform to further accelerate industry wide CMIC adoption. Furthermore, we gain an exceptional group of talented people that will fit well with Dialog’s culture. Together, we will significantly increase the value we can bring to our customers by creating a better-positioned and more-diversified mixed signal offering.”

“We believe Dialog will be a great environment for the Silego team to grow as part of a much larger company serving global customers,” stated John Teegen, CEO of Silego Technology. “Our proprietary and configurable approach has allowed Silego to establish leadership while creating a new market. By leveraging Dialog’s technology and capabilities, I am confident we can further drive adoption of CMICs.”

Silego anticipates achieving over $80 million of revenue in 2017 and double-digit growth in 2018. The transaction is expected to be accretive to Dialog’s underlying EPS for full calendar year 2018 and accretive to Dialog’s gross margin.

This article first appeared on SemiMD.com.

With mask costs rising and the need for flexibility growing, companies are beginning to adopt embedded field programmable gate arrays in their SoC designs.

BY DAVE LAMMERS, Contributing Editor

It was back in 1985 that Ross Freeman invented the FPGA, gaining a fundamental patent (#4,870,302) that promised engineers the ability to use “open gates” that could be “programmed to add new functionality, adapt to changing standards or specifications, and make last-minute design changes.”

Freeman, a co-founder of Xilinx, died in 1989, too soon to see the emerging development of embedded field programmable logic arrays (eFPGAs). The IP cores offer system-on-chip (SoC) designers an ability to create hardware accelerators and to support changing algorithms. Proponents claim the approach provides advantages to artificial intelligence (AI) processors, automotive ICs, and the SoCs used in data centers, software-defined networks, 5G wireless, encryption, and other emerging applications.

With mask costs escalating rapidly, eFPGAs offer a way to customize SoCs without spinning new silicon. While eFPGAs cannot compete with custom silicon in terms of die area, the flexibility, speed, and power consumption are proving attractive.

Semico Research analyst Rich Wawrzyniak, who tracks the SoC market, said he considers eFPGAs to be “a very profound development in the industry, a capability that is going to get used in lots of places that we haven’t even imagined yet.”

While Altera, now owned by Intel, and Xilinx, have not ventured publicly into the embedded space, Wawrzyniak noted that a lively bunch of competitors are moving to offer eFPGA intellectual property (IP) cores.

Multiple competitors enter eFPGA field

Achronix Semiconductor (Santa Clara, Calif.) has branched out from its early base in stand-alone FPGAs, using Intel’s 22nm process, to an IP model. It is emphasizing its embeddable Speedcore eFPGAs that can be added to SoCs using TSMC’s 16FF foundry process. 7nm IP cores are under development.

Efinix Inc. (Santa Clara recently rolled out its Efinix Programmable Accelerator (EPA) technology.

Efinix (efinixinc.com) claims that its programmable arrays can either compete with established stand-alone FPGAs on performance, but at half the power, or can be added as IP cores to SoCs. The Efinix Programmable Accelerator technology can provide a look up table (LUT)-based logic cell or a routing switch, among other functions, the company said.

Efinix was founded by several managers with engineering experience at Altera Corp. at various times in their careers — Sammy Cheung, Tony Ngai, Jay Schleicher, and Kar Keng Chua — and has financial backing from two Malaysia-based investment funds.

Flex Logix Technologies, (Mountain View, Calif.) (www.flex-logix.com) an eFPGA startup founded in 2014, recently gained formal admittance to TSMC’s IP Alliance program. It supports a wide array of foundry processes, providing embedded FPGA IP and software tools for TSMC’s 16FFC/FF+, 28HPM/HPC, and 40ULP/LP.

QuickLogic adds SMIC to foundry roster

Menta  (http://www.menta-efpga.com/) is another competitor in the FPGA space. Based in Montpellier, France, Menta is a privately held company founded a decade ago that offers programmable logic IP targeted to both GLOBALFOUNDRIES (14LPP) and TSMC (28HPM and 28HPC+) processes.

Menta offers either pre-configured IP blocks, or custom IPs for SoCs or ASICs. The French company supports its IP with a tool set, called Origami, which generates a bitstream from RTL, including synthesis. Menta said it has fielded four generations of products that in use by customers now “for meeting the sometimes conflicting requirements of changing standards, security updates and shrinking time-to-market windows of mobile and consumer products, IoT devices, networking and automotive ICs.”

QuickLogic, a Silicon Valley stalwart founded in 1988, also is expanding its eFPGA capability. In mid-September, QuickLogic (Sunnyvale, Calif.) (quicklogic.com) announced that its eFPGA IP can now be used with the 40nm low-leakage process at Shanghai-based Semiconductor Manufacturing International Corp. (SMIC). QuickLogic also offers its eFPGA technology on several of the mature GLOBALFOUNDRIES processes, and is participating in the foundry’s 22FDX IP program.

Wawrzyniak, who tracks the SoC market for Semico Research, said an important market is artificial intelligence, using eFPGA gates to add a flexible convolutional neural network (CNN) capability. Indeed, Flex Logix said one of its earliest adopters is an AI research group at Harvard University that is developing a programmable AI processor.

A seminal capability

The U.S. government’s Defense Advanced Projects Agency (DARPA) also has supported Flex Logix by taking a license, endorsing an eFPGA capability for defense and aerospace ICs used by the U.S. military.

With security being such a concern for the Internet of Things edge devices market, Wawrzyniak said eFPGA gates could be used to secure IoT devices against hackers, a potentially large market.

“The major use is in apps and instances where people need some programmability. This is a seminal, basic capability. How many times have you heard someone say, ‘I wish I could put a little bit of programmability into my SoC.’ People are going to take this and run with it in ways we can’t imagine,” he said.

Bob Wheeler, networking analyst at The Linley Group, said the intellectual property (IP) model makes sense for startups. Achronix, during the dozen years it developed and then fielded its standalone FPGAs, “was on a very ambitious road, competing with Altera and Xilinx. Achronix went down the road of developing parts, and that is a tall order.”

While the cost of running an IP company is less than fielding stand-alone parts, Wheeler said “People don’t appreciate the cost of developing the software tools, to program the FPGA and configure the IP.” The compiler, in particular, is a key challenge facing any FPGA vendor.

Wheeler said Achronix https://www.achronix.com/ , has gained credibility for its tools, including its compiler, after fielding its high-performance discrete FPGAs in 2016, made on Intel’s 22nm process.

And Wheeler cautioned that IP companies face the business challenge of getting a fair return on their development efforts, especially for low-cost IoT solutions where companies maintain tight budgets for the IP that they license.

Achronix earlier this year announced that its 2017 revenues will exceed $100 million, based on a seven-times increase in sales of its Speedster 22i FPGA family, as well as licensing of its Speedcore embedded IP products, targeted to TSMC’s leading-edge 16 nm node, with 7nm process technology for design starts beginning in the second half of this year. Achronix revenues “began to significantly ramp in 2016 and the company reached profitability in Q1 2017,” said CEO Robert Blake.

Escalating mask costs

Geoff Tate, now the CEO of Flex Logix Technologies, earlier headed up Rambus for 15 years. Tate said Flex Logix (www.flex-logix.com uses a hierarchical interconnect, developed by co-founder Cheng Wang and others while he earned his doctorate at UCLA. The innovative interconnect approach garnered the Lewis Outstanding Paper award for Wang and three co-authors at the 2014 International Solid-State Circuits Conference (ISSCC), and attracted attention from venture capitalists at Lux Ventures and Eclipse Ventures.

Tate said one of those VCs came to him one day and asked for an evaluation of Wang & Co.’s technology. Tate met with Wang, a native of Shanghai, and found him to be anything but a prima donna with a great idea. “He seemed very motivated, not just an R&D guy.”

While most FPGAs use a mesh interconnect in an X-Y grid of wires, Wang had come up with a hierarchical interconnect that provided high density without sacrificing performance, and proved its potential with prototype chips at UCLA.

“Chips need to be more flexible and adaptable. FPGAs give you another level of programmability,” Tate noted.

Meanwhile, potential customers in networking, data centers, and other markets were looking for ways to make their designs more flexible. An embedded FPGA block could help customers adapt a design to new wireless and networking protocols. Since mask costs were escalating, to an estimated $5 million for 16nm designs and more than double that for 7nm SoCs, customers had another reason to risk working with a startup.

TSMC has supported Flex Logix, in mid-September awarding the company the TSMC Open Innovation Platform’s Partner of the Year Award for 2017 in the category of New IP.

“Our lead customer has a working chip, with embedded FPGA on it. They are in the process of debugging rest of their chip. Overall, we are still in the early stages of market development,” Tate said, explaining that semiconductor companies are understandably risk-averse when it comes to their IP choices.

Asked about the status of its 16nm test chip, Tate said “the silicon is out of the fab. The next step is packaging, then evaluation board assembly.  We should be doing validation testing starting in late September.”

Potential customers are in the process of sending engineers to Flex Logix to look at metrics of the largest 16nm arrays, such as IR drop, vest vectors, switching simulations, and the like. “They making sure we are testing in a thorough fashion. If we screw them over, they’ll tell everybody, so we have got to get it right the first time,” Tate said.