Category Archives: Device Architecture

Microsemi Corporation (Nasdaq: MSCC), a provider of semiconductor solutions differentiated by power, security, reliability and performance, today announced the company’s new Mi-V™ ecosystem with industry leaders, to increase adoption of its RISC-V soft central processing unit (CPU) product family. The announcement comes as the company also introduces Mi-V RV32IMA and additional field programmable gate array (FPGA)-based soft CPU solutions ideally suited for designs utilizing RISC-V open instruction set architectures (ISAs).

“As a leader in RISC-V, we are pleased Microsemi is the first tier one vendor to build out a complete open RISC-V ecosystem, which not only supports our needs, but contributes to the entire development community,” said Jim Aralis, chief technology officer and vice president of advanced development at Microsemi. “Customers can now select RISC-V for their new designs knowing a tier one vendor committed to the success of this technology is providing all the necessary tools to confidently use RISC-V soft CPUs in their products.”

RISC-V, an ISA which is a standard open architecture under the governance of the RISC-V Foundation, offers numerous benefits, including portability as well as enabling the open source community to test and improve cores at a faster pace than closed ISAs. As the RISC-V intellectual property (IP) core is not encrypted, it can be used to ensure trust and certifications not possible with closed architectures. Microsemi’s new Mi-V ecosystem brings together a number of industry leaders involved in the development of RISC-V to leverage their capabilities and streamline RISC-V designs for customers.

“Micrium is pleased to join Microsemi’s Mi-V ecosystem with our highly dependable µC/OS-II real-time kernel, a full-featured embedded operating system,” said Jean Labrosse, co-founder and chief architect at Micrium. “As RISC-V continues to grow in popularity, we look forward to working closely with Microsemi to support accelerated adoption of its RISC-V soft CPU product offerings as well as the entire ecosystem’s RISC-V advancements.”

Microsemi’s Mi-V ecosystem, part of Microsemi’s Accelerate Ecosystem, contains a number of components. Design tools include Microsemi’s SoftConsole Eclipse-based integrated development environment (IDE), the firmware catalog and Libero PolarFire system-on-chip (SoC). Operating systems include Express Logic’s ThreadX, Huawei LiteOS and Micrium µC/OS-II. Boards include the RTG4™ development kit, IGLOO™2 RISC-V board from Future Electronics, PolarFire Evaluation Kit and more. Debug dongles from Microsemi and Olimex, first-stage bootloaders and numerous soft peripherals are also included. Example projects, drivers and firmware are all available on GitHub, the world’s largest repository of open source software.

Deployment of soft CPUs implemented with the R11C-V ISA is automatic and delivered to the user’s desktop via Microsemi’s IP Catalog. No end user license agreements are needed to gain access to the soft CPUs. Using RISC-V soft CPUs within the Mi-V ecosystem is simple, easy and free.

“Express Logic is pleased to be a foundational part of Microsemi’s Mi-V RISC-V ecosystem,” said William E. Lamie, President, Express Logic. “Our X-Ware Internet-of-Things (IoT) platform, including the industry-leading ThreadX RTOS with over 6.2 billion deployments, is the preferred embedded software platform for all designs requiring industrial-grade run-time solutions—making us an ideal fit for this new consortium.”

Offering low power and an open architecture, Microsemi’s PolarFire™, RTG4™, SmartFusion™2 and IGLOO™2 field programmable gate array (FPGA)-based RISC-V soft CPU cores are ideal for developing a wide variety of applications within the aerospace and defense, industrial and security markets. The Mi-V soft CPU cores make them particularly suitable for applications including guided munitions, IoT, secure communications and wireline bridging.

“The open source, royalty-free RISC-V instruction set creates a new business model for CPU designers that is garnering increasing interest and support,” said Linley Gwennap, principal analyst with The Linley Group, which named the RISC-V ISA “Best Technology of 2016” at its annual Analysts’ Choice Awards in January 2017. “By introducing the RV32IM CPU core with support from the Mi-V ecosystem, Microsemi will play an important role in boosting the adoption of RISC-V.”

Through Microsemi’s early involvement in the creation of the RISC-V Foundation, the company has an established leadership role in the emerging standard and ecosystem and is working closely with the nonprofit to ensure the ISA becomes an industry standard for a wide variety of computing devices. Ted Speers, head of product architecture and planning for Microsemi’s Programmable business unit, was appointed to the inaugural board of directors of the RISC-V Foundation in July 2016, and Ted Marena, director of SoC FPGA marketing, was recently sworn in as chair of the RISC-V Marketing Committee after serving as vice-chair since August 2016. Marena will also be the featured speaker at EE World Online’s upcoming webinar titled, “The RISC-V ecosystem is ready for prime time. Get started here!” on Oct. 25, 2017. Attendees can register online to join this event.

The Mi-V Ecosystem began as part of the Microsemi Accelerate Ecosystem, a program designed to reduce time to market for end customers and time to revenue for ecosystem participants. Microsemi’s Accelerate Ecosystem brings together leading silicon, intellectual property (IP), systems, software and design experts to deliver solutions for end customers.

The ConFab, to be held May 20-23 at The Cosmopolitan of Las Vegas, is excited to announce IBM’s Dr. Rama Divakaruni will be the opening keynote for the 2018 conference. Dr. Divakaruni’s presentation is entitled, “How AI is Driving the New Semiconductor Era“. He will address the Artificial Intelligence era demands for dramatic enhancement in computational performance and efficiency of AI workloads, and discuss the needs and changes required in algorithms, systems and chip design as well as in devices and materials.

“Increased use of artificial intelligence will radically change how semiconductors are designed and manufactured, and I’m delighted IBM’s Rama Divakaruni will be sharing his insights at The ConFab in 2018,” said Pete Singer, Editor-in-Chief of Solid State Technology and the conference chair of The ConFab.

Dr. Divakaruni is responsible for IBM Advanced Process Technology Research (which includes EUV technologies and advanced unit process and enablement technologies) and he is the main interface between IBM Semiconductor Research and IBM’s Systems Leadership. Dr. Divakaruni is an IBM Distinguished Engineer and one of IBMs top inventors with over 225 issued US patents.

An impressive background – since 1994, Dr. Divakaruni has been working on advanced semiconductor technologies at IBM. Through 2003, while in DRAM Technology Development, his team introduced the world’s first sub-8F2 vertical transistor DRAM trench technology. The next two years, Dr. Divakaruni worked as the technical lead for the 90nm strained silicon technology which was the world’s first to introduce dual stress liner technology; the technology was the basis of the Nintento Wii, XBOX360 and the PlayStation3 game platforms. After a year serving as project manager for the Unit Process team, he was program manager and technical lead for the development of 45nm industry standard bulk technologies for IBM’s Joint Development Alliance. At 45nm, IBM and its development partners introduced strained silicon technology for low power mobile products thus launching strained silicon across the spectrum of bulk low power and SOI performance CMOS technologies. This technology was the basis for the first Apple I-pad, early Apple I-phones and was the technology that IBM’s partners, including Samsung, used for all their mobile platforms and devices. 

Professor Martijn Kemerink of Linköping University has worked with colleagues in Spain and the Netherlands to develop the first material with conductivity properties that can be switched on and off using ferroelectric polarisation.

The phenomenon can be used for small and flexible digital memories of the future, and for completely new types of solar cells.

In an article published in the prestigious scientific journal Science Advances, the research group shows the phenomenon in action in three specially built molecules, and proposes a model for how it works.

This is the first material with conductivity properties that can be switched on and off using ferroelectric polarization. Credit: Thor Balkhed

This is the first material with conductivity properties that can be switched on and off using ferroelectric polarization. Credit: Thor Balkhed

“I originally had the idea many years ago, and then I just happened to meet Professor David González-Rodríguez, from the Universidad Autónoma de Madrid, who had constructed a molecule of exactly the type we were looking for,” says Martijn Kemerink.

The organic molecules that the researchers have built conduct electricity and contain dipoles. A dipole has one end with a positive charge and one with a negative charge, and changes its orientation (switches) depending on the voltage applied to it. In a thin film of the newly developed molecules, all the dipoles can be caused to switch at exactly the same time, which means that the film changes its polarisation. The property is known as ferroelectricity. In this case, it also leads to a change in the conductivity, from low to high or vice versa. When an electrical field with the opposite polarity is applied, the dipoles again switch direction. The polarisation changes, as does the ability to conduct current.

The molecules designed according to the model developed by the LiU researchers tend to spontaneously place themselves on top of each other to form a stack or a supramolecular wire, with a diameter of just a few nanometres. These wires can subsequently be placed into a matrix in which each junction constitutes one bit of information. This will make it possible in the future to construct extremely small digital memories with very high information density. The synthesis of the new molecules is, however, still too complicated for practical use.

“We have developed a model for how the phenomenon arises in principle, and we have shown experimentally that it works for three different molecules. We now need to continue work to build molecules that can be used in practical applications,” says Professor Martijn Kemerink, from Complex Materials and Devices at Linköping University, and principal author of the article.

IC Insights has raised its IC market growth rate forecast for 2017 to 22%, up six percentage points from the 16% increase shown in its Mid-Year Update.  The IC unit volume shipment growth rate forecast has also been increased from 11% depicted in the Mid-Year Update to 14% currently.  As shown below, a large portion of the market forecast revision is due to the surging DRAM and NAND flash markets.

In addition to increasing the IC market forecast for this year, IC Insights has also increased its forecast for the O-S-D (optoelectronics, sensor/actuator, and discretes) market.  In total, the semiconductor industry is now expected to register a 20% increase this year, up five percentage points from the 15% growth rate forecast in the Mid-Year Update.

For 2017, IC Insights expects a whopping 77% increase in the DRAM ASP, which is forecast to propel the DRAM market to 74% growth this year, the largest growth rate since the 78% DRAM market increase in 1994.  After including a 44% expected surge in the NAND flash market in 2017, including a 38% increase in NAND flash ASP this year, the total memory market is forecast to jump by 58% in 2017 with another 11% increase forecast for 2018.

At $72.0 billion, the DRAM market is forecast to be by far the largest single product category in the semiconductor industry in 2017, exceeding the expected NAND flash market ($49.8 billion) by $22.2 billion this year. As shown in Figure 1, the DRAM and NAND flash segments are forecast to have a strong positive impact of 13 percentage points on total IC market growth this year. Excluding these memory segments, the IC industry is forecast to grow by 9%, less than half of the current total IC market growth rate forecast of 22% when including these memory markets.

Figure 1

Figure 1

IC Insights is set to release its October Update to The McClean Report.  The 30-page Update includes a detailed analysis of IC Insights’ revised forecasts for the IC, O-S-D, and total semiconductor markets through 2021.

The 63rd annual IEEE International Electron Devices Meeting (IEDM), to be held December 2-6, 2017 at the Hilton San Francisco Union Square hotel, may go down as one of the most memorable editions for the sheer variety and depth of its talks, sessions, courses and events.

Among the most-anticipated talks are presentations by Intel and Globalfoundries, which will each detail their forthcoming competing FinFET transistor technology platforms in a session on Wednesday morning. FinFET transistors are a major driver of the continuing progress of the electronics industry, and these platforms are as important for their commercial potential as they are for their technical innovations.*

Each year at the IEDM, the world’s best technologists in micro/nano/bioelectronics converge to participate in a technical program consisting of more than 220 presentations, along with other events.

“Those who attend IEDM 2017 will find much that is familiar, beginning with a technical program describing breakthroughs in areas ranging from mainstream CMOS technology to innovative nanoelectronics to medical devices. The Sunday Short Courses are also a perennial favorite because they are not only comprehensive but are also taught by accomplished world experts,” said Dr. Barbara De Salvo, Scientific Director at Leti. “But we have added some new features this year. One is a fourth Plenary session, on Wednesday morning, featuring Nobel winner Hiroshi Amano. Another is a revamped Tuesday evening panel. Not only will it focus on a topic of great interest to many people, it is designed to be more open and less formal.”

Other features of the IEDM 2017 include:

  • Focus Sessions on the following topics: 3D Integration and Packaging; Modeling Challenges for Neuromorphic Computing; Nanosensors for Disease Diagnostics; and Silicon Photonics: Current Status and Perspectives.
  • A vendor exhibition will be held, based on the success of last year’s event at the IEDM.
  • The IEEE Magnetics Society will again host a joint poster session on MRAM (magnetic RAM) in the exhibit area. New for this year, though, is that the Society will also hold its annual MRAM Global Innovation Forum on Thursday, Dec. 7 at the same hotel, enabling IEDM attendees to participate. (Refer to the IEEE Magnetics Society website.) The forum consists of invited talks by leading experts and a panel discussion.

Here are details of some of the events that will take place at this year’s IEDM:

90-Minute Tutorials – Saturday, Dec. 2
These tutorials on emerging technologies will be presented by leading technical experts in each area, with the goal of bridging the gap between textbook-level knowledge and cutting-edge current research.

  • The Evolution of Logic Transistors Toward Low Power and High Performance IoT Applications, Dr. Dae Won Ha, Samsung Electronics
  • Negative Capacitance Transistors, Prof. Sayeef Salahuddin, UC Berkeley
  • Fundamental, Thermal, and Energy Limits of PCM and ReRAM, Prof. Eric Pop, Stanford University
  • Hardware Opportunities in Cognitive Computing: Near- and Far-Term, Dr. Geoffrey Burr, Principal Research Staff Member, IBM Research-Almaden
  • 2.5D Interposers and High-Density Fanout Packaging as Enablers for Future Systems Integration, Dr. Venkatesh Sundaram, Associate Director, Georgia Tech 3D Systems Packaging Research Center
  • Silicon Photonics for Next-Generation Optical Interconnects, Dr. Joris Van Campenhout, Program Director Optical I/O, Imec

Short Courses – Sunday, Dec. 3
The day-long Short Courses provide the opportunity to learn about important developments in key areas, and they enable attendees to network with the industry’s leading technologists.

Boosting Performance, Ensuring Reliability, Managing Variability in Sub-5nm CMOS, organized by Sandy Liao of Intel, will feature the following sections:

  • Transistor Performance Elements for 5nm Node and Beyond, Gen Tsutsui, IBM
  • Multi-Vt Engineering and Gate Performance Control for Advanced FinFET Architecture, Steve CH Hung, Applied Materials
  • Sub-5nm Interconnect Trends and Opportunities, Zsolt Tokei, Imec
  • Transistor Reliability: Physics, Current Status, and Future Considerations, Stephen M. Ramey, Intel
  • Back End Reliability Scaling Challenges, Variation Management, and Performance Boosters for sub-5nm CMOS,Cathyrn Christiansen, Globalfoundries
  • Design-Technology Co-Optimization for Beyond 5nm Node, Andy Wei, TechInsights

Merged Memory-Logic Technologies and Their Applications, organized by Kevin Zhang of TSMC, will feature the following sections:

  • Embedded Non Volatile Memory for Automotive Applications, Alfonso Maurelli, STMicroelectronics
  • 3D ReRAM: Crosspoint Memory Technologies, Nirmal Ramaswamy, Micron
  • Ferroelectric Memory in CMOS Processes, Thomas Mikolajick, Namlab
  • Embedded Memories Technology Scaling & STT-MRAM for IoT & Automotive, Danny P. Shum, Globalfoundries
  • Embedded Memories for Energy-Efficient Computing, Jonathan Chang, TSMC
  • Abundant-Data Computing: The N3XT 1,000X, Subhasish Mitra, Stanford University

Plenary Presentations – Monday, Dec. 4

  • Driving the Future of High-Performance Computing, Lisa Su, President & CEO, AMD
  • Energy-Efficient Computing and Sensing: From Silicon to the Cloud, Adrian Ionescu, Professor, EPFL
  • System Scaling Innovation for Intelligent Ubiquitous Computing, Jack Sun, VP of R&D, TSMC

Plenary Presentation – Wednesday, Dec. 6

  • Development of a Sustainable Smart Society by Transformative Electronics, Hiroshi Amano, Professor, Nagoya University. Dr. Amano received the 2014 Nobel Prize in Physics along with Isamu Akasaki and Shuji Nakamura for the invention of efficient blue LEDs, which sparked a revolution in innovative, energy-saving lighting. His talk will be preceded by the Focus Session on silicon photonics.

Evening Panel Session – Tuesday evening, Dec. 5

  • Where will the Next Intel be Headquartered?  Moderator: Prof. Philip Wong, Stanford

Entrepreneurs Lunch
Jointly sponsored by IEDM and IEEE EDS Women in Engineering, this year’s Entrepreneurs Lunch will feature Courtney Gras, Executive Director for Launch League, a local nonprofit focused on developing a strong startup ecosystem in Ohio. The moderator will be Prof. Leda Lunardi from North Carolina State University. Gras is an engineer by training and an entrepreneur by nature. After leaving her job as a NASA power systems engineer to work for on own startup company, she discovered a passion for building startup communities and helping technology-focused companies meet their goals. Named to the Forbes ’30 Under 30′ list in 2016, among many other recognitions and awards, Gras enjoys sharing her stories of founding a cleantech company with young entrepreneurs. She speaks on entrepreneurship, women in technology and clean energy at venues such as TEDx Budapest, the Pioneers Festival, and the IEEE WIE International Women’s Leadership Conference.

 

SEMI recently completed its annual silicon shipment forecast for the semiconductor industry. This SEMI forecast provides an outlook for the demand in silicon units for the period 2017–2019. The SEMI forecast shows polished and epitaxial silicon shipments totaling 11,448 million square inches in 2017; 11,814 million square inches in 2018; and 12,235 million square inches in 2019 (refer to table below). Total wafer shipments this year are expected to exceed the market high set in 2016 and are forecast to continue shipping at record levels in 2018 and 2019.

“Silicon shipment volumes are expected to ship at historic highs for this year and into 2019,” said Dan Tracy, senior director of Industry Research & Statistics at SEMI. “The expectation is for steady annual growth due to the proliferation of connected devices required for automotive, medical, wearables, and high-performance computing applications.”

2017 Silicon Shipment Forecast
(Millions of Square Inches, MSI)

Actual
Forecast
2015
2016
2017
2018
2019
MSI
10,269
10,577
11,448
11,814
12,235
Annual Growth
4.5%
3.0%
8.2%
3.2%
3.6%

Total Electronic Grade Silicon Slices* – Does not Include Non-Polished Wafers
Source: SEMI (www.semi.org), October 2017
*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

On 14-17 November in Munich, SEMICON Europa will co-locate with productronica for the first time, for a focus on innovation and the future of the electronics manufacturing supply chain. Gathering key stakeholders from across the electronics manufacturing supply chain, the extensive range and depth, programs and networking events make the platform a necessity for players across the European electronics industry. SEMICON Europa will take place at Messe München Hall B1.

An Opening Ceremony will include a welcome speech by Ajit Manocha, president and CEO of SEMI, followed by Laith Altimime, president, SEMI Europe, plus four keynotes:

  • Bosch Sensortec: Stefan Finkbeiner, CEO, on how environmental sensing can contribute to a better quality of life in the context of the IoT
  • Rinspeed Inc.: Frank M. Rinderknecht, founder and CEO, on how to create innovative technologies, materials and mobility means of tomorrow
  • SOITEC: Carlos Mazure, CTO, executive VP, on contributions and benefits of engineered substrates solutions and thin-layer transfer technologies, focusing on applications in the smart space
  • TSMC Europe: Maria Marced, president, on opportunities for new business models to apply in the Smart City

“We are at the brink of a new wave of innovation ─ called the “Fourth Industrial Revolution” or “Smart Manufacturing.” It’s driven by connected devices and smart applications known as the IoT. This presents many opportunities for closer collaborations at global level, connecting key players, key ecosystems and building on the strengths of players in the value chain,” said Laith Altimime, president of SEMI Europe.

New programs on Flexible Electronics, Materials, and Automotive expand SEMICON Europa’s impact:

Returning programs include:

Register for programs before 12 November for a discount: http://www.semiconeuropa.org/register

SEMICON Europa offers free programs available on the exhibition show floor, including the TechARENA sessions ─ from MedTech to Lithography, Smart Manufacturing and Photonics, and many other topics.

For the fourth time at SEMICON Europa, INNOVATION VILLAGE will bring early-stage technology companies, the semiconductor industry’s top strategic investors, and leading technology partners together. This year sponsors include the City of Dresden and Volkswagen.

More than ever, there are unique opportunities to network with peers and connect with a large number of stakeholders at SEMICON Europa as attendees gather at the SEMICON CXO Luncheon, SEMI Member Breakfast, and SEMI Networking Night.

Connect! Register here and stay in touch via Twitter at http://www.twitter.com (use #SEMICONEuropa)

China IC industry outlook


October 17, 2017

SEMI, the global industry association and provider of independent electronics market research, today announced its new China IC Industry Outlook Report, a comprehensive report for the electronics manufacturing supply chain. With an increasing presence in the global semiconductor manufacturing supply chain, the market opportunities in China are expanding dramatically.

China is the largest consumer of semiconductors in the world, but it currently relies mainly on semiconductor imports to drive its growth. Policies and investment funds are now in place to further advance the progress of indigenous suppliers in China throughout the entire semiconductor supply chain. This shift in policy and related initiatives have created widespread interest in the challenges and opportunities in China.

With at least 15 new fab projects underway or announced in China since 2017, spending on semiconductor fab equipment is forecast to surge to more than $12 billion, annually, by 2018. As a result, China is projected to be the top spending region in fab equipment by 2019, and is likely to approach record all-time levels for annual spending for a single region.

Figure 1

Figure 1

This report covers the full spectrum of the China IC industry within the context of the global semiconductor industry. With more than 60 charts, data tables, and industry maps from SEMI sources, the report reveals the history and the latest industry developments in China across vast geographical areas ranging from coastline cities to the less developed though emerging mid-western regions.

The China IC industry ecosystem outlook covers central and local government policies, public and private funding, the industry value chain from design to manufacturing and equipment to materials suppliers. Key players in each industry sector are highlighted and discussed, along with insights into China domestic companies with respect to their international peers, and potential supply implications from local equipment and material suppliers. The report specifically details semiconductor fab investment in China, as well as the supply chain for domestic equipment and material suppliers.

Figure 2

Figure 2

Semiconductor Manufacturing International Corporation (“SMIC”; NYSE: SMI; SEHK: 0981.HK), the largest and most advanced foundry in mainland China, today announced the appointment of Dr. Haijun Zhao and Dr. Liang Mong Song as SMIC Co-CEO and Executive Director.

Dr. Zhao, age 54, was appointed as the Chief Executive Officer of the Company on May 10, 2017. Dr. Zhao joined the Company in October 2010 and was appointed as Chief Operating Officer and Executive Vice President in April 2013. In July 2013, Dr. Zhao was appointed as General Manager of Semiconductor Manufacturing North China (Beijing) Corporation, a joint venture company established in Beijing and a subsidiary of the Company. Dr. Zhao received his bachelor of science and doctor of philosophy degrees in electronic engineering from Tsinghua University (Beijing) and a master degree in business administration from the University of Chicago. He has 25 years of experience in semiconductor operations and technology development.

Dr. Liang Mong Song, age 65, graduated with a doctor of philosophy degree in electrical engineering from the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. Dr. Liang has been engaged in the semiconductor industry for over 33 years, and was involved in memory and advanced logic process technology development. He owns over 450 patents and has published over 350 technical papers. He is a Fellow of Institute of Electrical and Electronic Engineers (IEEE).

Dr. Zixue Zhou, Chairman of SMIC, commented, “I am very pleased that Dr. Haijun Zhao and Dr. Liang Mong Song have joined the board of directors of SMIC as Executive Directors. I also warmly welcome Dr. Liang Mong Song to join SMIC together with Dr. Haijun Zhao to serve as Co-CEO. For decades Dr. Liang has focused on integrated circuit (“IC”) technology research and development and team management, with excellence and successful experience in advanced IC process development and management. His accession will further enhance SMIC’s ability to develop process technology and narrow the advanced technology gap between SMIC and its international peers; and at the same time, his efforts will further enhance SMIC’s ability to serve its customers and improve the metrics of SMIC’s existing technology. In addition, he brings corporate culture of top tier companies, which will enhance the company’s corporate culture to world class standards. It is believed with Dr. Haijun Zho and Dr. Liang Mong Song’s joint efforts SMIC will be led to a new height and make contributions to the development of IC industry.”

Dr. Haijun Zhao, Co-CEO of SMIC remarked, “I am pleased to join the board of directors of SMIC as Executive Director, and warmly welcome Dr. Liang Mong Song to join SMIC. Dr. Liang’s great achievements in the semiconductor industry are obvious to all. His accession will strengthen our management team, and as Co-CEO I am looking forward to working together with Dr. Liang. Together with our management and staff we will strive to make SMIC a global first-class IC enterprise.”

Dr. Liang Mong Song, Co-CEO of SMIC said, “I am greatly honored to take on the position of Co-CEO and Executive Director of SMIC, which to me, is not merely an opportunity, but also a challenge. SMIC’s rapid developments in recent years have been notable in the industry, and I am looking forward to working closely with the board of directors, Dr. Haijun Zhao and the management team to continuously improve the competitiveness of SMIC in the area of international IC manufacturing.”

sureCore Ltd. today announced it has joined the GLOBALFOUNDRIES (GF) FDXcelerator™ Partner Program and will make both their Low Power “PowerMiser” and Ultra Low Voltage “EverOn” SRAM offerings available on GF’s 22nm FD-SOI (22FDX®) process technology. PowerMiser delivers dynamic and static power savings exceeding 50 percent and 20 percent respectively. EverOn is the first commercially available SRAM to enable robust and reliable operation at near threshold voltages delivering hitherto unprecedented power savings. sureCore SRAMs are built from standard foundry bit cells and need no process modifications

“GF’s 22FDX is a logical next step for developers who are currently in 28nm bulk processes” said CEO Paul Wells. “We believe the 22FDX technology offers many technical and commercial benefits when compared to standard bulk CMOS technology. Combined with sureCore’s low power SRAM technology it will provide a best-in-class platform for the development of low power devices. In particular the EverOn SRAM will enable developers of IoT and Wearables the capability to deliver true near threshold operation by voltage scaling in tandem with the logic. Operation at as low as 550mV, the bit cell retention voltage, is a real game changer.”

“Our collaboration with sureCore enables customers to fully leverage the benefits of GF’s 22FDX platform and meet the ultra-low-power requirements of next generation connected devices,” said Alain Mutricy, senior vice president of product management at GF.

Key to the break-through is sureCore’s patented “smart-Assist” technology that allows robust operation down to the bit cell retention voltage. Other architectural improvements include enhanced sleep modes as well as array subdivision into four banks, each being independently controllable to be active, in retentive sleep or powered off thereby facilitating even greater power efficiency.

The challenges of near-threshold design drove sureCore to implement a world class verification and characterisation regime exploiting leading edge EDA tooling as well as extensive silicon validation using targeted process skews. Successful completion of industry standard High Temperature Operating Life (HTOL) tests has confirmed the inherent robustness and reliability of the EverOn SRAM.

“Low power design is placing new demands on SoC developers and, compared to the restrictions imposed by standard memory, our EverOn SRAM enables a new dimension in low power capability,” said Eric Gunn, sureCore’s COO.