Category Archives: Device Architecture

Over the past half-century, scientists have shaved silicon films down to just a wisp of atoms in pursuit of smaller, faster electronics. For the next set of breakthroughs, though, they’ll need novel ways to build even tinier and more powerful devices.

A study led by UChicago researchers, published Sept. 20 in Nature, describes an innovative method to make stacks of semiconductors just a few atoms thick. The technique offers scientists and engineers a simple, cost-effective method to make thin, uniform layers of these materials, which could expand capabilities for devices from solar cells to cell phones.

Stacking thin layers of materials offers a range of possibilities for making electronic devices with unique properties. But manufacturing such films is a delicate process, with little room for error.

“The scale of the problem we’re looking at is, imagine trying to lay down a flat sheet of plastic wrap the size of Chicago without getting any air bubbles in it,” said Jiwoong Park, a UChicago professor with the Department of Chemistry, the Institute for Molecular Engineering and the James Franck Institute, who led the study. “When the material itself is just atoms thick, every little stray atom is a problem.”

Today, these layers are “grown” instead of stacking them on top of one another. But that means the bottom layers have to be subjected to harsh growth conditions such as high temperatures while the new ones are added — a process that limits the materials with which to make them.

Park’s team instead made the films individually. Then they put them into a vacuum, peeled them off and stuck them to one another, like Post-It notes. This allowed the scientists to make films that were connected with weak bonds instead of stronger covalent bonds–interfering less with the perfect surfaces between the layers.

“The films, vertically controlled at the atomic-level, are exceptionally high-quality over entire wafers,” said Kibum Kang, a postdoctoral associate who was the first author of the study.

Kan-Heng Lee, a graduate student and co-first author of the study, then tested the films’ electrical properties by making them into devices and showed that their functions can be designed on the atomic scale, which could allow them to serve as the essential ingredient for future computer chips.

The method opens up a myriad of possibilities for such films. They can be made on top of water or plastics; they can be made to detach by dipping them into water; and they can be carved or patterned with an ion beam. Researchers are exploring the full range of what can be done with the method, which they said is simple and cost-effective.

“We expect this new method to accelerate the discovery of novel materials, as well as enabling large-scale manufacturing,” Park said.

A research group consisting of scientists from Tomsk Polytechnic University, Germany and Venezuela proved vulnerability of a two-dimensional semiconductor gallium selenide in air. This discovery will allow manufacturing superconducting nanoelectronics based on gallium selenide, which has never been previously achieved by any research team in the world.

The study was published in Semiconductor Science and Technology.

One of the promising areas of modern materials science is the study of two-dimensional (2D) materials, i.e. thin films consisting of one or several atomic layers. 2D materials due to their electrical superconductivity and strength could be a basis for modern nanoelectronics. Optic applications in nanoelectronics require advanced materials capable of ‘generating’ great electron fluxes upon light irradiation. Gallium selenide (GaSe) is one of the 2D semiconductors that can cope with this problem most efficiently.

‘Some research teams abroad tried to create electronic devices based on GaSe. However, despite extensive theoretical studies of this material, which were published in major scientific journals, the stability of the material in real devices remained unclear,’ says Prof. Raul Rodriguez, the Department of Lasers and Lighting Engineering.

The research team revealed the reasons behind this. They studied GaSe by means of Raman spectroscopy and x-ray photoelectron spectroscopy that allowed proving the existence of chemical bonds between gallium and oxygen. Photoluminescence in oxidized substance is absent that also proves the formation of oxides. It means that the scientists revealed that GaSe oxidizes quickly in air and loses its electrical conductivity necessary for creating nanoeletronic devices.

‘GaSe monolayers become oxidized almost immediately after being exposed to air. Further research of GASe stability in air will allow making proposals how to protect it and maintain its optoelectronic properties,’ emphasize the authors.

According to Prof. Rodriguez, for GaSe not to lose its unique properties it should be placed in a vacuum or inert environment. For example, it can be applied in encapsulated devices that are vacuum-manufactured and then covered with a protective layer eliminating air penetration.

This method can be used to produce next generation optoelectronics, detectors, light sources and solar batteries. Such devices of ultra-small sizes will have very high quantum efficiency, i.e. they will be able to generate large electron fluxes under small external exposure.

SEMICON Europa 2017 will take place in Munich for the first time, co-located with productronica (14-17 November in Munich, Germany). SEMICON Europa will showcase the critical issues shaping the entire electronics manufacturing supply chain. Fourexecutive keynotes will share their thought leadership on current opportunities for Europe: Maria Marced, president, TSMC Europe; Stefan Finkbeiner, CEO, Bosch Sensortec; and Frank M. Rinderknecht, founder and CEO of Rinspeed Inc.

“Innovations in semiconductor manufacturing are at the heart of the value chain driving innovations enabling key future growth drivers in Mobile, Automotive, Medical, passive and intelligent computing as well as AR and VR,” stated Laith Altimime, president, SEMI Europe. SEMICON Europa programs, sessions, and speakers will illuminate this year’s theme “Empowering Innovation and Shaping the Value Chain.”  Highlights of SEMICON Europa include:

  • Fab Management Forum: Quality Challenges – Solutions for Tomorrow ─ Topics include:Future of digital vehicles and requirements for quality and availability of semiconductors with Daimler AG, an analysis of Human failure and mindset change by European School of Management and Technology (ESMT) Berlin, and how innovative sensor and analytics solutions enable new applications in the fab of tomorrow by KINEXON GmbH.
  • Advanced Packaging Conference: Electronics Packaging and Test for Future Mobility ─With Yole Développement on the dynamics of the advanced packaging ecosystem, Robert Bosch GmbH on automotive, Infineon Technologies on packaging for automotive ─ challenges and solutions, RoodMicrotec GmbH on wafer and final test in the new era of electronics, and STMicroelectronics on packaging challenges for robust miniaturization.
  •  Power Electronics Conference: From Materials to Systems,The Latest Innovations ─Covering power electronics applications for Automotive by Fraunhofer Institute for Integrated Systems and Device Technology IISB, a forecast of the next five years to reveal how technology development will shape the power electronics market by Yole Développement, and  Cambridge University on Silicon and Wide bandgap devices in power electronics.
  • New! Materials Conference: Connected World ─ New Material Challenges and Solutions ─Includes a keynote by Christophe Maleville, SOITEC, on how to better optimize performance, power budget and cost to meet applications requirements; plus presentations from Volkswagen AG on the need for new industry alliances in automotive, FUJIFILM on maximum utilization of chemically amplified resist, and Dow Chemical on the information age and connectivity enabled by advanced electronic materials. The free Webinar “Connected World: New Material Challenges and Solutions – Market Update and Outlook“ is planned on 27 September.
  • New! European Connect2Car Forum ─ A new Forum in collaboration with SAE International. Insights for automotive OEM and supplier executives, consumer electronics leaders, mobile application developers, and aftermarket entrepreneurs focusing on enhancing the driver experience and accelerating the deployment of connected and autonomous vehicle technologies.
  • New! 2017FLEX Europe “Be Flexible” ─ New collaboration between FLEX and Fraunhofer EMFT. Insights on innovative solutions for flexible and stretchable systems by Würth Elektronik GmbH,  technology and applications of chip-film patch for hybrid systems in foil by IMS CHIPS, new capabilities and applications of flexible components by E Ink Corporation, and insight on how potentials of System-in-Package technologies will affect the future by Bosch.

SEMI and Messe München Joint Press Conference will take place on 14 November at 11:00-12:00, at Messe München Press Conference Center.

IC Insights has just released its September Update to The McClean Report.  This 32-page Update includes a detailed look at the pure-play foundry market and an analysis of the historical DRAM price-per-bit trends.  Shown below is an excerpt from the Update that examines the IC technology trends in the pure-play foundry market.

In 2017, the 7% increase in the total pure-play foundry market is forecast to be almost entirely due to an 18% jump in <40nm feature size device sales (Figure 1).

Figure 1

Figure 1

Although expected to represent 60% of total pure-play foundry sales in 2017, the ≥40nm pure-play IC foundry market is forecast to be up only $0.2 billion this year.  In contrast, the 2017 leading-edge <40nm pure-play foundry market is expected to surge by a hefty $3.3 billion.  Moreover, not only is almost all of the pure-play foundry growth forecast to come from leading-edge production in 2017, most of the profits that are expected to be realized in the foundry market also forecast to come from the finer feature sizes as well.

TSMC is by far the technology leader among the major pure-play foundries.  In 2017, 58% of TSMC’s revenue is expected to come from <40nm processing, more than double percentage at GlobalFoundries and more than triple the share at UMC.  In total, TSMC is forecast to hold an 86% share of the total <40nm pure-play foundry market this year.

Illustrating how dominant TSMC is in the leading-edge pure-play foundry market, the company is expected to have almost 7x the dollar volume sales at <40nm as compared to GlobalFoundries, UMC, and SMIC combined this year ($18.5 billion for TSMC and $2.7 billion for combined total of GlobalFoundries, UMC, and SMIC).  In fact, 10% of TSMC’s total sales this year are forecast to be for its 10nm process technology.

In contrast to TSMC, SMIC only entered initial production of its 28nm technology in 4Q15, more than three years after TSMC first put its 28nm process into production.  In fact, only 7% of SMIC’s 2017 sales are expected to be from devices having 28nm feature sizes (the company does not offer a finer feature size at this time), which is the primary reason its revenue per wafer is so much less compared to TSMC.

Semiconductor Research Corporation (SRC), today announced that Samsung Electronics Company Ltd. (Samsung), one of the world’s largest chipmakers, has signed an agreement to join SRC’s research consortium. Samsung will participate in two SRC platforms – the New Science Team (NST) project and the Global Research Collaboration (GRC) program.

The NST project, a 5-year, $300M+ initiative commences in January 2018. NST consists of two complementary research programs: JUMP (Joint University Microelectronics Program) and nCORE (nanoelectronics Computing Research), supporting long-term research focused on high- performance, energy-efficient microelectronics for communications, computing and storage needs. Within the GRC program, comprised of nine design and process technology research disciplines, Samsung will participate in the Packaging and Logic & Memory Devices programs.

“It is an exciting time at SRC with the addition of Samsung to our premier group of semiconductor design, manufacturing, and advanced technology companies. SRC welcomes Samsung as we continue to bring together the world’s most brilliant minds to turn theories into reality,” said Ken Hansen, President and CEO of Semiconductor Research Corporation. “We now have the most innovative semiconductor companies collaborating to advance research for next-generation technology and to continue the promise of Moore’s Law economics, bringing increased performance and new product features to the consumer.”

“Collaborative research has been a key element of Samsung’s global strategy,” said Dr. HK Kang, Executive Vice President of Semiconductor Research and Development Center, Samsung Electronics. “The roadmap to future discoveries in technology is deeply rooted in the research coming from industry-sponsored university programs such as NST and GRC. We look forward to working with the SRC team to spark meaningful advancements in semiconductor technology as we explore future innovation.”

With the addition of Samsung, 7 of the top 10 global semiconductor companies are now members of SRC. Samsung represents the fifth non-U.S. headquartered company to join SRC within the last 18+ months.

Intel Corporation today announced that Andrew Wilson, CEO of Electronic Arts Inc., has been elected to Intel’s board of directors. Wilson’s election brings Intel’s board membership to 12.

“Andrew understands first-hand how technology and data create opportunity with his transformation of EA from offline packaged goods to a leader in online digital services,” said Intel Chairman Andy Bryant. “In addition to his experience leading and growing a global, technology-driven company, Andrew possesses a combination of creativity and business acumen that will further strengthen Intel’s board.”

Wilson, 43, joined Electronic Arts (“EA”) in May 2000, and has served as the company’s chief executive officer and a director of EA since September 2013. During his tenure as CEO, EA has launched groundbreaking new games and services, reached record player engagement levels across its global franchises, and transformed into one of the world’s leading digital entertainment companies. Prior to his appointment as CEO, Wilson held several leadership positions at EA, including executive vice president of EA SPORTS. He also serves as chairman of the board for the World Surf League.

GLOBALFOUNDRIES today announced the availability of a new set of enhanced RF SOI process design kits (PDKs) to help designers improve their designs of RF switches and deliver differentiated RF front-end solutions for a wide range of markets including front-end modules for mobile devices, mmWave, 5G and other high-frequency applications.

GF’s advanced RF technology platform, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications. Designed for use with Coupling Wave Solutions’ (CWS) simulation tool, SiPEX™, GF’s 7SW SOI PDK allows designers to integrate RF switches with other critical RF blocks that are essential to the design of complex electronic systems for future RF communication chips. Specifically, this new capability allows designers to improve RF simulation output by simulating a highly-resistive substrate parasitic effect across their entire design.

“GF leads the industry in RFSOI technology, and we are committed to providing our customers with design productivity solutions for our RF processes,” said Bami Bastani, senior vice president of RF at GF. “CWS’ SiPEX™ tool provides our customers with best-in-class correlation between simulated results and real world measurements, further optimizing the design layout to achieve efficiency and deliver differentiated RF front-end solutions.”

“This is great news for the RF design community,” said Brieuc Turluche, chairman of the board of directors and chief executive officer of CWS. “The integration of SiPEX into GF’s RF SOI PDKs is a major milestone to achieve first-time correct complex and optimized RF SOI designs for high-performing cellular, IoT, 5G and Wi-Fi communication chips.”

GF’s RF SOI technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. CWS’ SiPEX accelerates the design of RF SOI switches by improving linearity simulation accuracy. It can also be effective in the design of low-noise amplifiers (LNA) and power amplifiers (PA), enabling designers to reduce their size to lower costs.

SiPEX™ is available in the current release of GF’s 7SW SOI PDK. For more information on the company’s RF SOI solutions, contact your GF sales representative or go to www.globalfoundries.com.

Modern life will be almost unthinkable without transistors. They are the ubiquitous building blocks of all electronic devices: each computer chip contains billions of them. However, as the chips become smaller and smaller, the current 3D field-electronic transistors (FETs) are reaching their efficiency limit. A research team at the Center for Artificial Low Dimensional Electronic Systems, within the Institute for Basic Science (IBS), has developed the first 2D electronic circuit (FET) made of a single material. Published on Nature Nanotechnology, this study shows a new method to make metal and semiconductor from the same material in order to manifacture 2D FETs.

In simple terms, FETs can be thought as high-speed switches, comprised of two metal electrodes and a semiconducting channel in between. Electrons (or holes) move from the source electrode to the drain electrode, flowing through the channel. While 3D FETs have been scaled down to nanoscale dimensions successfully, their physical limitations are starting to emerge. Short semiconductor channel lengths lead to a decrease in performance: some electrons (or holes) are able to flow between the electrodes even when they should not, causing heat and efficiency reduction. To overcome this performance degradation, transistor channels have to be made with nanometer-scale thin materials. However, even thin 3D materials are not good enough, as unpaired electrons, part of the so-called “dangling bonds” at the surface interfere with the flowing electrons, leading to scattering.

Passing from thin 3D FETs to 2D FETs can overcome these problems and bring in new attractive properties. “FETs made from 2D semiconductors are free from short-channel effects because all electrons are confined in naturally atomically thin channels, free of dangling bonds at the surface,” explains Ji Ho Sung, first author of the study. Moreover, single- and few-layer form of layered 2D materials have a wide range of electrical and tunable optical properties, atomic-scale thickness, mechanical flexibility and large bandgaps (1~2 eV).

The major issue for 2D FET transistors is the existence of a large contact resistance at the interface between the 2D semiconductor and any bulk metal. To address this, the team devised a new technique to produce 2D transistors with semiconductor and metal made of the same chemical compound, molybdenum telluride (MoTe2). It is a polymorphic material, meaning that it can be used both as metal and as semiconductor. Contact resistance at the interface between the semiconductor and metallic MoTe2 is shown to be very low. Barrier height was lowered by a factor of 7, from 150meV to 22meV.

IBS scientists used the chemical vapor deposition (CVD) technique to build high quality metallic or semiconducting MoTe2 crystals. The polymorphism is controlled by the temperature inside a hot-walled quartz-tube furnace filled with NaCl vapor: 710°C to obtain metal and 670°C for a semiconductor.

The scientists also manufactured larger scale structures using stripes of tungsten diselenide (WSe2) alternated with tungsten ditelluride (WTe2). They first created a thin layer of semiconducting WSe2 with chemical vapor deposition, then scraped out some stripes and grew metallic WTe2 on its place.

It is anticipated that in the future, it would be possible to realize an even smaller contact resistance, reaching the theoretical quantum limit, which is regarded as a major issue in the study of 2D materials, including graphene and other transition metal dichalcogenide materials.

The International Microelectronics And Packaging Society (IMAPS) will celebrate the 50th anniversary of its flagship technical conference – the IMAPS Symposium – from October 9 – 12, 2017, as microelectronics engineers and scientists gather at the Raleigh Convention Center near Research Triangle Park, North Carolina, USA to take part in the electronics industry’s largest technical conference dedicated to advanced microelectronics packaging technology. Researchers and exhibitors will showcase their work during a comprehensive conference program of technical papers, panels, special sessions, short courses/tutorials, and an exhibition that will spotlight premier work in the fields of microelectronics, semiconductor packaging and circuit design.

The 50th International Symposium on Microelectronics is an international technology forum for the presentation of applied research on microelectronics, consisting of more than 180 papers presented by researchers from corporations, universities and government labs worldwide, with five technical tracks: Chip Packaging Interactions; High Performance, Reliability, & Security; Advanced Packaging & Enabling Technologies; Advanced Packaging & System Integration; and Advanced Materials & Processes.

Keynote Presentations Lead Off the IMAPS Technical Program on Tuesday, October 10
Four keynote addresses from leading industry experts include:

“Packaging Challenges for the Next Generation of Mobile Devices,” by Ahmer Syed, Senior director of package engineering, Qualcomm Technologies

“Packaging without the Package – A More Holistic Moore’s Law,” by Subramanian (Subu) S. Iyer, distinguished chancellor’s professor in the Charles P. Reames Endowed Chair of the Electrical Engineering Department at the University of California at Los Angeles (UCLA) and Director of the Center for Heterogeneous Integration and Performance Scaling (CHIPS)

“Electronics Outside the Box: Building a Manufacturing Ecosystem for Flexible Hybrid Electronics,” by Benjamin Leever, senior materials engineer, Air Force Research Laboratory (AFRL) Soft Matter Materials Branch

“Transforming Electronic Interconnect,” by Tim Olson, founder & CTO, Deca Technologies

International Panel Session & Wine Reception on Wednesday, October 11
A panel session on “Global Perspectives on Packaging Requirements & Trends Towards 2025” will be moderated by Jan Vardaman, TechSearch International and Gabriel Pares, CEA-Leti. Panelist will include representatives from Asia (Yasumitsu Orii, NAGASE Group and Ton Schless, SIBCO), Europe (Steffen Kroehnert, Nanium and Eric Bridot, SAFRAN), and North America (David Jandzinski, Qorvo). The 90-minute panel session includes a wine reception.

Diversity Roundtable & Networking Discussions on Monday, October 9
Following the opening reception, IMAPS leaders will conduct a series of roundtable discussions designed to inspire conversations about overcoming diversity barriers, the strengths inherent in a diverse workforce, identifying and collaborating with a mentor, and more.

Posters & Pizza Session on Thursday, October 12
One of the fastest-growing segments of the IMAPS conference is the popular “Posters & Pizza” session held outside the exhibit hall, giving attendees the opportunity to interact one-on-one with presenters in a more informal setting.

Professional Development Courses (Short Courses & Tutorials) on Monday, October 9
Preceding the IMAPS Symposium technical program is a full day of professional development opportunities, presented as a series of 2-hour sessions in four tracks: Intro to Microelectronics Packaging; Next Generation Packaging Challenges; Baseline & Emerging Technologies; and Reliability. These short courses represent a unique opportunity, only available through IMAPS, for participants to personally interact with the instructors, and with each other in small groups from 10 – 30 people, led by industry experts in the field with ample time for questions and networking.

Student Opportunities at IMAPS
As part of its ongoing mission IMAPS invites students to participate in an informal networking event on Tuesday, October 10 with IMAPS industry leaders over lunch in the exhibit hall, giving them an chance to learn about career opportunities, navigating the hiring process, and other topics. In addition, the IMAPS Microelectronics Foundation sponsors a student paper competitionin conjunction with the Symposium that awards more than $3,500 in scholarships for outstanding student papers.

Social Events & an Introduction to the RTP/Raleigh Area’s Technology Community
In addition to the technical program, a variety of social events are planned around the IMAPS Symposia, including the Annual David C. Virissimo Memorial Fall Golf Classic, a charity golf outing scheduled for Monday, October 9 at NCSU’s Lonnie Poole Golf Course. Proceeds from the event benefit the IMAPS Microelectronics Foundation.

Monday evening’s welcome reception will feature NC-themed entertainment from a local bluegrass band, and participants will also be able to view historical photos and other memorabilia spanning 50 years of IMAPS history.

There is also a scheduled tour of the nearby Micross Advanced Interconnect Technology (AIT) facility, one of the premier wafer bumping and wafer level packaging facilities in the U.S., with more than 20 years experience providing leading edge interconnect and 3D integration technologies (TSV, Si interposers, 3D IC) to worldwide customers.

New to the Symposium this year is a unique opportunity for IMAPS attendees to experience the vibrant technology community in the greater RTP/Raleigh area. IMAPS has invited local non-profit organizations that comprise the area’s rapidly-growing technology ecosystem to participate in a special area adjacent to the exhibit hall during the day of October 10, providing an opportunity for IMAPS Symposium attendees to network and interact.

To register for the IMAPS 50th International Symposium on Microelectronics, please visit the online registration site for more information, or contact Brianne Lamm, IMAPS Marketing & Events Manager, at [email protected] or 980-299-9873.

TowerJazz, the global specialty foundry, today announced the release of its advanced 5V 65nm power process providing customers with multiple advantages over 0.18um 5V technologies. The advanced 5V 65nm technology increases TowerJazz’s footprint in the 5V power market by offering enhanced Rdson efficiency with an attractive die cost advantage over 0.18um 5V processes. This technology is based on TowerJazz’s automotive 300mm 65nm process platform manufactured in its Uozu, Japan facility and supports both best in class quality and manufacturing cycle time.

The advanced 5V 65nm contains a rich portfolio of analog features and many different metal combinations to optimize cost/performance for any application. The first products, for several strategic customers, were already prototyped with outstanding performance. The technology is now fully released and supports Multi-layer Masking (MLM) and an MPW option to reduce engineering costs. The first MPW is targeted for November 2017.

TowerJazz’s 5V 65nm power technology offers high Rdson efficiency using tighter design rules for power devices, and a thick copper top metal for large current applications, enabling the 5V transistors using a 65nm design to achieve dense digital capabilities and a dense analog periphery, with a low number of manufacturing masks. The technology offers an average of 30% area reduction for a given 5V power transistor and typically a 35% die size reduction for a mixed-signal chip. An optimization effort to minimize cost and manufacturing layers needed to support 5V enables highly competitive solutions for many different markets such as automotive, industrial and consumer. The advanced 5V 65nm supports high current power applications such as PMIC, DC/DC converters, load switches and point of load ICs using single and dual 3.3um thick copper metal layers.

“Streamlining our feature rich automotive quality 65nm technology allows TowerJazz to provide very attractive 5V power and mixed-signal solutions with the high quality standard set required for servicing the automotive market,” said Shimon Greenberg, Vice President and General Manager of Mixed-Signal and Power Management Business Unit, TowerJazz. “This technology is utilized for relatively high current power ICs at 5V which have large growth drivers to advanced analog and mixed-signal ICs.”