Category Archives: Device Architecture

IC Insights has revised its outlook and analysis of the IC industry and presented its new findings in the Mid-Year Update to The McClean Report 2017, which originally was published in January 2017.  Entering the second half of the year, it is clear the IC industry is on course for a much stronger upturn than was initially forecast in January.  IC Insights now expects the IC market to increase 16% in 2017 due to exceptional growth in the DRAM and NAND flash memory markets. The DRAM market is now forecast to grow 55% and the NAND flash market is now expected to rise 35% this year—in both cases, almost entirely due to fast-rising prices rather than unit growth.  Excluding these two markets, the overall IC market growth is forecast to show just 6% year-over-year growth (Figure 1).  The expected 16% increase would be the first double-digit gain for the IC market since it expanded by 33% in 2010—the recession-recovery year—and the fifth double-digit increase for the IC market since 2000.

ic insights

As seen in the figure, the DRAM market has had a notable impact on total IC market growth in recent years. With market surges of 32% and 34% in 2013 and 2014, respectively, the DRAM market alone boosted the worldwide IC market growth rate by three percentage points in 2013 and four percentage points in 2014.

At $64.2 billion, the DRAM market is forecast to be by far the largest single product category in the IC industry in 2017, exceeding the expected second-ranked MPU market for standard PCs and servers ($47.1 billion) by $17.1 billion this year.

Overall, IC Insights’ global economic outlook remains on course with initial projections covered in The McClean Report. Electronic system production, capital spending as a percent of sales, and IC wafer capacity added were unchanged from the original outlook.  However, other factors and conditions that contribute to the forecast were upgraded slightly in the Mid-Year Update. For example, the worldwide GDP forecast was upgraded by 0.1 point to 2.7% for 2017, marginally ahead of what is considered to be the global recession threshold of 2.5% growth.  IC Insights believes that through the forecast period, annual IC market growth rates will closely track with the performance of worldwide GDP growth.

Following a fairly strong first half of growth, China’s 2017 GDP was raised to 6.8% for 2017 from the original forecast of 6.3%.  Also, IC Insights upgraded its U.S GDP forecast to 2.1% in the Mid-Year Updatefrom 2.0% in January. While the U.S. economy is far from perfect, it is currently one of the most significant positive driving forces in the worldwide economy.  A falling unemployment rate, PMI figures of 57.0 and 55.8 in the first and second quarters of this year, and relatively low oil prices should help the U.S. economy sustain its modest growth in the second half of this year. Growth rates for IC unit shipments, IC average selling price, and semiconductor capital spending were also revised slightly higher.

Additional details and commentary regarding the updated IC forecasts for the 2017-2021 timeperiod are covered in IC Insights’ Mid-Year Update to The McClean Report 2017.

Flux-closure domain (FCD) structures are microscopic topological phenomena found in ferroelectric thin films that feature distinct electric polarization properties. These closed-loop domains have garnered attention among researchers studying new ferroelectric devices, ranging from data storage components and spintronic tunnel junctions to ultra-thin capacitors.

In the development of thin films for such devices, researchers have thought that contact with commonly used oxide electrodes limits FCD formation. However, a group of researchers in China has shown otherwise. The findings are reported this week as the cover article in Applied Physics Letters, from AIP Publishing.

Ferroelectric materials are typically developed and studied as thin films, sometimes as thin as only a few nanometers. As a result, researchers have begun discovering the abundant domain structures and unique physical properties that these ferroelectrics possess, such as skyrmion and FCD formation that could benefit next-generation electronic devices. Because the films are so thin, however, their interaction with electrodes is inevitable.

“The general thinking has been that oxide electrodes would destabilize flux-closure domains. However, our work has shown that this is no longer true when the top and bottom electrodes are symmetric, which physically makes sense,” said Yinlian Zhu, professor at the Institute of Metal Research at the Chinese Academy of Sciences and a co-author of the paper.

Zhu and colleagues used two types of oxide electrodes: one based on strontium ruthenate, the other based on lanthanum strontium manganite, chosen as oxide electrodes because of their similar perovskite structures, which work well in layer-by-layer film growth. They studied how these electrodes influenced FCD formation in PbTiO3 (PTO) perovskite-oxide-based thin films deposited on gadolinium scandium oxide (GSO) substrates.

The research team’s previous studies indicated that flux-closure domains can be stabilized in strained ferroelectric films in which the strain plays a critical role in the formation of flux-closure domains, such as multilayer PTO/strontium titanate systems grown on GSO-based (specifically GdScO3) substrates.

Based on their previous studies, the researchers consequently anticipated that similar phenomenon might also occur in PTO/electrode systems. They then grew PTO films sandwiched between symmetric oxide electrodes on GSO substrates using pulsed laser deposition.

They found that periodic FCD arrays can be stabilized in PTO films when the top and bottom electrodes are symmetric, while alternating current domains appear when they apply asymmetric electrodes.

“We successfully grew ferroelectric thin films with symmetric oxide electrodes in which flux-closure domains and their periodic arrays clearly do exist,” Zhu said. “Our work sheds light on understanding the nature of flux-closure domains in ferroelectrics. We expect that it will open research possibilities in the evolution of these structures under external electric fields.”

Analog Devices, Inc. (ADI) today announced that it has become an affiliate member of Mcity at the University of Michigan. Mcity is a public-private partnership led by the University of Michigan to advance connected and automated vehicles. Among Mcity’s key initiatives is operating the Mcity Test Facility, which is the first purpose-built proving ground for testing connected and automated vehicles and technologies in simulated urban and suburban driving environments. Analog Devices will use the facility to test and refine future products in its Drive360 suite of technologies, including 28nm CMOS RADAR, solid state LIDAR, and high performance inertial measurement units for automated and autonomous driving applications.

By joining Mcity, ADI is committing to support the autonomous driving ecosystem as a premier semiconductor solutions provider and will use Mcity to understand market requirements through collaboration across the automotive design chain to bring connected and automated vehicle technologies to the commercial market.

ADI joins ranks with Mcity’s more than 65 industry members, which all play a role in creating a viable ecosystem to support connected and automated vehicles, including auto manufacturers and major parts suppliers, as well as vehicle communications, traffic infrastructure, and insurance companies, among others.

“Organizations like Mcity provide an important stage for testing products in real-world scenarios and for gathering real-time feedback from our customers and other key players in the autonomous driving ecosystem,” said Chris Jacobs, vice president, Autonomous Transportation and Safety, Analog Devices. “Working with the initiative will help shape our product and technology strategy by creating an open line of communication with customers and other industry leaders. This powerful connection will allow us to directly identify and address the toughest challenges to enable autonomous transportation.”

For an increasing number of designs, companies are finding it beneficial to design their own ASICs with system-on-a- chip (SoC) complexity. For reasons of cost reduction, quality improvement, IP protection and security, a full turn-key ASIC can be achieved for $1-5 million, particularly if the design can be built using mature technology nodes.

To further explore this topic, we asked questions from three leading experts in the field. Participating in the Q&A are:

• Michel Villemain, CEO, Presto Engineering, Inc.
• Guillaume Etorre, VP Engineering, Devialet
• Venkata Simhadri, CEO, Gigacom Semiconductor

Q: What is the decision-making process for deter- mining which applications are best addressed with an ASIC vs standard, off-the-shelf components? How does one calculate non-recurring engineering (NRE) costs, for example, and how does the anticipated part volume impact the decision?

Etorre: In many cases, particularly for IoT or other space-constrained designs, going with multiple standard compo- nents is simply not an option. A single chip must embed the microcon- trollers, sensors, battery management system, radios, etc. required by the application, in the smallest possible form factor.

When space is available, a standard component approach can be more appropriate to meet tight deadlines or to address situations where demand for the product is unproven. It can also serve as a stop-gap to serve the market immediately while a lower-cost ASIC solution is being designed.

If demand for the product is proven, a net present value calculation over a range of scenarios (best, typ., worst case for volumes and schedule for instance) will provide guidance on the best approach. An ASIC typically carries higher NRE (design, tapeout, qualification, test) but yields lower unit cost than an off-the-shelf solution. Depending on anticipated volumes and cost of capital, the lower unit cost of an ASIC will outweigh the higher NRE.

Simhadri: Primarily two factors can impact a company’s decision to design its own ASIC.
1. Competitive advantage – If the company is building its system using off-the- shelf components, competition can quickly reproduce it and you are only left with software as the differentiating factor. In this situation, you must have your own ASIC to protect your IP.
2. Cost – When addressing large volume markets the unit cost becomes an important factor and the only way to cut down the cost is to integrate/optimize the off-the-shelf components.

The typical NRE cost includes the cost of design, proto- typing (shuttle) and qualifying the part. Companies typically use a few benchmarks to justify the upfront cost.

For example, NRE cost is primarily dependent on the infrastructure (staff and tools) the customer already has in place. If the company already has a design team, EDA tools, etc. then the incremental cost might not be too high. However, without a design infrastructure already in place, it’s going to be a lot more time- consuming and costly. In this case, it is much easier to work with an ASIC design house to have all the infra- structure and some of the building blocks put in place.

Villemain: NRE is somewhat challenging to calculate since the duration of the project is often underestimated and unpredicted issues (who really does anticipate them!) bring additional cost to such a project. One way of mitigating this is to use external sources provided on (primarily) fixed- cost engagements. Beside ROI on NRE (function of margins and volume, indeed), drivers for using ASICs include: form factor, reliability, IP, power consumption and security.

Q: What are the tools and supply chain partners needed to successfully design an ASIC solution, including EDA software, foundry, packaging and test house?

Simhadri: You need the standard EDA tools for both Analog/ Digital, if you are designing a mixed-signal chip. Typically, you will have to work with at least two EDA vendors, such as Synopsys, Cadence, or Mentor Graphics. Many of the foundries will also work with small companies, provided you show a path to volume. However, in terms of design support (pdks, libraries, etc) foundries with better design infrastructure can save significant time. If you are a start-up or doing it for the first time, it can be quite daunting to setup the relationships and you can lose quite a bit of time to get the process going. But there are ways to save time and cost by outsourcing some of the work to the right design companies and echo system partners.

Villemain: Success is a function of a combination of multiple competencies that need to work coher- ently throughout the life of the product, especially post-design: industrialization, supplier management, quality, planning, logistics and product sustaining. This typically represents more than ten different skillsets that need to be part of the extended product team.

Etorre:
• Availability of proven IP (CPU, peripherals, interconnects, digital & analog I/O,…) for the chosen technology node.
• Affordable EDA software, with specific packages for companies designing only one or two chips at any given time, for specific end-user products vs. fabless IC companies which can spread the EDA license cost over many different chip designs every year.
• Efficient turn-key supply chain partner that can abstract out the complexity of foundry, packaging, test, storage and logistics for companies that lack critical mass.

Q: With the rise of IoT, IIoT and wearables, there’s much interest in analog/mixed-signal ASICs. How are their requirements different from traditional digital designs?

Villemain: Analog/RF designs tend to be smaller in size and to require less aggressive wafer fab processes. From a design standpoint, they demand less expensive EDA tools and less costly verification. However, their characterization and test is typically more complex and requires more expertise than a purely digital equivalent. Finally, yield management can be more demanding as the equation design window vs. process window is left more to the engineers than digital products, which can use semi-automated tools.

Simhadri: The primary difference in the require- ments is power and connectivity. If the ASICs must be connected to the internet, determining which protocols you need to incorporate on to the chip makes a big difference. Power is going to be a huge differentiating factor for the wearables, and designers are looking at various power saving techniques in an effort to optimize the power. Also, the foundries are offering special process nodes like SOI to address these markets.

In addition to the standard low power techniques like voltage islands and power shut off modes, the ASIC can further optimize the power by custom- izing the IP blocks for the specific applications. For, example, serial interfaces that burn lot of power, can be optimized.

Etorre:
• Design cycle is longer for analog IP than for digital.
• It is therefore critical to choose a foundry and a node for which all or most of the required IP are available.
•Analog IP is typically not portable between foundries or between nodes without significant rework.• •Custom analog IP is therefore a significant investment that will be depreciated if a foundry change or node change is required.
• The best nodes for analog, MEMS, RF, high- voltage and digital are usually not the same.
• Selecting the most appropriate node for the applications is not a trivial task.
• Introducing new functionality in a subse- quent version of an ASIC can require a node change and therefore major redesign of analog / mixed signal circuits. Anticipating future requirements can help make better technology choices.

Q: How do mask set costs of more mature technologies (180-40nm node) compare with those of 28nm and below, and how do mask costs enter into the overall cost equation?

Simhadri: I strongly advise our customers to use shuttles to prototype the ASIC and completely qualify it before spending a huge amount on the full mask. As expected, the 180-40nm shuttle costs are signifi- cantly lower than 28/16nm.

Villemain: With verification being less of a factor for analog/RF designs, mask sets can become a significant part of NRE below 90nm. Process technology is obviously a leading factor, but in addition, process routes can be costly because of additional options or IP, implying the addition of a mask/process layer, and thus, decreasing ROI in smaller geometries. Also, cost plateaus do exist (depending on the foundries) due to equipment transition (wafer size, lithography technol- ogies, etc.)

Etorre: The mask cost ratio between older technol- ogies and more recent ones can reach 20:1. For a 180nm design, once design, qualification and test fixtures are factored in, mask cost is not a significant contributor to the overall NRE.

Q: Out of the various advantages of ASIC design — cost reduction, quality improvement, IP protection and security – how would you rank their importance. Are there other advantages to ASIC solutions?

Villemain: What we see in the industry is a combi- nation of those factors (cost reduction, quality to architect an ASIC that replaces the discrete compo- nents in the system, which can reduce the BOM improvement, IP protection and security) as a function of the market our customers are operating in. The most common drive is, of course, that of cost (ASICs usually bring a dramatic product cost reduction), although for infrastructure applications, reliability is a key criterion, while for battery-operated applica- tions, power consumption reduction is mandatory— and all are benefits of using an ASIC.

In addition, more and more IoT segments require security in order to be even just a contender in the market, and an ASIC-based solution offers both a certifiable source of design and a cost benefit as compared to standalone secured elements.

Finally, in very competitive markets, the IP differen- tiation that an ASIC provides is a huge benefit.

Simhadri: IP protection and security shall rank first, followed by cost reduction. In some cases, off-the-shelf chips may not meet the performance requirements.

Etorre:
1. Real estate savings – an ASIC-based design is much smaller than an off-the-shelf approach;
2. Cost reduction
3. IP protection
4. Quality improvement, if any – combining various
functions and technologies (analog, digital, RF, power, MEMS, etc.) on the same die can lead to lesser quality.

Q: How has your company benefitted from an ASIC approach?

Etorre: Devialet’s Analog-Digital Hybrid (ADH) audio amplification technology was first implemented with discrete components. This discrete design is used in our high-end Expert Pro amplifiers and it supports the widest range of operating conditions.

In our Phantom speakers, we had to fit the same technology is a much smaller area. We specialized the analog circuit for the specific speaker drivers used in the Phantom and we designed an ASIC to deal with the analog part of the ADH technology.

Simhadri: Gigacom has been working with a company in the industrial IoT space and building systems for sensing gases and air quality. We have worked together by 10x and reduce the area and power significantly at the same time.

Q: How has the supply chain evolved to meet this new kind of demand?

Villemain: The supply chain needs to evolve in order to focus more on the backend than the frontend. If SoC brought RFCMOS to mass adoption with connected product, IoT, relying on a sensor-specific package, must integrate a companion ASIC driver and a transceiver; System in Package back-end technologies are gaining tremendous momentum. More and more companies will design their own ASICs, on well-proven, stable fab processes. However, packaging, reliability, test and security will become prime drivers, defining not only product costs, but also the ability to ramp, yield and scale up in volume. Supply chains (and especially the management of supply chains) is evolving accordingly.

For example, until recently, building an ASIC for an IoT device required the assembly of a team of experts, each with expertise in a different part of the process. The design might be created in-house or through an outside firm, and large companies, like automotive manufacturers, might assemble whole organizations, often called “operations” departments, with the sole task of managing the production of the specialized devices they needed. For a small company, with a game-changing new product idea, the cost and delay of assembling such a team can be fatal. If a competitor beats you to market you might not get a second chance. This need for manufacturing expertise led to the creation of “outsourced operations” companies, like Presto Engineering, that can manage the entire semiconductor manufacturing process from the completion of the design to the delivery of the tested product. By reducing the risk, cost, and difficulty of the production process, companies, such as Presto, are playing a key role in accelerating the proliferation of application specific semiconductor solutions.

Etorre: By design, ASICs run in lower volumes that standard parts. The supply chain must adapt to deal with more customers running lower volumes. This creates an opportunity for companies providing turn-key supply chain services to bridge the gap between numerous mid-volume customers and tradi- tional foundries and packaging houses who only address the largest fabless IC vendors.

Simhadri: The supply chain needs some improve- ments in the following areas. The older process nodes from 180nm to 40nm have suddenly become popular for IoT applications. However, most of the PDKs and other collateral were developed for older EDA tool versions and they need to be updated. Also, most of the IP vendors are targeting their resources for developing the IP for the latest process nodes where they get the best returns on their investment. Some of this IP has to be ported back to enable the ASICs in older nodes.

Also, to bring up these ASICs, the industry needs good support for packaging and testing facilities and all the top vendors are focused on high volume and leading- edge ASICs. Companies like Presto can potentially fill the needs.

As 3D NAND becomes the mainstream technology, its challenging roadmap poses opportunities for continued innovation.

BY HARMEET SINGH, Lam Research Corp., Fremont, CA

Since its introduction several years ago, 3D NAND has become a mainstream technology because of its ability to increase bit density in memory devices. Its adoption has been accelerated by advances in the underlying manufacturing processes that are enabling 3D architectures and lowering the cost per bit. With all its advantages, however, the overall complexity and capital intensity of 3D NAND manufacturing add significantly to the challenges fabs are facing in terms of process control, yield, and economics.

Market and technology drivers for 3D NAND

The main impetus for 3D NAND was the recognition that planar technology was approaching the end of its physical limits to deliver higher densities and a lower cost-per-bit. Past advances in conventional planar NAND technology have primarily been driven by physical scaling, where lithography capabilities determined just how many memory cells could fit within a given die size. Using multiple levels of charge within each cell by going from single- to multi-level cell designs has also enabled increased bit densities. However, these improvements typically have come at the expense of speed because of the need to differentiate between the multiple levels of charge. In addition, since the individual memory cells for these designs lie in a horizontal plane, scaling is still ultimately limited by lithography. Other challenges in scaling 2D NAND beyond the 15 nm node include cell-to-cell interference, unscalable dielectrics, and electron leakage [1].

To address these challenges, 3D NAND fundamentally changes the scaling paradigm. Instead of traditional X-Y scaling in a horizontal plane, 3D NAND scales in the Z-direction by stacking multiple layers of NAND gates vertically. This allows more cells to be packed into the same X-Y space (planar area) on the die without shrinking dimensions horizontally. By easing cell size requirements, triple- and even quadruple-level cell designs are possible. As such, 3D NAND offers a signif- icant increase in bit density over planar NAND.

Unlike planar NAND, where scaling is primarily driven by lithography, 3D NAND scaling is enabled by advances in deposition and etch processes. An incredible level of precision and repetition is required in defining complex 3D structures with extremely high aspect ratio (HAR) features. Achieving success with 3D NAND requires innovative deposition and etch solutions that minimize variability.

Overview of critical 3D NAND processes

The 3D NAND architecture requires advanced capabilities enabling HAR and complex structures (FIGURE 1). Critical processes involved include multilayer stack deposition, HAR channel etch, wordline metallization, staircase etch, HAR slit etch, and stair contacts formation. The following sections look at some of these areas in more depth and describe the most critical process parameters that must be controlled.

Screen Shot 2017-07-27 at 9.33.14 AM

Film deposition

Creating stacked memory cells starts with depositing alternating layers of thin films. Unlike planar NAND, where cell pitch is defined by lithography, pitch in 3D NAND is determined by the film thickness. As such, precise control of layer-to-layer deposition uniformity is extremely important. Currently, commercial 3D NAND products in high-volume manufacturing have layers ranging from 32 to 48 pairs, while next-generation products with more than 60 pairs are now beginning high-volume ramps.

Critical requirements for depositing stacked films are the stress and uniformity of the individual layers within the overall stack. These requirements become more stringent and increasingly more challenging to meet as the number of layers grows. Wafer bow and local film stress (FIGURE 2) directly impact the ability to achieve precise lithog- raphy overlay. Film thickness and repeatability affects the active area of cell and consistency of the litho/etch performance. As a result, both film stress control and excellent uniformity are critical to wafer yields. To address these concerns, careful management of stress by tuning deposition conditions and optimizing integration is needed not only for the film stack deposition, but also throughout 3D NAND manufacturing.

Screen Shot 2017-07-27 at 9.33.22 AM

High aspect ratio channel etching

HAR channel etch is the most critical and challenging step in 3D NAND because it is key to achieving uniform hole size through multiple layers to define the channel of memory cells. More than a trillion holes must be etched simultaneously and uniformly on every wafer, each with an aspect ratio of more than 40:1. For comparison, the highest aspect ratio structure that is etched in planar NAND is less than 15:1.

Deep etch on these multilayer stacks can push the limits of physics to achieve uniformity from top to bottom. As shown in FIGURE 3, the high aspect ratio of this etch leads to transport limitation challenges that can generate a range of problems. These include incomplete etch wherein some holes don’t reach the bottom, bowing, twisting, and CD variation between the top and bottom of the stack. Such defects can lead to shorts, interference between neighboring memory strings, and other perfor- mance issues. Solving these HAR-related transport issues requires precise control of high-energy ions during the etch process. Technologies that help deliver this capability include a symmetric chamber design for intrinsic uniformity, a proprietary high ion energy source with advanced plasma confinement and modulation, and orthogonal (independent) uniformity tuning knobs, such as multi-zone gas delivery and temperature control to achieve required uniformity across the wafer.

Screen Shot 2017-07-27 at 9.33.33 AM Screen Shot 2017-07-27 at 9.33.40 AM

As the 3D NAND roadmap adds more layers to achieve higher bit density, channel hole etching becomes increasingly challenging due to higher aspect ratios. Managing the fundamental trade-offs among profile, selectivity, and CD requires continuous equipment innovation, not only to deliver HAR etching capabilities for more than 100 pairs, but also to do this at the productivity needed for volume manufacturing.

Wordline tungsten metal fill

For replacement-gate 3D NAND schemes, wordline tungsten fill provides the critical conductive links between individual memory cells within layers. This process is particularly challenging because of the need to achieve void-free fill of complex, narrow, lateral structures with minimal stress on the memory stack.

Due to the structural complexity, atomic-scale engineering is required for wordline fill. Traditional CVD tungsten films have inherent characteristics that limit capability for 3D NAND wordline fill. High tensile stress in CVD tungsten can lead to wafer bow, and fluorine in the process has been known to diffuse into adjacent layers where it can create yield-limiting defects. In addition, resistivity limits scaling: making each layer thinner would allow for more layers (more storage bits), but would also make wordline resistance too high. One approach to address these concerns is the use of a low-fluorine tungsten (LFW) ALD process. This has the ability to provide a smoother morphology that conforms better with the surface in each fill layer, thereby minimizing stress induced by the deposition process. Stress reduction by more than an order of magnitude has been demonstrated with LFW ALD technology. This approach has also been shown to lower fluorine content by up to 100x (FIGURE 4) and reduce resistivity by over 30% compared to conventional CVD tungsten.

Screen Shot 2017-07-27 at 9.36.22 AM

 

Staircase etch

The staircase etch step creates the individual contact pads for each memory cell within the layers. A highly controlled etch process is used to define the size of each contact pad. To reduce the cost associated with lithography and improve productivity, repeated vertical etch and lateral trim etch processes are adopted to form the staircase instead of using numerous lithography steps. For each lithography pass, multiple staircase levels can be created by etching and trimming, as shown in FIGURE 5. The number of stairs that can be formed by this process is determined by the lateral-to-vertical (L/V) etch rate. Improving L/V etch selec- tivity can reduce the number of lithography steps needed.

Screen Shot 2017-07-27 at 9.33.50 AM

Extreme accuracy is required to maintain the stair CD, thus avoiding misaligned contacts. If the CD for a pad is off by a few percent, that error will propagate through subsequent pads defined within the same lithography pass. Current technology can deliver uniform and repeatable stair CD precision of 1% (3-sigma) after more than five L/V trim processes. This is a critical factor for achieving high productivity and being able to scale to higher stacks with more layers economically.

Summary

Traditional planar scaling to increase NAND density is approaching its limits due to lithography and performance challenges. As 3D NAND becomes the mainstream technology, its challenging roadmap poses opportunitiesforcontinuedinnovation. Stress management throughout wafer processing is crucial, and significant innovations in both deposition and etch processes are essential in forming the HAR features that dominate 3D NAND architectures. Finally, reducing variability in every critical step is a must to meet performance, yield, reliability, and cost requirements.

3D NAND completely changes the scaling paradigm by going vertical. No longer limited by lithography capabilities, 3D NAND can achieve greater levels of integrity, perfor- mance, and reliability – while building vertically for higher bit density and a lower cost-per- bit – through relying on advances in deposition and etch processes.

References

1. Y.W. Park, Flash Memory, IEDM short course, 2015

A key step in unlocking the potential for greener, faster, smaller electronic circuitry was taken recently by a group of researchers led by UAlberta physicist Robert Wolkow.

The research team found a way to delete and replace out-of-place atoms that had been preventing new revolutionary circuitry designs from working. This unleashes a new kind of silicon chips for used in common electronic products, such as our phones and computers.

“For the first time, we can unleash the powerful properties inherent to the atomic scale,” explained Wolkow, noting that printing errors on silicon chips are inevitable when working at the atomic scale. “We were making things that were close to perfect but not quite there. Now that we have the ability to make corrections, we can ensure perfect patterns, and that makes the circuits work. It is this new ability to edit at the atom scale that makes all the difference.”

Think of a typing mistake and the ability to go back and white it out and type it again perfectly. Now imagine that the white out is actually single hydrogen atoms, allowing a level of precision previously unattainable.

“We can precisely erase any errors and reprint that atom in the correct place. It’s not even a compromise like white out where you either have a gooey layer or indentation. It’s actually perfect,” said Wolkow, who worked with fellow scientists from the University of Alberta, the National Research Council, and Quantum Silicon Inc.

Scientists have seen many hints that atomic circuitry was within reach. However, the necessary precision was previously possible only for simple materials that had to be maintained at ultra-low temperatures, impractical for everyday applications demanded in computers and personal digital devices. Wolkow and his team have discovered methods and material to ensure stability at room temperature, challenges that he and other scientists the world over have been working for decades on overcoming.

Wolkow’s graduate students Roshan Achal and Taleana Huff together with postdoc Moe Rashidi showed they can overcome these obstacles with a modified approach to the same silicon chips that are used in today’s circuitry. While they had previously improved accuracy of atomic silicon printing, errors in the form of misplaced atoms always occurred at the one percent level. Though the placement errors were small–about one third of a nanometer–they nevertheless large enough to upset circuit operation.

The students created a reliable procedure for picking up single hydrogen atoms with their atomically sharp probe and replacing one or more hydrogen atoms to perfectly erase atomic misprints.

With their new discovery, many remaining challenges to ultra-low power atomic circuitry have also been erased. Wolkow, Achal, and Huff’s discovery has been captured in the academic paper “Atomic Whiteout,” appearing in the scientific journal ACS Nano.

 

Dow Corning, a developer of silicones, silicon-based technology and innovation and a wholly owned subsidiary of The Dow Chemical Company (NYSE: DOW), today announced that it received the prestigious Global Supplier Award from The Bosch Group, a worldwide supplier of technology and engineering services. Issued every two years, Bosch’s coveted awards recognize companies that have demonstrated outstanding performance in the manufacture and supply of products or services to Bosch – especially in terms of quality, pricing, reliability, technology, and continuous improvement. Bosch recognized 44 companies from 11 countries this year.

“We are delighted and very proud that Bosch has recognized Dow Corning’s commitment to its success with this prestigious award,” said Jörg Kersten, Dow Corning’s global key customer manager for The Bosch Group. “Like Bosch, we believe that long-term partnerships and close collaboration are the key to mutual success. It continues to be our privilege to work alongside their industry-leading team of innovators, and support their mission to be a top global engineer of automotive and electronic components.”

Karl Nowak, president of Corporate Sector Purchasing and Logistics at Bosch, informed Dow Corning via a letter that it had received the honor. Nowak’s letter read, in part: “Success in an increasingly connected and digitalized world requires strong and reliable partnerships. Your company’s outstanding performance and exemplary teamwork in 2015-16 contributed to Bosch’s success. To demonstrate our appreciation to you and your employees, we would like to honor you with the Bosch Global Supplier Award.”

Bosch officially bestowed its awards at a gala award ceremony held on July 12 in Stuttgart, Germany, and hosted by Robert Bosch GmbH’s executives and board members. Patrick McLeod, global business director, Dow Performance Silicones, and Wiltrud Treffenfeldt, chief technology officer, EMEAI at Dow, attended to accept the award on behalf of Dow Corning.

North America-based manufacturers of semiconductor equipment posted $2.29 billion in billings worldwide in June 2017 (three-month average basis), according to the June Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.

SEMI reports that the three-month average of worldwide billings of North American equipment manufacturers in June 2017 was $2.29 billion. The billings figure is 0.8 percent higher than the final May 2017 level of $2.27 billion, and is 33.4 percent higher than the June 2016 billings level of $1.72 billion.

“Through the first half of the year, 2017 equipment billings are 50 percent above the same period last year,” said Dan Tracy, senior director, Industry Research & Statistics, SEMI.  “While month-to-month growth is slowing, 2017 will be a remarkable growth year for the semiconductor capital equipment industry.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
January 2017
$1,859.4
52.3%
February 2017
$1,974.0
63.9%
March 2017
$2,079.7
73.7%
April 2017
$2,136.4
46.3%
May 2017 (final)
$2,270.5
41.8%
June 2017 (prelim)
$2,288.9
33.4%

Source: SEMI (www.semi.org), July 2017
SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

 

A team of physicists featuring researchers from MIPT and ITMO University has conducted a comparative analysis of a range of materials to determine if they are applicable to dielectric nanophotonics. Their systematic study produced results that can optimize the use of known materials for building optical nanodevices, as well as encourage the search for new materials with superior properties.

In order to send, receive, and process electromagnetic signals, antennas are used. An antenna is a device capable of effectively transmitting, picking up, and redirecting electromagnetic radiation. Typically, one thinks of antennas as macroscopic devices operating in the radio and microwave range. However, there are similar optical devices. The wavelengths of visible light amount to several hundred nanometers. As a consequence, optical antennas are, by necessity, nanosized devices. Optical nanoantennas, which can focus, direct, and effectively transmit light, have a wide range of applications, including information transmission over optical channels, photodetection, microscopy, biomedical technology, and even speeding up chemical reactions.

For an antenna to pick up and transmit signals efficiently, its elements need to be resonant. In the radio band, such elements are pieces of wire. In the optical range, silver and gold nanoparticles with plasmonic resonances have long been used for this purpose. Electromagnetic fields in such particles can be localized on a scale of 10 nanometers or less, but most of the energy of the field is wasted due to Joule heating of the conducting metal. There is an alternative to plasmonic nanoparticles, which has been studied extensively for the last five years, namely particles of dielectric materials with high refractive indices at visible light frequencies, such as silicon. When the size of the dielectric particle and the wavelength of light are just right, the particle supports optical resonances of a particular kind, called Mie resonances. Because the material properties of dielectrics are different from those of metals, it is possible to significantly reduce resistive heating by replacing plasmonic nanoantennas with dielectric analogs.

The key characteristic of a material determining Mie resonance parameters is the refractive index. Particles made of materials with high refractive indices have resonances characterized by high quality factors. This means that in these materials electromagnetic oscillations last longer without external excitation. In addition, higher refractive indices correspond to smaller particle diameters, allowing for more miniature optical devices. These factors make high-index materials — i.e., those with high indices of refraction — more suitable for the implementation of dielectric nanoantennas.

In their paper published in Optica, the researchers systematically examine the available high-index materials in terms of their resonances in the visible and infrared spectral ranges. Materials of this kind include semiconductors and polar crystals, such as silicon carbide. To illustrate the behavior of various materials, the authors present their associated quality factors, which indicate how quickly oscillations excited by incident light die out. Theoretical analysis enabled the researchers to identify crystalline silicon as the best currently available material for the realization of dielectric antennas operating in the visible range, with germanium outperforming other materials in the infrared band. In the mid-infrared part of the spectrum, which is of particular interest due to possible applications, such as radiative cooling, i.e., the cooling of a heated body by means of radiating heat in the form of electromagnetic waves into the environment; and thermal camouflage — reducing thermal radiation given off by an object, thus making it invisible to infrared cameras, the compound of germanium and tellurium took the pedestal.

There are fundamental limitations on the value of the quality factor. It turns out that high refractive indices in semiconductors are associated with interband transitions of electrons, which inevitably entail the absorption of energy carried by the incident light. This absorption in turn leads to a reduction of the quality factor, as well as heating, and that is precisely what the researchers are trying to get rid of. There is, therefore, a delicate balance between a high index of refraction and energy losses.

“This study is special both because it offers the most complete picture of high-index materials, showing which of them is optimal for fabricating a nanoantenna operating in this spectral range, and because it provides an analysis of the manufacturing processes involved,” notes Dmitry Zuev, research scientist at the Metamaterials laboratory of the Faculty of Physics and Engineering, ITMO University. “This enables a researcher to select a material, as well as the desired manufacturing technique, taking into account the requirements imposed by their specific situation. This is a powerful tool furthering the design and experimental realization of a wide range of dielectric nanophotonic devices.”

According to the overview of manufacturing techniques, silicon, germanium, and gallium arsenide are the most thoroughly studied high-index dielectrics used in nanophotonics. A wide range of methods are available for manufacturing resonant nanoantennas based on these materials, including lithographic, chemical, and laser-assisted methods. However, in the case of some materials, no technology for fabrication of resonant nanoparticles has been developed. For example, researchers have yet to come up with ways of making nanoantennas from germanium telluride, whose properties in the mid-infrared range were deemed the most attractive by the theoretical analysis.

“Silicon is currently, beyond any doubt, the most widely used material in dielectric nanoantenna manufacturing,” says Denis Baranov, a PhD student at MIPT. “It is affordable, and silicon-based fabrication techniques are well established. Also, and this is important, it is compatible with the CMOS technology, an industry standard in semiconductor engineering. But silicon is not the only option. Other materials with even higher refractive indices in the optical range might exist. If they are discovered, this would mean great news for dielectric nanophotonics.”

The research findings obtained by the team could be used by nanophotonics engineers to develop new resonant nanoantennas based on high-index dielectric materials. Besides, the paper suggests further theoretical and experimental work devoted to the search for other high-index materials with superior properties to be used in new improved dielectric nanoantennas. Such materials could, among other things, be used to considerably boost the efficiency of radiative cooling of solar cells, which would constitute an important technological advance.

Worldwide silicon wafer area shipments increased during the second quarter 2017 when compared to first quarter 2017 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,978 million square inches during the most recent quarter, a 4.2 percent increase from the 2,858 million square inches shipped during the previous quarter. New quarterly total area shipments are 10.1 percent higher than second quarter 2016 shipments and are at their highest recorded quarterly level.

“For the fifth consecutive quarter, global silicon wafer volume shipments have shipped at record levels,” said Chungwei (C.W.) Lee (李崇偉), chairman of SEMI SMG and spokesman, VP, Corporate Development and chief auditor of GlobalWafers (環球晶圓). “These record levels are being driven by both 200mm and 300mm shipments.”

Silicon* Area Shipment Trends

Source: SEMI, (www.semi.org), July 2017

 

Millions of Square Inches
 

1Q2016

2Q2016

3Q2016

4Q2016

1Q2017

2Q2017

Total

2,538

2,706

2,730

2,764

2,858

2,978
*Semiconductor applications only

 

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.