Category Archives: Device Architecture

By Emmy Yi

SEMI Taiwan Testing Committee founded to strengthen the last line of defense to ensure the reliability of advanced semiconductor applications.

Mobile, high-performance computing (HPC), automotive, and IoT – the four future growth drivers of semiconductor industry, plus the additional boost from artificial intelligence (AI) and 5G – will spur exponential demand for multi-function and high-performance chips. Today, a 3D IC semiconductor structure is beginning to integrate multiple chips to extend functionality and performance, making heterogeneous integration an irreversible trend.

As the number of chips integrated in a single package increases, the structural complexity also rises. Not only will this make identifying chip defects harder, but the compatibility and interconnection between components will also introduce uncertainties that can undermine the reliability of the final ICs. Add to these challenges the need for tight cost control and a faster time to market, and it’s clear that semiconductor testing requires disruptive, innovative change. Traditional final-product testing focusing on finished components is now giving way to wafer- and system-level testing.

In addition, the traditional notion of design for testing, an approach that enhances testing controllability and observability, is now coupled with the imperative to test for design, which emphasizes drawing analytics insights from collected test data to help reduce design errors and shorten development cycles. Going forward, the relationship among design, manufacturing, packaging, and testing will no longer be un-directional. Instead, it will be a cycle of continuous improvement.

This paradigm shift in semiconductor testing, however, will also create a need for new industry standards and regulations, elevate visibility and security levels for shared data, require the optimization of testing time and costs, and lead to a shortage of testing professionals. Solving all these issues will require a joint effort by the industry and academia.

“With leading technologies and $4.7 billion in market value, Taiwan still holds the top spot in global semiconductor testing market,” said Terry Tsao, President of SEMI Taiwan. “When testing extends beyond the manufacturing process, it can play a critical role in ensuring quality throughout the entire life cycle from design and manufacturing to system integration while maintaining effective controls on development costs and schedules. Taiwan’s semiconductor industry is in dire need of a common testing platform to enable the cross-disciplinary collaboration necessary for technical breakthroughs.”

The new SEMI Taiwan Testing Committee was formed to meet that need, gathering testing experts and academics from MediaTek, Intel, NXP Semiconductors, TSMC, UMC, ASE Technology, SPIL, KYEC, Teradyne, Advantest, FormFactor, MJC, Synopsys, Cadence, Mentor, and National Tsing Hua University to collaborate in building a complete testing ecosystem. The committee addresses common technical challenges faced by the industry and cultivates next-generation testing professionals to enable Taiwan to maintain its global leadership in semiconductor testing.

The SEMI Taiwan Testing Platform spans communities, expositions, programs, events, networking, business matching, advocacy, and market and technology insights. For more information about the SEMI Taiwan Testing platform, please contact Elaine Lee ([email protected]) or Ana Li ([email protected]).

Emmy Yi is a marketing specialist at SEMI Taiwan.  

This story originally appeared on the SEMI blog.

By Christian G. Dieseldorff

This year, SEMI ISS covered it all – from a high-level semiconductor market and global geopolitical overview down to the neuro morphic and quantum level. Here are key takeaways from the Day 1 keynote and Economic Trends and Market Perspectives presentations.

In the opening keynote, Anne Kelleher from Intel pointed to the huge growth of data, with fabs collecting more than 5 billion sensor data points each day. The challenge, Kelleher noted, is to turn massive amounts of data into valuable information. Moore’s law is not dead. New models of computing benefit still from Moore’s law and advances in Si/CMOS technologies for conventional, deep learning, neuro morphic and quantum computing.

With customers expecting continual improvements in applications, the question is whether the chip industry is moving fast enough to meet these expectations, Kelleher said. A broad supply chain, equipment and materials innovations, and attracting the “best of the best” college graduates to fuel innovation is key, she said.

In the economic trends session, Nicholas Burns (ambassador ret.) from Harvard University pointed out that we will see a major shift in power. The U.S. will remain the major world power over the next 10 years, but we will see a major shift in power in the next coming decades as the gap with countries like China, Russia and India continues to narrow.

Duncan Meldrum from Hilltop Economics said that we are passing the peak growth of economic cycle. He warns that a more likely outlook is that a global growth recession is developing. Although semiconductor MSI growth will see a noticeable slowdown in 2019 and 2020, the semiconductor industry is still healthy over the longer term.

Bob Johnson from Gartner sees demand shifting from consumer to commercial applications with higher ROIs and budgets. AI, IoT and 5D are the major enablers. He sees structural changes in the semiconductor industry especially for memory but also for Moore’s law with increasing costs and fewer players.

The DRAM markets shows volatility and NAND market may be negative in 2019 but non-memory are expected to accelerate mainly because of increasing content and some price hikes.

Overall Gartner expects good long-term growth with a CAGR (2017 to 2022) of 5.1%, outpacing 2011 to 2016 CAGR of 2.6%. After a strong 2018 with 13.4% revenue, he forecasts a slower 2019 with 2.6% growth followed by a 8% growth in 2020 and negative growth rate in 2021.

Andrea Lati of VLSI went “Back to fundamentals” in his presentation about the industry. VLSI sees a downside bias due to slowing global economy, tariffs, and trade wars. Future drivers are data economy, cloud, AI and automotive.

As memory leads the 2019 slowdown, analog, power, logic and other sectors remain in positive territory. VLSI lowered its semiconductor equipment forecast for 2018 from 20% (Jan. 2018) to 14% (Dec. 2018) but increased its sales outlook from 8% to 15% in 2018. VLSI expects revenue to slow into the first half of 2019 but increase to over 4% in the second half of the year, resulting in total 2019 drop of 2.7%. Semiconductor equipment sales are expected to drop from 14% in 2018 to -10% in 2019.

Michael Corbett of Linz Consulting, covering wafer fab materials in the years of 3D scaling, sees these as good times for the industry. His outlook for wafer fab materials is bullish based on strong MSI and because wafer fab materials suppliers are getting bigger because of M&As.

In the Market Perspective session, Sujeet Chand of Rockwell Automation pointed out that as more and more data is generated, the problem is how to get value of all the data collected. There is a need to create the right architecture for machine learning and AI and big data is increasingly being replaced by contextual/structured data. He expects Industry 4.0 to drive foundries to become smaller, more flexible and more productive.

In the Technology and Manufacturing session, Aki Sekiguchi of TEL addressed process challenges in the age of co-optimization. The semiconductor industry continues to expand, driven by massive growth of interconnected devices, with heavy demand for processing power and storage. He expects an exponential increase of data from about 40ZB in 2018 to 50ZB in 2020 to 163 ZB in 2026.

Major technologies such as DRAM, 3D NAND and logic are dealing with scaling challenges. The density of DRAM (Mb/chip) is plateauing according to 2015 to 2020 trend data, with DRAM is in need of EUV. Memory capacity demand is leading to increasing layers and higher aspect ratios that is concern for 3D NAND and mainly for plasma etch. With Logic already implementing 3D structures, it appears to be in a solid position.

Buddy Nicoson of Micron talked about his 50 years in the industry and looked ahead to the next 50. The anchors – quality, cost, scale and speed – won’t change. It has been a great journey so far with unprecedented opportunities and challenges ahead of us. We are getting into a convergence (specialization, integration) and solution-based phase. We will see some inflection points in the coming years, with the best yet to come.

Christian G. Dieseldorff is senior principal analyst in the Industry Research and Analysis group at SEMI in California.

This story first appeared on the SEMI blog.

SIA today filed comments to the Department of Commerce Bureau of Industry and Security (BIS) in response to an advanced notice of proposed rulemaking of controls for “emerging” technologies. In accordance with requirements of the Export Control Reform Act of 2018 (ECRA), enacted into law as part of the defense authorization bill, BIS is required to establish export controls on certain “emerging and foundational technologies.” The SIA comments respond to the request for comments on “emerging” technologies, and we expect BIS to commence a separate rulemaking on “foundational” technologies sometime this year.

Maintaining a strong U.S. semiconductor industry is critical to our country’s economic and national security. Semiconductors are America’s fourth-largest export, and the semiconductor industry has a highly complex, specialized, and geographically widespread global supply chain. For these reasons, it is important for government and industry to work together to ensure U.S. export control policies both enhance our national security and continue to allow the U.S. semiconductor industry to grow and innovate. SIA has long collaborated with the U.S. government to support reforms and modernization of export control policy, particularly with respect to semiconductors.

The SIA comments outline the statutory framework set forth in ECRA and call on BIS to carefully consider each of the factors set forth in the statute in crafting narrowly tailored controls on emerging technologies. Among other things, ECRA calls on BIS to consider controls only on technologies essential to national security, whether these technologies are exclusive to the U.S. or are available from foreign sources, and the effectiveness of proposed controls. It also directs BIS to consider the impact of unilateral controls on specified technologies on domestic research and development and the economy as a whole. SIA’s comments provide detailed recommendations on how BIS can best implement these statutory mandates.

We are confident BIS, by following the statutory criteria set forth in ECRA and considering the input of affected stakeholders, will enhance national security while at the same time enabling the semiconductor industry in the U.S. to grow and innovate.

The SEMI Industry Strategy Symposium (ISS) opened this week with the theme “Golden Age of Semiconductor: Enabling the Next Industrial Revolution.” The annual three-day conference of C-level executives gives the year’s first comprehensive outlook of the global electronics manufacturing industry.

For ISS 2019’s nearly 300 attendees, opening day highlighted market and technology opportunities and the high-water mark for semiconductor manufacturing supply chain investments in 2018. Deep discussions on applications, disruptions and Industrial Revolution 4.0 will mark today, Day 2. Day 3 will feature presentations on industry workforce development and the evolving U.S.-China relationship and convene an expert panel on “The Next Semiconductor Revolution: Filling the Gap Between Smart Speakers and Autonomous Vehicles” to culminate SEMI‘s business leader annual kick-off event.

Opening keynote speaker Ann Kellehere, Senior Vice President and General Manager of the Technology and Manufacturing Group at Intel, observed that data is powering the fourth industry revolution and the expansion of compute markets. Excellent customer experience and new technologies including Internet of Things (IoT), artificial intelligence (AI) and autonomous vehicles are key drivers of data growth.

Today, fabs collect more than 5 billion sensor data points each day. The challenge, Kellehere noted, is to turn massive amounts of data into valuable information. With customers expecting continual improvements in applications, the question is whether the chip industry is moving fast enough to meet these expectations. A broad supply chain, equipment and materials innovations, and attracting the “best of the best” college graduates to fuel innovation is key, she said.

In the Economic Trends session, presenters took on macroeconomic trends and detailed industry-specific forecasts:

Ambassador (Ret.) Nicholas Burns, Harvard Kennedy School of Government, noted the United States is trailing China in a battle for technological supremacy. By 2050, Indo-Pacific could become the world’s locus of economic power, potentially leading to conflict and instability. The rise of nationalism in China, India, Japan, Russia and the U.S. is a major trend, and the power gap between the U.S. and China, Russia and India is narrowing. From 1979 through last, China and the U.S. came together to solve big problems, he noted. The world has shifted ominously from strategic engagement to outright strategic competition.

Duncan Meldrum, Hilltop Economics, noted the world has passed the peak of its current economic expansion, with GDP peaking in 2018 and gradually slowing to 2.7 percent trend growth. The consensus outlook is for strong global economic growth. While an alternate outlook holds that a global recession will develop, a deep growth recession isn’t expected. The problem today is that global economic uncertainty is at an all-time high, suppressing investment and growth.

Bob Johnson, Gartner, forecasts businesses will get $5 trillion of value from AI by 2025 as businesses explore ways to implement AI to tap its tremendous potential. AI, IoT and 5G are major enablers of new value, with market demand shifting from consumer to commercial applications offering higher returns on investments, Johnson said. Future semiconductor market drivers include augmented analytics, digital twins, AI, autonomous things, blockchain, smart spaces and quantum computing.

Andrea Lati, VLSI Research, expects the semiconductor slowdown to continue into the first half of 2019 and said it could face a decline of as much as 35 percent. The strategic question for industry leaders is how to transition from a commodity provider to a value provider. In 2019, both semiconductor equipment and assembly sales are forecast to drop 13 percent, ending equipment’s strong run since 2016.

Michael Corbett, Linx Consulting, provided an upbeat outlook for the materials industry, which is enjoying a record expansion with MSI a key driver and record levels of capital expenditures reflecting very high utilization across both 200mm and 300mm. Materials market trends include a wafer fab materials CAGR of 6.9 percent from 2017 to 2022 and industry growth of $26 billion in 2018 to $33 billion in 2022.

The afternoon session focused on Market Perspectives, including smart manufacturing, human health, AI and 5G.

Sujeet Chand, Rockwell Automation, outlined Smart manufacturing best practices for semiconductor production. He envisions big data being increasingly replaced by data structured based on target factory outcomes that dictate whether to run analytics on the edge or in the cloud. Semiconductor fab productivity driven by digitization will grow faster in the next 10 years than in the past 50 as information and operational technology converge to speed the optimization of semiconductor fabs and supply networks, he said.

Igor Fisch, Selexis, focused on how the current golden age of semiconductors is shaping human health. He pointed to the critical importance of chips in biotechnology as big data becomes key to the analytics that will give rise to personalized diagnostics and therapies. Drug discovery and development will rely on massive computing power and data storage, with semiconductor and supercomputer technologies key enablers of precision medicine.

Eric Jones, Enthought, noted that semiconductor manufacturers must reimagine themselves over the next decade to power their own digital transformation. Data consolidation, automation and simulation will enable the predictive power – key to digital transformation – of AI and machine learning, he said. However, the greatest challenge is related to changing company culture, philosophy and organizational design.

Sree Koratala, Ericsson, forecasts 5G will evolve from initial use cases to mainstream adoption in 2024. Connectivity has reached an inflection point, with the focus shifting from consumers to businesses including the immersive experiences of virtual and augmented reality (AR/VR), autonomous control and cloud robotics. 4G and 5G will co-exist to deliver a much larger impact to people and businesses, she noted.

Sarah Cooper, Amazon Web Services, highlighting IoT trends, offered a vision of products learning from collected data to personalize functionality. Product differentiation is not about the specifications but about the customer experience. Coupling device data with machine learning can create a product that adapts to changing customer needs, eliminating the need to develop separate SKUs, she noted.

Days 2 and 3 at ISS will delve deeper into the industry with presentations by: Tokyo Electron Limited,Xperi, Micron Technology, Google, Applied Materials, McKinsey & Company, Brewer Science, DECA Technologies, Carbon, Bank of America Merrill Lynch and SEMI. 

The SEMI Industry Strategy Symposium (ISS) examines global economic, technology, market, business and geo-political developments influencing the global electronics manufacturing industry along with their implications for your strategic business decisions. For more than 35 years, ISS has been the premier semiconductor conference for senior executives to acquire the latest trend data, technology highlights and industry perspective to support business decisions, customer strategies and the pursuit of greater profitability.

SEMI, the global industry association serving the electronics manufacturing supply chain, today announced that Mike Russo has joined SEMI as vice president of Global Industry Advocacy, based in the company’s Washington D.C. office. Reporting to SEMI President and CEO Ajit Manocha, Russo oversees SEMI’s government relations program and advocacy efforts worldwide, leading the development and execution of strategies to strengthen SEMI’s public policy program and the association’s initiatives addressing the broader semiconductor industry’s talent gap, a top SEMI priority.

“In light of the changing geopolitical dynamics around the world seriously impacting our industry, we are thrilled to welcome government affairs veteran Mike to SEMI,” said Manocha. “His arrival at SEMI to support SEMI’s Global Advocacy mission is very timely. Mike is a high-impact leader with rich public policy experience in the semiconductor industry and an invaluable asset to SEMI and our members as we advocate for the industry across trade, tax, technology and talent. Already, Mike is broadening the scope of SEMI’s advocacy work with global programs that address the industry’s critical need to build the workforce of the future.”

Russo’s experience as a government affairs executive in the semiconductor industry includes spearheading strategic initiatives in supply chain innovation, infrastructure development, education and workforce development. Most recently, he served as president of Entregar Consulting Group, a firm focused on strategic, public-private partnerships in manufacturing and technology.

For nearly a decade, Russo led the U.S. corporate office of government affairs for GLOBALFOUNDRIES, the nation’s largest global contract semiconductor chipmaker. In that role, Russo oversaw government relations, regulatory affairs and strategic initiatives.

In government, Russo served as a senior staff member in both the Senate and House and has served in various capacities as an advisor to the U.S. government on manufacturing industrial base policy, including leading the national advisory group for the former National Network of Manufacturing Innovation (NNMI), now Manufacturing USA, under the President’s Council of Advisors on Science and Technology  for Advanced Manufacturing Partnership (AMP).

By Paul Trio

SCIS is a SEMI Technology Community that tackles critical component defectivity for the semiconductor manufacturing industry. The organization develops test methods for measuring defects in these critical components. Originally, this SEMI community was looking at challenges surrounding sub-10nm process nodes, but our constituents – Integrated Device Manufacturers (IDMs), capital equipment OEMs, and (sub)component suppliers – felt that the immediate need was for standards that would apply to process nodes that are already being used for volume semiconductor device manufacturing.

IDMs need ways to tell their supply chain how defects attributable to these critical components factor into the overall process-node defect budgets and wafer-contamination limits. Chipmakers and IDMs needed to start with a baseline: How problematic are existing critical components in the overall fab systems and how do these contaminants contribute to defects and how do they affect overall process yields?

These questions must be answered for every component in the fab’s process line including the drums that hold the fab chemistries, fluid delivery systems, and components used in the wafer-processing chamber. All of these critical fab-line components come into contact with each manufactured wafer, in one way or another, and each is a suspect with respect to contamination, defects, and yield problems. SCIS develops test methods for these fab-line critical components testing that are used to identify the defects caused by these components and for establishing baselines.

SCIS has seven working groups dealing with various critical components. Each is developing various test methods for many critical fab-line components. There are many facets with respect to testing each of these critical components.

Take something as simple as a seal, such as an FFKM (perfluoroelastomer, made from polymers) seal. These seals are ubiquitous in fab lines. In harsher environments, such as inside of a processing chamber, these seals are exposed to high temperatures and harsh chemistries. Different FFKM seals will have different characteristics such as thermal resistivity and chemical resistance, depending on customer specifications, and can also vary from one manufacturer to another. In addition, these characteristics can change depending on environmental conditions – or just the passage of time.

SCIS looks at defect traits from the perspective of each component in the fab line and decides which of the components’ parameters contribute most to process defects. Initially, the SCIS Seals & Valves Group collected a list of seal-related issues or parameters. The working group then cross-checked these parameters against different manufacturing processes used in the fab including ALD (atomic layer deposition) and CVD (chemical vapor deposition). Some processes are harder on seals than others. Then the working group prioritized these various parameters according to their contribution to the overall process defect budget. IDMs provided important input during these steps because they work with these seals on a daily basis. At this point, the SCIS working group had a prioritized list of parameters, vetted by various stakeholders in the semiconductor manufacturing industry. The group then set to develop standardized measurement methods for these critical parameters.

Based on this work, the SCIS Seals & Valves Group has already published two documents. The first is a standard that specifies methods for testing seal-induced impurities such as ashing (analysis of metals content of the ash) and TOC (total organic content).

The second document published by the Seals & Valves Group is a guide that documents BKMs (best known methods) for handling seals – from the moment they’re cured in an oven to packaging, shipping, handling in a fab, and installation – a to reduce contamination problems during use. For example, some seals are sensitive to light. Some polymer seals degrade when they come into contact with IPA (isopropyl alcohol), which is often used for prepping. A degraded seal can emit contamination particles during processing, which will cause yields to fall. (This latter bit of information came directly from a major IDM, which demonstrates the invaluable role that users of these components can play in the development of testing standards.)

The Seals & Valves Group’s current work focuses on developing a standard for measuring seal leak rates. This standard will define test methods for evaluating a seal’s ability to maintain pressure under vacuum. Although there are well-established standard for testing seal CSR (compressive stress relaxation) in the aerospace industry, there’s no such standard for the semiconductor industry. So originally, the Seals & Valves Group tried to tackle that challenge by developing a similar standard for SEMI’s constituents. However, a more practical and immediate parametric challenge turned out to be seal leakage rates.

Installed seals are exposed to high temperatures and harsh chemistries in the semiconductor fabrication process. The Seals & Valves Group decided to develop a test method that would determine how well seals perform over time with respect to leakage rates as the seals are exposed to cyclic harsh conditions. The goal is to simulate the working conditions for these seals, as closely as possible and in a repeatable manner.

There are, of course, some challenges associated with this work. For example, IDMs and equipment OEMs don’t want to reveal their exact process conditions as they are proprietary. So the Seals & Valves Group took a step back and focused on developing a test method based solely on exposure to elevated temperatures.

Development of this thermal test requires the design of a standardized test jig to help ensure consistent, repeatable tests, shown in Figure 1.

Figure 1: Elastomer seal test jig developed by the SCIS Seals & Valves Group.

The seal under test, shown in red in Figure 1, sits at the center of the jig. A second seal, shown in green, is used to seal the actual test environment. Two thermocouples in the jig’s top and bottom monitor of the temperature inside of the jig. There are gas and purge lines for controlling the ambient pressures on either side of the seal under test.

Figure 2 illustrates how the jig is connected to the gas sources.

Figure 2: The Seals Test Jig is connected to helium and nitrogen gas sources and to a calibrated leak (vacuum) line.

The seals leak test is based on a helium leak test. Helium is one of the smallest atoms so it will leak through just about any small gap and, with time, permeate through the material as well. In addition, helium is inert, and testing for helium using a mass spectrometer is a well-established technique for leak testing. Helium leak testing can be one thousand to one million times more sensitive than using mechanical, pressure-decay test techniques. The jig’s nitrogen lines serve to purge the test chambers of helium between leak tests.

Developing just a test jig is not sufficient. The Seals & Valves Group also developed a test sequence for using the jig. There were no existing standard, so the group needed to use its knowledge of the seals’ composition and operating conditions to develop certain test parameters. For example, the group elected to use 200°C as the maximum temperature for the high-temperature portion of the test because FFKM seals start to degrade at 250°C.

At this point, the Seals & Valves Group has gone through several iterations of a proposed test sequence. There was some initial reluctance to provide detailed inputs, but after a few iterations of the proposed method (and an understanding that this would become an industry standard to hold suppliers accountable), inputs have become more forthcoming.

This is an excellent example that demonstrates why it’s so important for SCIS working groups to get chipmakers, IDMs, component vendors, and even feedstock materials vendors to participate in these standardization efforts. Standards are far more useful if they’re based on real-world conditions.

Currently, the SCIS Seals & Valves Group is working towards finalizing the seals-leak test sequence. The jig has been designed in AutoCAD and a prototype will soon be manufactured. Although the test and jig have been developed with significant industry participation, the validity of the test has yet to be determined. The validity will be verified though Alpha testing before the jig design and test method are incorporated into a standard.

However, SEMI is not a test house. It’s a facilitator. The testing will therefore be performed by a neutral third party capable of carrying out the test under fab-like conditions. SEMI’s role is to work with different testing entities such as SUNY Polytechnic Institute in Utica, New York or IMEC in Belgium.

SEMI will solicit bids for this work through its SCIS Executive Advisory Committee, which consists of C-level executives from device makers, semiconductor capital equipment OEMs, and major critical component suppliers. This project has leveraged many of the relationships that SEMI has developed over the years and has broken new ground in standards making for SCIS and for SEMI.

For those looking to learn more about SCIS or engage in ongoing efforts, please contact Paul Trio, senior manager of Strategic Initiatives at SEMI, at [email protected].

IC Insights is in the process of completing its forecast and analysis of the IC industry and will present its new findings in The McClean Report 2019, which will be published later this month.  Among the semiconductor industry data included in the new 400+ page report is an in-depth analysis of the IC foundry market and its suppliers.

With the recent rise of the fabless IC companies in China, the demand for foundry services has also risen in that country.  In total, pure-play foundry sales in China jumped by 30% in 2017 to $7.6 billion, triple the 9% increase for the total pure-play foundry market that year.  Moreover, in 2018, pure-play foundry sales to China surged by an amazing 41%, over 8x the 5% increase for the total pure-play foundry market last year.

As a result of a 41% increase in the China pure-play foundry market last year, China’s total share of the 2018 pure-play foundry market jumped by five percentage points to 19% as compared to 2017, exceeding the share held by the rest of the Asia-Pacific region (Figure 1).  Overall, China was responsible for essentially all of the total pure-play foundry market increase in 2018!

All of the major pure-play foundries registered double-digit sales increases to China last year, but the biggest increase by far came from pure-play foundry giant TSMC.  Following a 44% jump in 2017, TSMC’s sales into China surged by another 61% in 2018 to $6.0 billion.  The China market was responsible for essentially all of TSMC’s sales increase last year with China’s share of the company’s sales doubling from 9% in 2016 to 18% in 2018.

A great deal of TSMC’s sales surge into China in 2018 was driven by increased demand for custom devices going into the cryptocurrency market.  While TSMC enjoyed a great ramp up in sales for its cryptocurrency business through 2Q18, the company encountered a slowdown for this business in the second half of last year, which was apparent in its slower sales to China in 3Q18 and 4Q18.  The 2018 plunge in the price of Bitcoins (from over $15K per Bitcoin in January of 2018 to less than $4K in December of 2018) and other cryptocurrencies lowered the demand for these ICs.

Figure 1

With China’s share of the pure-play foundry market quickly growing (going from representing 11% of the total pure-play foundry market in 2015 to a 19% share in 2018) it comes as no surprise that many of the pure-play foundries are planning to locate or expand IC production in Mainland China.  Notably, each of the top seven pure-play foundries has plans for increasing China-based wafer fabrication production, including the five non-Chinese foundries of TSMC, GlobalFoundries, UMC, Powerchip, and TowerJazz

SEMI and imec are joining forces to drive innovation and deepen industry alignment on technology roadmaps and international standards while adding technology depth to SEMI’s five vertical application platforms including Smart Transportation, Smart MedTech and Smart Data.

Under a Memorandum of Understanding announced today at ISS 2019, the two organizations have set their sights on bringing together key industry players to advance cutting-edge technologies including Internet of Things (IoT), artificial intelligence (AI) and machine learning that enable new capabilities across healthcare, automotive and semiconductor manufacturing. The partnership also aims to speed the time to better business results for SEMI and imec members and partners.

SEMI brings to the partnership access to the $2 trillion global electronics manufacturing supply chain and imec its global research and development (R&D) and innovation leadership in nanoelectronics and digital technologies.

Under the MOU, the two organizations will co-produce SEMI Think Tanks, extend SEMI’s International Standards platform to non-CMOS technologies, identify and fill gaps in technology roadmaps, and tighten imec’s engagement with SEMI in European workforce development efforts.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $41.4 billion for the month of November 2018, an increase of 9.8 percent from the November 2017 total of $37.7 billionand 1.1 percent less than the October 2018 total of $41.8 billion. Monthly sales are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor industry continues to post solid year-to-year sales increases, and year-to-date revenue through November has surpassed annual sales from all of 2017, but growth has slowed somewhat in recent months,” said John Neuffer, SIA president and CEO. “Year-to-year sales increased in November across all major regional markets, with the China market standing out with growth of 17 percent. Double-digit annual growth is expected for 2018 once December’s sales are tallied, with more modest growth projected for 2019.”

Regionally, year-to-year sales increased in China (17.4 percent), the Americas (8.8 percent), Europe (5.8 percent), Japan(5.6 percent), and Asia Pacific/All Other (4.4 percent). Compared with last month, sales were up in Asia Pacific/All Other (1.1 percent), Europe (0.5 percent), and Japan (0.4 percent), but down slightly in the Americas (-2.2 percent) and China(-2.7 percent).

UNSW researchers at the Centre of Excellence for Quantum Computation and Communication Technology (CQC2T) have shown for the first time that they can build atomic precision qubits in a 3D device – another major step towards a universal quantum computer.

The team of researchers, led by 2018 Australian of the Year and Director of CQC2T Professor Michelle Simmons, have demonstrated that they can extend their atomic qubit fabrication technique to multiple layers of a silicon crystal – achieving a critical component of the 3D chip architecture that they introduced to the world in 2015. This new research was published today in Nature Nanotechnology.

The group is the first to demonstrate the feasibility of an architecture that uses atomic-scale qubits aligned to control lines – which are essentially very narrow wires – inside a 3D design.

What’s more, the team was able to align the different layers in their 3D device with nanometer precision – and showed they could read out qubit states single shot, i.e. within one single measurement, with very high fidelity.

“This 3D device architecture is a significant advancement for atomic qubits in silicon,” says Professor Simmons. “To be able to constantly correct for errors in quantum calculations – an important milestone in our field – you have to be able to control many qubits in parallel.

“The only way to do this is to use a 3D architecture, so in 2015 we developed and patented a vertical crisscross architecture. However, there were still a series of challenges related to the fabrication of this multi-layered device. With this result we have now shown that engineering our approach in 3D is possible in the way we envisioned it a few years ago.”

In this paper, the team has demonstrated how to build a second control plane or layer on top of the first layer of qubits.

“It’s a highly complicated process, but in very simple terms, we built the first plane, and then optimized a technique to grow the second layer without impacting the structures in first layer,” explains CQC2T researcher and co-author, Dr Joris Keizer.

“In the past, critics would say that that’s not possible because the surface of the second layer gets very rough, and you wouldn’t be able to use our precision technique anymore – however, in this paper, we have shown that we can do it, contrary to expectations.”

The team also demonstrated that they can then align these multiple layers with nanometer precision.

“If you write something on the first silicon layer and then put a silicon layer on top, you still need to identify your location to align components on both layers. We have shown a technique that can achieve alignment within under 5 nanometers, which is quite extraordinary,” Dr Keizer says.

Lastly, the researchers were able to measure the qubit output of the 3D device with what’s called single shot – i.e. with one single, accurate measurement, rather than having to rely on averaging out millions of experiments. “This will further help us scale up faster,” Dr Keizer explains.

Towards commercialisation

Professor Simmons says that this research is a major milestone in the field.

“We are working systematically towards a large-scale architecture that will lead us to the eventual commercialisation of the technology.

“This is an important development in the field of quantum computing, but it’s also quite exciting for SQC,” says Professor Simmons, who is also the founder and a director of SQC.

Since May 2017, Australia’s first quantum computing company, Silicon Quantum Computing Pty Limited (SQC), has been working to create and commercialise a quantum computer based on a suite of intellectual property developed at CQC2T and its own proprietary intellectual property.

“While we are still at least a decade away from a large-scale quantum computer, the work of CQC2T remains at the forefront of innovation in this space. Concrete results such as these reaffirm our strong position internationally,” she concludes.