Category Archives: Device Architecture

The annual Symposia on VLSI Technology and Circuits, held together since 1987, provides an opportunity for the world’s top device technologists, circuit and system designers to exchange leading-edge research related to VLSI, with venues alternating between Japan and Hawaii. This year, the Symposia will be held at the Rihga Royal Hotel, Kyoto, Japan from June 5 to 8, 2017, with a fully-overlapping schedule for the first time. The full-day short courses and a new demo session are on Monday June 5, plenary talks are on the morning of Tuesday June 6, and the panel discussions are on the evening of Tuesday June 6.

This year marks the 37th anniversary for the Symposium on VLSI Technology, and the 31st for the Symposium on VLSI Circuits. The Circuits’ 30th anniversary ceremony will be held just before the panel discussions on the evening of June 6. The Symposia are followed by a special event on Friday June 9, the “International Forum on Singularity: Exponential X,” details of which will be announced shortly. In order to emphasize synergies between technology and circuits, the 2017 Symposia on VLSI Technology & Circuits offer the attendees an opportunity to participate in both the Technology and Circuits Symposia with a single registration.

Comment by Satoshi Inaba of Toshiba Memory Corporation, chair of the 2017 Symposium on VLSI Technology:

“This year, for the first time, we will have a three-day program overlapping with the 2017 Symposium on VLSI Circuits at the same location. In line with our common theme of “Harmonious Integration Toward Next Dimensions,” the various events during the two Symposia will stimulate harmonious co-optimization between device technology and circuit design. In addition, the Symposium on VLSI Technology will present 7nm CMOS, emerging memory, and 3D integration technologies. We expect the combination of activities in the two Symposia will generate new dimensions of engagement to maintain the continuous growth of our VLSI community.”

Comment by Masato Motomura of Hokkaido University, chair of the 2017 Symposium on VLSI Circuits:

“Our Symposium on VLSI Circuits will celebrate its 30th anniversary this year. We’ve introduced several changes to sustain the continued growth of this premier conference. The three-day overlap mentioned above allows us to start a new associated event, the “International Forum on Singularity: Exponential X,” in which distinguished presenters will talk about integrations beyond VLSI.”

Plenary Talks (June 6)
On Tuesday morning, two consecutive welcome and plenary sessions will be held in the same conference room. First, in the Technology plenary session, Dr. Takashi Tsutsui, Chief Scientist  & SVP, SoftBank Corporation, Japan, will talk about state-of-the-art 5G communication technology and its context up until 2020, and Dr. Fari Assaderaghi, CTO & SVP, NXP Semiconductors, USA, will talk about the latest IoT technology topics. In the following Circuits plenary session, Dr.  Takeshi Yukitake, CTO, Connected Solutions  Company,   Panasonic Corporation, Japan, will give a talk about the innovative solutions for society to which AI, robotics and IoT will lead us. The final talk of the plenary sessions will be given by Dr. Daniel Rosenband, Google, USA, about leading-edge self-driving car technology.

Focus Sessions (June 6, 7, 8)
Focus sessions for both Symposia will explore different aspects of the conference theme of harmonious integration. Technology focus sessions include “1D and 2D Atomic Thin Materials and Devices” and “Emerging Memory Technology,” addressing perspectives on the further development of 1D/2D devices, and the future direction of embedded memories. The Circuits focus sessions are “Ultra-Low Power Wireless Transceivers for IoT Systems” and “Advanced Sensing Systems,” examining the development of wireless systems and sensing systems. Joint focus sessions shared by the Technology and Circuits programs include “Ultra Low Power for IoT,” “Computing beyond von Neumann,” “Emerging Reliability Solutions,” and “Advanced Assembly,” enabling participants from each of the Symposia to share ideas on the cross-linkage of these critical technology areas.

Panel Discussions (June 6)
Panel discussions provide an opportunity for Symposia participants to interact with leading industry experts in examining critical issues surrounding major industry developments.

“Transistor Future; How Does It Evolve after FinFET Era?” (Tech. Panel)
It is uncertain whether FinFETs can satisfy performance requirements beyond 5nm. Alternative FET structures such as nano-sheets/wires or 2D channels may emerge to secure scaling, but these devices struggle with drive current improvement. To maintain the area scaling, 3D monolithic structures may emerge, but they also have some issues (cost, thermal budget, Joule heating, etc.). A FET roadmap for the post-FinFET era will be discussed by device experts.

“How Will We Survive the Post-Scaling Era?” (Joint Panel)
For many decades the semiconductor industry has enjoyed the benefits of scaling. While we have largely maintained area scaling, it has been difficult to obtain even modest node-to-node improvements in performance and power. What happens when scaling slows to the point that it has, for practical purposes, stopped? How will we survive the post-scaling era? The panel of experts, spanning VLSI technology, circuits, and business, looks at the difficulties ahead and potential ways forward.

“The Most Important Circuits of 2037” (Circuit Panel)
Many innovative circuit design techniques have been presented during the history of 30 years of the Symposium on VLSI Circuits, but what kinds of VLSI circuits will be presented, and for what kind of applications, 20 years from now? Answers will be revealed by a mix of young specialists and senior specialists from across the circuit  spectrum.

Full-day Short Courses (June 5)
VLSI Technology Short Course: “Technology Enablers for 5nm and the Next Wave of Integration.” This short course will introduce various technology innovations for enabling the 5nm node and a new integration scheme for the Internet of Things and AI era. The course comprises eight lectures given by distinguished experts in their respective fields, covering CMOS device technology, design and technology co-optimization (DTCO), interconnect, 2.5D/3D integration, scaled analog/RF, embedded memory, and in-memory computing.

VLSI Circuit Short Course: Two circuit short courses will be held. First, “Machine Learning for Circuit Designers” introduces the audience to the basics and to recent developments in machine learning, gives an overview of promising applications, and provides insight into state-of-the-art implementation techniques. Second, “Integrated Circuits for Smart Connected Cars and Automated Driving” demystifies recent advances in automotive electronics covering wireless/wireline communication, powertrain, and various sensors, from the fundamentals to future trends.

Symposia Demo Session (June 5)
The newly-created demo session will provide an opportunity for in-depth interaction with authors of outstanding papers selected from both Technology and Circuits sessions. More than 10 demonstrations will illustrate technological concepts and analyses, table-top real-time presentations of new device characterization, their chip operation highlighting key results, and systems showcasing potential applications for circuit-level innovations.

Sponsoring Organizations
The Symposium on VLSI Technology is sponsored by the Japan Society of Applied Physics and the IEEE Electron Devices Society, in cooperation with the IEEE Solid-State Circuits Society.

The Symposium on VLSI Circuits is sponsored by the Japan Society of Applied Physics and the IEEE Solid-State Circuits Society, in cooperation with the Institute of Electronics, Information and Communication Engineers.

Further information, registration, and a complete program, visit: http://www.vlsisymposium.org.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $30.9 billion for the month of March 2017, an increase of 18.1 percent compared to the March 2016 total of $26.2 billion and 1.6 percent more than the February 2017 total of $30.4 billion. Sales from the first quarter of 2017 were $92.6 billion, up 18.1 percent compared to the first quarter of 2016 but down 0.4 percent compared to the last quarter of 2016. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales saw solid sales growth in March, increasing sharply compared to last year and more modestly compared to last month,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Global sales are up 18 percent compared to last year, the largest increase since October 2010, with all major regional markets posting double-digit year-to-year growth. All major semiconductor product categories also experienced year-to-year growth, with memory products continuing to lead the way.”

Year-to-year sales increased across all regions: China (26.7 percent), the Americas (21.9 percent), Asia Pacific/All Other (11.9 percent), Europe (11.1 percent), and Japan (10.7 percent). Month-to-month sales increased in Europe (5.0 percent), Japan (3.6 percent), Asia Pacific/All Other (2.9 percent), and China (0.2 percent), but decreased slightly in the Americas (-0.5 percent).

March 2017

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.99

5.96

-0.5%

Europe

2.82

2.96

5.0%

Japan

2.77

2.87

3.6%

China

10.05

10.07

0.2%

Asia Pacific/All Other

8.77

9.02

2.9%

Total

30.39

30.88

1.6%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

4.89

5.96

21.9%

Europe

2.67

2.96

11.1%

Japan

2.59

2.87

10.7%

China

7.95

10.07

26.7%

Asia Pacific/All Other

8.05

9.02

11.9%

Total

26.15

30.88

18.1%

Three-Month-Moving Average Sales

Market

Oct/Nov/Dec

Jan/Feb/Mar

% Change

Americas

6.33

5.96

-5.8%

Europe

2.80

2.96

5.6%

Japan

2.84

2.87

0.9%

China

10.17

10.07

-0.9%

Asia Pacific/All Other

8.86

9.02

1.7%

Total

31.01

30.88

-0.4%

After nearly a quarter of a century, the semiconductor industry could see a new #1 supplier in 2Q17. If memory market prices continue to hold or increase through 2Q17 and the balance of this year, Samsung could charge into the top spot and displace Intel, which has held the #1 ranking since 1993. Using the mid range sales guidance set by Intel for 2Q17, and a modest, yet typical, 2Q sales increase of 7.5% for Samsung, the South Korean supplier would unseat Intel as the world’s leading semiconductor supplier in 2Q17 (Figure 1).  If achieved, this would mark a milestone achievement not only for Samsung, specifically, but for all other competing semiconductor producers who have tried for years to supplant Intel as the world’s largest supplier.  In 1Q16, Intel’s sales were 40% greater than Samsung’s, but in just over a year’s time, that lead may be erased and Intel may find itself trailing in quarterly sales.

samsung 1

Samsung’s big increase in sales has been driven by an amazing rise in DRAM and NAND flash average selling prices (Figure 2).  IC Insights expects that the tremendous gains in DRAM and NAND flash pricing experienced through 2016 and into the first quarter of 2017 will begin to cool in the second half of the year, but there remains solid upside potential to IC Insights’ current forecast of 39% growth for the 2017 DRAM market and 25% growth in the NAND flash market.

samsung 2

As shown in Figure 3, Intel has been locked in as the world’s top semiconductor manufacturer since 1993 when it introduced its x486 processor and soon thereafter, its revolutionary Pentium processor, which sent sales of personal computers soaring to new heights.

samsung 3

Over the past 24 years, some companies have narrowed the sales gap between themselves and Intel, but never have they surpassed the MPU giant.  If memory prices don’t tank in the second half of this year, it’s quite possible that Samsung could displace Intel in full-year semiconductor sales results as well.  Presently, both companies are headed for about $60.0 billion in 2017 semiconductor sales.

MRAM lowers system power


April 28, 2017

BY BARRY HOBERMAN, CEO, Spin Transfer Technologies

ST-MRAM (spin-transfer magnetic RAM) is an extremely promising new technology with the potential to replace major segments of the market for flash, SRAM, and DRAM semiconductors in applications such as mobile products, automotive, IoT, and data storage. With ST MRAM technology, data is stored in minute magnetic nodes—a physical mechanism different from traditional non-volatile memory (NVM). MRAM technology fundamentally requires less energy to use, and features like byte-addressability that further contributes to energy efficiency.

Embedded MRAM primarily fills the role that is currently handled by embedded NOR flash: storage of code and data that must survive when the power is removed. Indeed, MRAM is challenging NOR flash due to overall lower power and byte-addressability.

Energy consumption starts with voltages and currents: their product yields the power of the device – that is, the rate of energy consumption. Lower voltages and currents mean lower power. Energy consumed is determined by how long that rate is sustained – power multiplied by operating time. Therefore speed, the ability to finish a job sooner, also contributes to lower energy consumption especially when devices can enter sleep mode after tasks are complete.

To understand how NOR flash consumes energy, we need to look at how it operates. Let’s say we have a 32-bit word whose value we wish to update. With NOR flash, you can store data only in locations that have been freshly erased. This means you have to erase the old value before you can write the new value.

But there’s a more significant challenge; you can’t just erase those 32 bits. NOR flash can only be erased in sectors. So, in order to update those 32 bits, you have to find a new place to write them. This means creating and maintaining pointers to keep track of stored data since, with each update, the data location will move. Eventually, you run out of fresh space, and must perform garbage collection to free up the space used by all the out-of-date instances.

By contrast, MRAM has none of these requirements. Because it is byte-addressable, you can read and write just as you would with SRAM. Those 32 bits that needed updating? You simply write the new value over the old value. MRAM consumes less energy for a number of reasons:

No erase before writing: NOR flash erasure is very slow. With MRAM, there’s really no notion of erasing data; you’re either writing 1s or 0s, in any combination. The need to erase is a key contributor to the energy consumption of a NOR flash device.
Faster, lower-power writing: Not only can MRAM devices be written more quickly than NOR flash (even without considering erasure), the power while writing is also lower. The fact that you can complete the operation sooner means you can put the device to sleep sooner, yet another advantage to lowering energy.

No charge pumps: NOR flash, unlike MRAM, needs high voltages internally – much higher than the voltages at the external power pins. Those voltages are generated by internal charge pumps. Ideally, power would stay the same, but real charge pumps aren’t ideal; their inefficiency means lost energy.
Charge pumps also take longer to power up, and settle after a sleeping device awakens. This increases wake-up times dramatically. MRAM wakes up in nanoseconds to micro- seconds; NOR flash in milliseconds.

No complex storage management: The lack of byte-addressability in NOR flash creates complexity that increases the time to store data and code. Data tables must be maintained, along with the occasional garbage collection. The CPU, or some other circuit, must manage this data storage. These other devices consume energy, so the more time spent managing data, the more energy consumed. This energy consumption doesn’t apply to MRAM technology.

Mixed read/write stream: NOR flash storage operations, due to complexity, mean long lock-out times during writes. No data reading is permitted during these times. If certain pieces of data are quickly needed, then further management may be required to anticipate this ahead of a data write, so the data can be cached. By contrast, MRAM can handle a stream of operations – reads and writes – in any combination.

Staggered writing: Data can be stored 32 bits at a time. While overall energy consumption in doing this is lower for MRAM than for NOR flash, it still might challenge the peak current capabilities of a battery-powered device. The ability for MRAM to break the write into four successive single-byte writes, a feature known as “staggered write,” reduces current demands on the battery.

Micron Technology, Inc. (NASDAQ:MU) announced today that the board of directors has appointed Sanjay Mehrotra as president and chief executive officer and a member of the board of directors, effective May 8, 2017. Mehrotra succeeds Mark Durcan and joins Micron at a time of increasing opportunity for memory and storage technologies and solutions as the key enablers for the next-generation of computing architectures.

“Sanjay has an outstanding track record of business success and exceptional knowledge of the memory and storage industry,” said Robert E. Switz, chairman of the board of directors and a member of the CEO selection committee. “His experience in markets ranging from consumer to enterprise make him uniquely qualified to lead Micron into the future.”

Mehrotra was a co-founder of SanDisk and served as its president and CEO from 2011 to 2016. He drove the growth of the company from a start-up in 1988 to an industry-leading Fortune 500 company with revenues that reached $6.6 billion, and ultimately culminated in a sale for $16 billion to Western Digital Corporation in 2016.

His team pioneered a diversified and comprehensive portfolio of flash storage solutions that included removable products, embedded mobile solutions, client and enterprise solid state drives and innovative enterprise system solutions. He also initiated and guided a highly successful 17-year joint venture partnership with Toshiba in NAND Flash memory technology development and manufacturing.  In addition, he established and ran key manufacturing operations in China, Taiwan, Japan and Malaysia.

“Innovation in memory and storage technology is enabling new products, improved customer experience and growth across multiple markets,” said Mehrotra. “Micron is at the forefront of driving these innovations, and I am thrilled to have the opportunity to lead such a talented global team.”

Durcan will step down as CEO and from the Micron board of directors effective May 8, 2017, but will serve as an advisor to the company until early August. “Mark has made an immense contribution to Micron and to the semiconductor industry at large over his 32 years at the company and 5 years as CEO,” noted Switz. “We wish him all the best in his future endeavors.”

Strong growth in MCUs for IoT applications and suppliers jockeying for marketshare in this IC segment have resulted in several major acquisitions that changed the pecking order of MCU leaders in 2016, according to data released in IC Insights’ April Update to The McClean Report, which was released earlier this month. Figure 1 ranks the largest MCU suppliers in 2016 by dollar-sales volume.  Among the top MCU suppliers shown, NXP, Microchip, and Cypress Semiconductor moved up in the sales ranking during 2016 with strong increases in revenues, which were driven by acquisitions of IC companies that sold microcontrollers. Meanwhile, those suppliers not making significant acquisitions in microcontrollers posted low-single digit percentage increases or declines in MCU sales in 2016.

Figure 1

Figure 1

Although overall growth in microcontrollers has wobbled and stalled in the past couple years, MCUs remain at the epicenter of tremendous growth in the Internet of Things, automotive, robotics, embedded applications and other emerging systems.   Major MCU suppliers have been improving their portfolios to address many of these key markets.  Part of that improvement process has included merging and acquiring competitors in order to gain a quick foothold into these developing markets.

In 2016, NXP in the Netherlands overtook Renesas Electronics in Japan as the world’s largest microcontroller supplier with MCU revenues climbing 116% following its $11.6 billion purchase of U.S.-based Freescale Semiconductor in December 2015.  Prior to its acquisition, Freescale was ranked second in MCUs and was catching up with Renesas in microcontroller sales with only $210 million separating the two companies in 2015 versus about a $1 billion gap in 2014.  Renesas suffered a 19% drop in MCU dollar sales in 2015 (largely due to the weak yen exchange rate in that year but also because of the continued fallout from Japan’s troubled economy).  In 2016, Renesas’ fall in MCU sales eased, dropping 4% to nearly $2.5 billion, or about 16% of the total microcontroller market.  In 2011, Renesas’ MCU marketshare was 33% of worldwide microcontroller sales.

The Freescale acquisition moved NXP from sixth in the 2015 MCU ranking to the top spot in 2016 with a marketshare of 19% ($2.9 billion).  About three-quarters of NXP’s 2015 microcontroller sales were 8-bit and 16-bit MCUs used in smartcards.  After Freescale’s business was merged into NXP, smartcard MCUs accounted for a little over one-quarter of the company’s total microcontroller sales in 2016. MCUs developed and introduced by Freescale are aimed at a wide range of embedded control applications, including significant amounts in automotive systems.  NXP and Freescale both have developed extensive 32-bit MCUs with Cortex-M CPU design cores licensed from ARM in the U.K.

U.S.-based Microchip Technology climbed from fifth in the 2015 MCU ranking to third in 2016 with sales increasing 50% to $2.0 billion following its $3.4 billion acquisition of Atmel in 2Q16.  U.S.-based Atmel was ranked ninth in MCU sales in 2015 ($808 million).  Prior to buying Atmel, Microchip had been the only major MCU supplier not licensing ARM CPU technology.  For about 10-years, Microchip has developed and sold 32-bit MCUs, based on a RISC-processor architecture developed by MIPS Technologies (which is now owned by Imagination Technology in the U.K.,  a rival of ARM).  Six months after completing the Atmel acquisition, Microchip said it would expand both its MIPS-based PIC32 MCU product line and Atmel’s ARM-based SAM series.  Microchip has promised to “remain core agnostic, fitting the best solution with the right customer and for the right application.”

Meanwhile, Cypress in Silicon Valley moved into eighth place in the MCU ranking with sales increasing 15% in 2016 to about $622 million.  Cypress boosted its presence in MCUs when it acquired Spansion for about $5.0 billion in stock in March 2015.  Originally spun out of Advanced Micro Devices as a NOR flash memory supplier, Spansion had purchased Fujitsu Semiconductor’s Microcontroller and Analog Business in 2013 for $110 million as part of its efforts to expand beyond nonvolatile storage ICs. Spansion also licensed ARM’s 32-bit CPU cores for microcontrollers in 2013.  Cypress’ increase in microcontroller sales was partly a result of having a full year of revenue from Spansion’s MCU business but also growth in the company’s programmable system-on-chip (PSoC) products, which combine microcontroller functionality with user-configurable peripherals of mixed-signal and digital functions that are targeted at end-use applications.

The biggest decline in the MCU leader list was posted by Samsung, which saw its sales drop 14% in 2016, primarily because of weakness in the smartcard microcontroller market.  Samsung sells MCUs to OEMs but also serves in-house needs for its own brands of consumer electronics, computers, and communications systems (i.e., smartphones).

With its unique characteristics, FD-SOI is generating increasingly strong interest from major players in the semiconductor ecosystem for a very wide range of markets.

BY MANUEL SELLIER, Soitec, Bernin (Grenoble), France

Fully depleted silicon-on-insulator or FD-SOI is the only technology bringing together two substantial characteristics of CMOS transistors: 2D planar transistor structure and fully depleted operation. It relies on a unique substrate whose layer thicknesses are controlled at the atomic scale. FD-SOI offers remarkable transistor performance with one of the best power, performance, area and cost tradeoffs (PPAC) among all advanced CMOS technologies. In addition, FD-SOI has numerous other unique advantages including back bias ability, very good transistor matching, near threshold supply capability, ultra-low sensitivity to radiation and very high intrinsic transistor speed, which allows it to handle mmWave frequencies.

All these key features are progressively making FD-SOI a de facto technology for many applications including entry-level application processors for smartphones, system-on- chip (SoC) devices for autonomous driving and IoT, and all mmWave applications such as 5G transceivers and radar systems for automotive electronics.

FD-SOI technology is supported by multiple foundries and IDMs with full technology offerings now available for the 28nm and 22nm nodes and emerging for the 65nm and 12nm nodes. With this global ecosystem in place, FD-SOI is ready for applications development for diversified markets.
There are several striking characteristics of FD-SOI substrates that give this technology unique advantages. This article summarizes the latest advances and the various elements of the global ecosystem that supportwidespread implementation of FD-SOI as well as the applications that most benefit from it.

The heart of FD-SOI

Everything in FD-SOI technology starts with the substrate. The substrate directly defines the transistor architecture, as shown in FIGURE 1. To allow the fully depleted operation of transistors, the thickness of the top silicon layer defining the device channel represents a real challenge, with the thickness target typically around 60 Å or 11 atomic layers. Given the consumption of silicon material during device fabrication, a 120 Å incoming top silicon specification is usually required by foundries. Uniformity is another very challenging specification needed to keep transistor variability as low as possible. Uniformity of +/-5 Å or 1 atomic layer is typically considered essential. Buried oxide (BOx) thickness also must be very thin – around 20nm – to maximize electrostatic control in the transistor channel due to the ground plane effect.

Screen Shot 2017-04-27 at 12.01.02 PM

Manufacturing a 300mm piece of crystalline silicon with a thickness specification as low as 11 +/-1 atomic layers is understandably difficult. Ten years ago, it sounded unachievable so people studied other paths to enable fully depleted transistors [1]. But it is now possible.

Fabrication relies on the well-known Smart Cut TM process (FIGURE 2). As shown, wafer A first undergoes an oxidation step followed by high-dose ion implantation, creating a weakened layer just beneath the surface. After careful cleaning steps, wafer A is bonded to wafer B through molecular-bonding technology. Splitting is then induced at the precise location of the weakened zone of wafer A. Finally, the formed SOI wafer is subjected to other smoothing process steps to achieve the targeted thickness specification. It is noteworthy that high-quality wafer A can be recycled for further reuse, making Smart Cut the most cost- effective solution for SOI manufacturing.

Screen Shot 2017-04-27 at 12.01.10 PM

The FD-SOI substrate-manufacturing process is now fully mature. In particular, thickness uniformity is very well controlled at all levels, from transistor to wafer, as shown in FIGURE 3. This ensures a very low level of transistor variability.

Screen Shot 2017-04-27 at 12.01.22 PM

When less is more

The way of getting more performance out of silicon below 28nm node adds more complexity to the manufacturing process. Consequently, as illustrated in FIGURE 4, the smaller nodes get, the greater number of masks are needed to create chips. This increases manufacturing costs as well as other non-recurring engineering costs including design flow, design verification, mask sets and more.

Screen Shot 2017-04-27 at 12.01.32 PM

On the other hand, FD-SOI is a simple technology from a manufacturing standpoint. In fact, it offers more perfor- mance while decreasing the manufacturing process complexity. Most of the channel engineering work is actually done directly at the substrate level, making FD-SOI easier to implement than bulk silicon, as major foundries have reported [2] [3].

The next level of transistor performance

In addition to simpler manufacturing, FD-SOI offers other substantial benefits, as depicted below and summarized in FIGURE 5.

Screen Shot 2017-04-27 at 12.01.46 PM Screen Shot 2017-04-27 at 12.01.53 PM

1. Better design flexibility through body bias

The thin BOx of FD-SOI not only enhances electro- static control of the channel, but also makes it possible to completely tune the threshold voltage through back biasing. All the complex Vth adjustment techniques through channel doping can be avoided. Low, mid-range and high Vth can be achieved simply through back-gate polarization. The thin BOx behaves like a real second gate and, most importantly, it can be used dynami- cally. This means that the same functional block can operate under high or low power, on demand. Back bias potential is huge: selective body bias for critical path improvements [4], process variation compensation [5] and reliability drift compensation [6]. Full back biasing is a very unique feature, only achievable with SOI on thin BOx technology.

2. Power-performance-area-cost tradeoff: Best PPAC of all planar technologies.

Thanks to simpler manufacturing, better control of random mismatch, minimizing of junction leakage and capacitances, enhanced electrostatic control through fully depleted transistor operation and the possibility of tuning body bias, FD-SOI technology presents the best power- performance-area-cost tradeoff (PPAC) among all planar technologies.

3. Ultra-low power through near-threshold supply voltage

Almost all CMOS technologies achieve their best energy efficiency – i.e., the lowest amount of energy per function, regardless of the frequency – at around 0.4 V supply voltage, often referred to as Vdd [7]. At this level of supply voltage, variability management is a real challenge. Thanks to body bias and to its intrinsic low-variability characteristics, FD-SOI can achieve very low supply voltages. More generally, the ability to lower the supply voltage, although not necessarily as low as 0.4 V, is a real challenge in many applications in which power is a greater challenge than performance. Given the fact that dynamic power scales with Vdd2, a technology like FD-SOI that is capable of strong power savings through tremendous supply voltage reduction presents a unique advantage.

4. Best RF-CMOS technology with almost 2 times maximum frequency over 3D devices

Integrating as many analog/RF functions as possible into a single RF-CMOS silicon platform is becoming an increasingly important issue in many markets for obvious cost and power reasons. However, one limitation of RF-CMOS platforms is the limited ability to increase frequency, especially in the mmWave spectrum (30 GHz and above). This is a bigger issue with 3D devices such as FinFETs, which must carry very strong parasitic capaci- tances due to their 3D structures [8]. As a result, SiGe- Bipolar platforms are often used for this frequency range. FD-SOI is a planar technology and, as such, it should not suffer from the limitations of 3D devices. Ft/Fmax in the range of 325-350 GHz have been reported [3], allowing full usage of the mmWave spectrum up to 100 GHz and giving FD-SOI RF-CMOS platforms a bright future in many applications.

5. Enhanced reliability

Low sensitivity to high-energy particles is another key characteristic of FD-SOI. High-energy particles can interact with silicon and generate a significant amount of charges capable of flipping transistor logic state, thus increasing the soft errors rate (SER). FD-SOI devices are completely isolated from the substrate due to the BOx layer. This means that any charge generated in the substrate is unlikely to modify the device logic state. In short, FD-SOI is much less sensitive to SER [9]. This has very important consequences for safety-critical devices such as autonomous car systems.

6. Outstanding analog transistor characteristics

Often, analog designers have to make their designs work with more and more degraded transistors as technology shrinks. Meeting speed, noise, power, leakage and variability requirements is increas- ingly challenging. By providing a transistor with improved matching, gain and parasitic, FD-SOI can greatly simplify device design [10]. Moreover, the back bias has potential for the design of many new analog structures [11].

FD-SOI’s growing use at foundries

Some of the most pioneering work with FD-SOI has been done at semiconductor foundries around the world.

STMicroelectronics adopted FD-SOI technology in 2012 [12] and started several projects. The company demonstrated an ARM-based application processor for smart-phones with 3 GHz+ operating frequency on 28nm FD-SOI [13]. The technology is now used at STMicroelectronics for many diversified markets [14] [15].

In 2014, Samsung announced the adoption of 28nm FD-SOI technology for its foundry division [15]. Mass production maturity was reached in 2016 [2], and the first product release was announced recently [16] [17].

In 2015, GLOBALFOUNDRIES developed a 22nm FD-SOI technology called 22FDX [18], which it positioned as offering the best performance/cost ratio. This FD-SOI technology platform achieved performance close to 16nm/14nm FinFET at a cost similar to 28nm bulk silicon [19]. The first commercial product was announced in February 2017 by GLOBALFOUNDRIES and Dream Chip Technologies [20]. GLOBALFOUNDRIES’ technology is now almost fully qualified, with volume ramp-up expected this year.

In Asia, the Chinese foundry Huali has announced its intention to include 22nm FD-SOI technology in its fab2 plan [21], offering the Chinese market greater access to FD-SOI technology.

In Japan, Renesas’ experience with FD-SOI includes work on a very low-power FD-SOI technology called silicon- on-thin-BOx (SOTB), which targets low-power MCU markets. This technology has been supported by the LEAP initiative (Low-Power Electronics Association and Project) and is now available in 65nm. Renesas has reported very low-power consumption with this platform, as small as a tenth of that achieved using bulk silicon.

IP/CAD status and roadmap

The design ecosystem is well established for 28nm FD-SOI with complete libraries and foundation IP and growing at a fast pace for 22nm technology. EDA companies are on board and developing IP ported to FD-SOI.

In September 2016, GLOBALFOUNDRIES announced a new partner program called FDXceleratorTM to facil- itate 22FDX SoC design and reduce time to market for its customers including Synopsys, Cadence, INVECAS, VeriSilicon, CEA-Leti, Dream Chip and Encore Semi [22]. In December 2016, the foundry announced the addition of eight new partners to its growing FDXcel- erator program including Advanced Semiconductor Engineering (ASE Group), Amkor Technology, Infosys, Mentor Graphics, Rambus, Sasken, Sonics and Quick- Logic [23].

As for the technology roadmap, FD-SOI is available on a wide range of technology nodes from 65nm to 12nm with visibility down to 7nm. Building on the success of its 22FDX offering, in 2016 GLOBALFOUNDRIES unveiled a new 12nm FD-SOI semiconductor technology called 12FDX [24]. Staying with fully depleted planar processing allows the foundry to take advantage of the low parasitic capacitance, avoid the complex lithog- raphy steps required by equivalent 3D transistors, and leverage back biasing to boost transistor performance, especially at low supply voltages. Customer product tape-outs are expected to begin by the end of 2017.

Leti, which pioneered FD-SOI development 15 years ago, worked with GLOBALFOUNDRIES on the 22FDX and 12FDX platforms. The organization recently developed test devices on 10nm FD-SOI technology and produced models for 10nm and 7nm on FD-SOI. Leti strongly believes that FD-SOI can be scaled down to 7nm.

Both Samsung and GLOBALFOUNDRIES plan to have embedded non-volatile memory integrated into their FD-SOI technology platforms by 2018 [2] [3].

FD-SOI traction in power and analog/RF integration ThankstothegrowingmaturityoftheFD-SOIecosystem, there is now a wide range of applications seeing strong differentiation possibilities through FD-SOI. These include single-chip solutions for entry-level mobile communications, general purpose application processors, image signal processors, SoC for set-top boxes, embedded computer vision, microcontrollers, mixed-signal applications such as transceivers, GPS/satellite receivers, wi-fi/ BT combos and mmWave radar systems.

For all these applications, power budget is typically very limited and must be balanced with performance targets. A good example of this can be found in embedded computing applications such as ADAS, where designers must constantly find compromises to achieve the required performance with a very limited power budget, typically around 3 W. For all embedded computing applications, FD-SOI – and its ability to run on very low supply voltages – is gaining momentum as the reference technology.

In addition, RF/analog integration is often key for these applications. Having best-in-class RF-CMOS technology available on the same silicon die as the digital parts is a unique advantage of FD-SOI. It opens up possibilities for single-chip solutions covering a wide range of functions. This is particularly advantageous in entry-level markets such as low-end mobile, where the price pressure is so great that integration must be pushed to its limits, or in mmWave applications including radar and 5G transceivers, where the mmWave RF functions can be integrated on the same die as the computing functions.

A new wave of ground-breaking products

The list of FD-SOI-based products is increasing at a very fast pace, with multiple product announcements over the past months.

In September 2016, Huami (a Xiaomi partner company) introduced a new fitness smartwatch that includes a FD-SOI-based global positioning system (GPS) chip demonstrating record energy efficiency (FIGURE 6) [25]. The chip allows the watch to reach an unsurpassed battery life of 35 hours with the GPS turned on, which represents two to five times more than today’s similar devices. The chip, revealed in February 2016 at the International Solid- State Circuits Conference (ISSCC) in San Francisco [27], dramatically lowers power usage and opens the door for always-on GPS applications in smartwatches, smart-phones, drones and a large number of devices for the IoT.

Also in 2016, Mobileye posted on its website that its next EyeQ4 product family dedicated to level3 autonomous driving will be based on FD-SOI technology [26] (FIGURE 7).

Screen Shot 2017-04-27 at 12.02.09 PM

In March 2017, NXP released two general-purpose processor families (i.MX7ULP and i.M8X) [16] [17] based on Samsung’s 28FDS FD-SOI technology for ultra-low power consumption and rich graphics in battery-powered applications (see NXP roadmap FIGURE 8). NXP reported a deep-sleep suspended power consumption of 15 μW or less for its i.MX7ULP product, 17 times less in comparison to previous low-power bulk devices, while the dynamic power efficiency improved by 50 percent. This high-performance, low-power solution is optimized for customers developing IoT, home control, wearable and other applications that spend a significant amount of time in standby mode with short bursts of performance-intense activity that require exceptional graphics processing.

Screen Shot 2017-04-27 at 12.02.17 PM

In March 2017, Eutelsat Communications and STMicroelectronics announced a new-generation SoC for interactive applications that represents a step down in the overall cost of interactive satellite terminals while reducing power consumption [14].

On the 22nm side, Dream Chip announced the industry’s first 22nm FD-SOI product for a new ADAS SoC for automotive computer-vision applications [20]. The SoC device (FIGURE 9) offers high- performance image acquisition and processing capabilities and supports convolutional neural network (CNN) vision workloads to meet the demand for complex automotive object detection and processing.

Screen Shot 2017-04-27 at 12.02.27 PM

The 22nm FD-SOI product portfolio is expected to grow significantly in the coming year as the technology ramps up.

Adding fabs to meet overall FD-SOI demand

Faced with the growing interest of FD-SOI, particularly in China, foundries are organizing themselves to build up enough production capacity. In February 2017, GLOBALFOUNDRIES announced plans to expand the capacity of its Fab 1 facility in Dresden by 40 percent by 2020. Dresden will continue to be the center for FDX technology development [27].

In China, GLOBALFOUNDRIES and the Chengdu munici- pality have announced a partnership to build a fab. The partners plan to establish a 300mm fab to support the growth of the Chinese semiconductor market and to meet accelerating global customer demand for 22FDX [27]. The fab will begin producing mainstream process technologies in 2018 and then focus on manufacturing GLOBALFOUNDRIES’ commercially available 22FDX process technology, with volume production expected to start in 2019.

With these two announcements, GLOBALFOUNDRIES will have a future production capacity of more than 2 million FD-SOI wafers per year.

Regarding FD-SOI substrate manufacturing capacity, Soitec owns one 300mm fab in France and has another one in Singapore (currently in standby mode) with a combined global capacity of 1.5 million wafers per year (for manufacturing FD-SOI and other emerging SOI products). The company has plans to go beyond that to meet additional customer demand.

Conclusion

Growing interest in FD-SOI reflects today’s new paradigm for semiconductor technologies. Customers are demanding for more computing capability with drastically reduced power consumption, enabled by enhanced analog/RF integration. With its unique characteristics, FD-SOI is generating increasingly strong interest from major players in the semiconductor ecosystem for a very wide range of markets, especially for embedded computing applications. FD-SOI is now a mainstream technology, which device designers are leveraging for key competitive advantages.

Acknowledgements

The author would like to warmly thank the Soitec team (Christophe Maleville, Bich-Yen Nguyen, Thomas Piliszczuk, Alexandra Givert, and Camille Dufour) for their valuable contribution and constructive discussions.

References

1. H. Chenming, “FinFET-a self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Transactions on Electron Devices, p. 2320–2325, December 2000.
2. Y. Jeon (SAMSUNG), “The industry’s first mass-produced FD-SOI technology for the IoT era, with single design platform benefits,” in SOI Industry Consortium workshop, Tokyo, 2016.
3. J. Schaeffer (GLOBALFOUNDRIES), “FDX Rising,” in GLOBAL- FOUNDRIES Technology Conference, San Jose, 2016.
4. W. Abbey (ARM), “Realize the potential of FD-SOI,” in SOI Industry Consortium workshop, San Jose, 2016.
5. P. Flatresse (ST), “FD-SOI ULV, Body Biasing & Demonstrators,” in LETI days FDSOICE Workshop, GRENOBLE, 2015.
6. C. Ndiaye (ST), “Performance vs. reliability adaptive body bias scheme in 28nm & 14nm UTBB FD-SOI nodes,” Microelectronics Reliability, 2016.
7. B. Zha, in VLSI symposium, 2006.
8. IMEC, chez VLSI Design, 2010.
9. P. Roche (ST), “Technology downscaling worsening radiation effects in bulk: SOI to the rescue,” in IEDM, 2013.
10. G. Cesana (ST), “Advances in Applications and Ecosystem for the FD-SOI Technology,” in LETI days FDSOICE Workshop, GRENOBLE, 2015.
11. A. Cathelin (ST), “On the usage of FBB for inverter-based Analog and RF 28nm UTBB FD-SOI circuits : example of a 450MHz Gm-C filter with IIP3> 1dBv over a 0.7-1V power supply,” in LETI Days FDSOICE Workshop, GRENOBLE, 2015.
12. STMicroelectronics Announces Its 28nm FD-SOI Technology Is Ready for Manufacturing in Its Leading-Edge Crolles Fab, ST Press Release, 2012.
13. ST-Ericsson brings PC speeds to mobile devices: First 3Ghz smartphone prototype demo at Mobile World Congress, STE Press Release, February 20, 2013.
14. EUTELSAT and STMicroelectronics announce low-cost, low-power, system-on-chip for interactive satellite terminals, EUTELSAT Press Release, March 8, 2017.
15. G. Desoli (ST), «A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systems,» chez International Solid-State Circuits Conference (ISSCC), 2017.
16. Samsung and STMicroelectronics Sign Strategic Agreement to Expand 28nm FD-SOI Technology, Samsung/STMicroelectronics Press Release, May 14, 2014.
17. NXP Taps into FD-SOI Technology to Enable the Industry’s Lowest Power General Purpose Applications Processors, NXP Press Release, March 13, 2017.
18. NXP Delivers Increased Safety, Reliability and Scalability to Industrial Applications with New i.MX 8X Processors, NXP Press Release, March 14, 2017.
19. GLOBALFOUNDRIES Launches Industry’s First 22nm FD-SOI Technology Platform, GLOBALFOUNDRIES Press Release, July 13, 2015.
20. S. Jha (GLOBALFOUNDRIES), “The Right Technology at the Right Time,” in SOI Industry Consortium workshop, Shanghai, 2015.
21. Dream Chip Technologies Presents First 22nm FD-SOI Silicon of New Automotive Driver Assistance SoC, DREAM CHIP Press Release, February 27, 2017.
22. R. Merritt, “China Defends Big Chip Bet – Inside Huali’s $5.9 billion bet on Fab 2,” EETIMES, January 12, 2017.
23. GLOBALFOUNDRIES Unveils Ecosystem Partner Program to Accelerate Innovation for Tomorrow’s Connected Systems, GLOBALFOUNDRIES Press Release, September 8, 2016.
24. GLOBALFOUNDRIES Expands Partner Program to Speed Time- to-Market of FDXTM Solutions, GLOBALFOUNDRIES Press Release, December 15, 2016. www.solid-state.com
25. GLOBALFOUNDRIES Extends FDXTM Roadmap with 12nm FD-SOI Technology, GLOBALFOUNDRIES Press Release, September 8, 2016.
26. J. Yoshida, «Sony-Inside Huami Watch: Is It Time for FD-SOI?,» October 4, 2016.
27. K. Yamamoto (SONY), “A 0.7V 1.5-to-2.3mW GNSS receiver with 2.5-to-3.8dB NF in 28nm FD-SOI,” in International Solid-State Circuits Conference (ISSCC), 2016.
28. Mobileye, “The Evolution of EyeQ,” [Online]. Available: http:// www.mobileye.com/our-technology/evolution-eyeq-chip/. [Accessed 29 March 2017].
29. GLOBALFOUNDRIES Expands to Meet Worldwide Customer Demand, GLOBALFOUNDRIES Press Release, February 9, 2017.

The new Samsung Galaxy S8 equipped with 64 gigabytes (GB) of NAND flash memory carries a bill of materials (BOM) cost that comes out to US$301.60, much higher than for previous versions of the company’s smartphones, according to a preliminary estimate from IHS Markit (Nasdaq: INFO).

After $5.90 in basic manufacturing costs are added, Samsung’s total cost to make the Galaxy S8 rises to $307.50; the unsubsidized price for a 64GB Galaxy S8 starts at around $720. The preliminary estimated total at this point is $43.34 higher than that of the Galaxy S7 previously performed by IHS Markit, and is $36.29 higher than the total build cost of the Galaxy S7 Edge, considered a better comparison to the Galaxy S8. IHS Markit has not yet performed a teardown analysis on the larger Galaxy S8 Plus.

“The higher total BOM costs for the Galaxy S8 seem to be part of a trend that reflects something of an arms race in features among Apple, Samsung and other phone manufacturers, as they all try to add new and distinguishing hardware features,” said Andrew Rassweiler, senior director of cost benchmarking services for IHS Markit. “While there are new non-hardware features in the Galaxy S8, such as a virtual assistant called Bixby, from a teardown perspective the hardware in the Galaxy S8 and that of the forthcoming new iPhone is expected to be very similar.”

The introduction of the Galaxy S8 comes at a delicate time for the embattled South Korean electronics giant, which is eager to put behind the challenges associated with the Galaxy Note 7, whose exploding batteries prompted a worldwide recall.

The latest salvo from Samsung shows how it’s keen to regain consumer confidence and attain leadership in the smartphone landscape, a nearly saturated but still highly competitive space that remains key to retaining subscriber loyalties and winning new converts.

First smartphone capable of gigabit-LTE speeds

Both the Galaxy S8 and S8 Plus feature a 10-nanometer (nm) system-on-chip (SoC) along with CAT-16 LTE modem and radio. The CDMA version of the S8, intended for use in the United States as well as in China, will feature the Snapdragon 835 chipset from San Diego-based Qualcomm. In comparison, a version of the phone featuring Samsung’s homegrown Exynos 8895 chipset will be used for the rest of the world.

The CAT-16 LTE radio allows the new Galaxy phone to aggregate three carriers of up to 20 megahertz each. Combined with 4×4 MIMO antennas and higher-order modulation of 256 QAM, the LTE modem is capable of reaching peak theoretical speeds of one gigabit per second. “Gigabit LTE is very much the marquee specification for 2017 flagship smartphones,” said Wayne Lam, principal analyst of smartphone electronics, IHS Markit. “Keep in mind that gigabit speeds are a best-case scenario and that a user’s real-world experience will be limited to what mobile networks can provide.”

New “Infinity Display” design fits better in hand

The redesigned Galaxy S8 has a tall, narrow shape that is 1.5 millimeters narrower than the previous Galaxy S7, providing slick new ergonomics while also optimizing screen real estate. The screen curves around the edges, and Samsung designers have maximized the display, relative to the size of the phone, with a 5.8-inch 2960×1440 AMOLED display and an elongated aspect ratio of 18.5:9. Compared to conventional 16:9 aspect-ratio Quad HD smartphone displays, the Galaxy S8 features an additional 15 percent more pixels in a form factor that is easier to hold in the hand. The device’s haptic engine, which provides the “click” feel for users, also has been improved for longer-duty cycles and a more dynamic response.

Double the base-model storage

Both the Galaxy S8 and S8 Plus feature 4GB of RAM and built-in storage of 64GB—twice the standard built-in storage found in the Galaxy S7 as well as the iPhone 7. Storage for the new Samsung phones can also be expanded, up to 256GB, via a microSD card. The Samsung NAND flash memory and DRAM on the S8 come in at a cost of $41.50. Rassweiler said: “While in previous years the cost per gigabyte has generally fallen in both the NAND flash and DRAM areas, we have seen rising prices in both DRAM and NAND flash recently due to some tightness in the marketplace. The cost of memory in the S8 reflects these recent market dynamics, even though we expect the erosion in memory pricing—something that occurs regularly in the memory market—to resume during the course of the year.”

Battery

The battery capacity on the Galaxy S8, at 3000 milliamp hour (mAh), is the same as that found in last year’s Galaxy S7. However, compared to the Galaxy S7 Edge, which had a 3600mAh battery, Samsung played it safe after the Note 7 incident and included a considerably less dense battery pack. Overall cost estimate for the Galaxy S8 battery pack is $4.50.

Single camera lens

Although the Galaxy S8 and S8 Plus come with new features and the latest components, each still has only a single camera in the back—essentially the same as the camera module found in last year’s Galaxy S7. Apple’s iPhone 7 Plus, the newly launched LG G6 and many Chinese OEMs are now promoting dual cameras as a key feature. Owing to the asymmetric placement of the rear fingerprint sensor, it would have been likely that a dual-camera design was scrapped at the last minute in the design cycle.

Everything we experience is made of light and matter. And the interaction between the two can bring about fascinating effects. For example, it can result in the formation of special quasiparticles, called polaritons, which are a combination of light and matter. A team at the Center for Theoretical Physics of Complex Systems, within the Institute for Basic Science (IBS), modeled the behavior of polaritons in microcavities, nanostructures made of a semiconductor material sandwiched between special mirrors (Bragg mirrors). Published in Scientific Reports, this research brings new ideas to the emerging valleytronics field.

Minimal energy locations, called valleys, are shown with white crosses. Credit: IBS

Minimal energy locations, called valleys, are shown with white crosses. Credit: IBS

Emerging from the coupling of light (photons) and matter (bound state of electrons and holes known as excitons), polaritons have characteristics of each. They are formed when a light beam of a certain frequency bounces back and forth inside microcavities, causing the rapid interconversion between light and matter and resulting in polaritons with a short lifetime. “You can imagine these quasiparticles as waves that you make in water, they move together harmoniously, but they do not last very long. The short lifetime of polaritons in this system is due to the properties of the photons,” explains Mr Meng Sun, first author of the study.

Researchers are studying polaritons in microcavities to understand how their characteristics could be exploited to outperform the present semiconductor technologies. Modern optoelectronics read, process, and store information by controlling the flow of particles, but looking for new more efficient alternatives, other parameters, like the so-called ‘valleys’ could be considered. Valleys can be visualized by plotting the energy of the polaritons to their momentum. Valleytronics aims to control the properties of the valleys in some materials, like transition metal dichalcogenides (TMDCs), indium gallium aluminum arsenide (InGaAlAs), and graphene.

Being able to manipulate their features would lead to tunable valleys with two clearly different states, corresponding for example to 1 bit and 0 bit, like on-off states in computing and digital communications. A way to distinguish valleys with the same energy level is to obtain valleys with different polarization, so that electrons (or polaritons) would preferentially occupy one valley over the others. IBS scientists have generated a theoretical model for valley polarization that could be useful for valleytronics.

Although polaritons are formed by the coupling of photons and excitons, the research team modeled the two components independently. “Modeling potential profiles of photons and excitons separately is the key to find where they overlap, and then determine the minimal energy positions where valleys occur,” points out Sun.

A crucial feature of this system is that polaritons can inherit some properties, like polarization. Valleys with different polarization form spontaneously when the splitting of the transverse (i.e. perpendicular) electronic and magnetic modes of the light beam is taken into consideration (TE-TM splitting).

Since this theoretical model predicts that valleys with opposite polarization can be distinguished and tuned, in principle, different valleys could be selectively excited by a polarized laser light, leading to a possible application in valleytronics.

By Douglas G. Sutherland and David W. Price

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which examined the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing.

While working at the Guinness® brewing company in Dublin, Ireland in the early-1900s, William Sealy Gosset developed a statistical algorithm called the T-test1. Gosset used this algorithm to determine the best-yielding varieties of barley to minimize costs for his employer, but to help protect Guinness’ intellectual property he published his work under the pen name “Student.” The version of the T-test that we use today is a refinement made by Sir Ronald Fisher, a colleague of Gosset’s at Oxford University, but it is still commonly referred to as Student’s T-test. This paper does not address the mathematical nature of the T-test itself but rather looks at the amount of data required to consistently achieve the ninety-five percent confidence level in the T-test result.

A T-test is a statistical algorithm used to determine if two samples are part of the same parent population. It does not resolve the question unequivocally but rather calculates the probability that the two samples are part of the same parent population. As an example, if we developed a new methodology for cleaning an etch chamber, we would want to show that it resulted in fewer fall-on particles. Using a wafer inspection system, we could measure the particle count on wafers in the chamber following the old cleaning process and then measure the particle count again following the new cleaning process. We could then use a T-test to tell if the difference was statistically significant or just the result of random fluctuations. The T-test answers the question: what is the probability that two samples are part of the same population?

However, as shown in Figure 1, there are two ways that a T-Test can give a false result: a false positive or a false negative. To confirm that the experimental data is actually different from the baseline, the T-test usually has to score less than 5% (i.e. less than 5% probability of a false positive). However, if the T-test scores greater than 5% (a negative result), it doesn’t tell you anything about the probability of that result being false. The probability of false negatives is governed by the number of measurements. So there are always two criteria: (1) Did my experiment pass or fail the T-test? (2) Did I take enough measurements to be confident in the result? It is that last question that we try to address in this paper.

Figure 1. A “Truth Table” highlights the two ways that a T-Test can give the wrong result.

Figure 1. A “Truth Table” highlights the two ways that a T-Test can give the wrong result.

Changes to the semiconductor manufacturing process are expensive propositions. Implementing a change that doesn’t do anything (false positive) is not only a waste of time but potentially harmful. Not implementing a change that could have been beneficial (false negative) could cost tens of millions of dollars in lost opportunity. It is important to have the appropriate degree of confidence in your results and to do so requires that you use a sample size that is appropriate for the size of the change you are trying to affect. In the example of the etch cleaning procedure, this means that inspection data from a sufficient number of wafers needs to be collected in order to determine whether or not the new clean procedure truly reduces particle count.

In general, the bigger the difference between two things, the easier it is to tell them apart. It is easier to tell red from blue than it is to distinguish between two different shades of red or between two different shades of blue. Similarly, the less variability there is in a sample, the easier it is to see a change2. In statistics the variability (sometimes referred to as noise) is usually measured in units of standard deviation (σ). It is often convenient to also express the difference in the means of two samples in units of σ (e.g., the mean of the experimental results was 1σ below the mean of the baseline). The advantage of this is that it normalizes the results to a common unit of measure (σ). Simply stating that two means are separated by some absolute value is not very informative (e.g., the average of A is greater than the average of B by 42). However, if we can express that absolute number in units of standard deviations, then it immediately puts the problem in context and instantly provides an understanding of how far apart these two values are in relative terms (e.g., the average of A is greater than the average of B by 1 standard deviation).

Figure 2 shows two examples of data sets, before and after a change. These can be thought of in terms of the etch chamber cleaning experiment we discussed earlier. The baseline data is the particle count per wafer before the new clean process and the results data is the particle count per wafer after the new clean procedure. Figure 2A shows the results of a small change in the mean of a data set with high standard deviation and figure 2B shows the results of the same sized change in the mean but with less noisy data (lower standard deviation). You will require more data (e.g., more wafers inspected) to confirm the change in figure 2A than in figure 2B simply because the signal-to-noise ratio is lower in 2A even though the absolute change is the same in both cases.

Figure 2. Both charts show the same absolute change, before and after, but 2B (right) has much lower standard deviation. When the change is small relative to the standard deviation as in 2A (left) it will require more data to confirm it.

Figure 2. Both charts show the same absolute change, before and after, but 2B (right) has much lower standard deviation. When the change is small relative to the standard deviation as in 2A (left) it will require more data to confirm it.

The question is: how much data do we need to confidently tell the difference? Visually, we can see this when we plot the data in terms of the Standard Error (SE). The SE can be thought of as the error in calculating the average (e.g., the average was X +/- SE). The SE is proportional to σ/√n where n is the sample size. Figure 3 shows the SE for two different samples as a function of the number of measurements, n.

Figure 3. The Standard Error (SE) in the average of two samples with different means. In this case the standard deviation is the same in both data sets but that need not be the case. With greater than x measurements the error bars no longer overlap and one can state with 95% confidence that the two populations are distinct.

Figure 3. The Standard Error (SE) in the average of two samples with different means. In this case the standard deviation is the same in both data sets but that need not be the case. With greater than x measurements the error bars no longer overlap and one can state with 95% confidence that the two populations are distinct.

For a given difference in the means and a given standard deviation we can calculate the number of measurements, x, required to eliminate the overlap in the Standard Errors of these two measurements (at a given confidence level).

The actual equation to determine the correct sample size in the T-test is given by,

Equation 1

Equation 1

where n is the required sample size, “Delta” is the difference between the two means measured in units of standard deviation (σ) and Zx is the area under the T distribution at probability x. For α=0.05 (5% chance of a false positive) and β=0.95 (5% chance of a false negative), Z1-α/2 and Zβ are equal to 1.960 and 1.645 respectively (Z values for other values of α and β are available in most statistics textbooks, Microsoft® Excel® or on the web). As seen in Figure 3 and shown mathematically in Eq 1, as the difference between the two populations (Delta) becomes smaller, the number of measurements required to tell them apart will become exponentially larger. Figure 4 shows the required sample size as a function of the Delta between the means expressed in units of σ. As expected, for large changes, greater than 3σ, one can confirm the T-test 95% of the time with very little data. As Delta gets smaller, more measurements are required to consistently confirm the change. A change of only one standard deviation requires 26 measurements before and after, but a change of 0.5σ requires over 100 measurements.

Figure 4. Sample size required to confirm a given change in the mean of two populations with 5% false positives and 5% false negatives

Figure 4. Sample size required to confirm a given change in the mean of two populations with 5% false positives and 5% false negatives

The relationship between the size of the change and the minimum number of measurements required to detect it has ramifications for the type of metrology or inspection tool that can be employed to confirm a given change. Figure 5 uses the results from figure 4 to show the time it would take to confirm a given change with different tool types. In this example the sample size is measured in number of wafers. For fast tools (high throughput, such as laser scanning wafer inspection systems) it is feasible to confirm relatively small improvements (<0.5σ) in the process because they can make the 200 required measurements (100 before and 100 after) in a relatively short time. Slower tools such as e-beam inspection systems are limited to detecting only gross changes in the process, where the improvement is greater than 2σ. Even here the measurement time alone means that it can be weeks before one can confirm a positive result. For the etch chamber cleaning example, it would be necessary to quickly determine the results of the change in clean procedure so that the etch tool could be put back into production. Thus, the best inspection system to determine the change in particle counts would be a high throughput system that can detect the particles of interest with low wafer-to-wafer variability.

Figure 5. The measurement time required to determine a given change for process control tools with four different throughputs (e-Beam, Broadband Plasma, Laser Scattering and Metrology)

Figure 5. The measurement time required to determine a given change for process control tools with four different throughputs (e-Beam, Broadband Plasma, Laser Scattering and Metrology)

Experiments are expensive to run. They can be a waste of time and resources if they result in a false positive and can result in millions of dollars of unrealized opportunity if they result in a false negative. To have the appropriate degree of confidence in your results you must use the correct sample size (and thus the appropriate tools) that correspond to the size of the change you are trying to affect.

References:

  1. https://en.wikipedia.org/wiki/William_Sealy_Gosset
  2. Process Watch: Know Your Enemy, Solid State Technology, March 2015

About the Authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.