Category Archives: Device Architecture

The Department of Mechanical Engineering of The Hong Kong Polytechnic University (PolyU) has developed a novel technology of embedding highly conductive nanostructure into semiconductor nanofiber. The novel composite so produced has superb charge conductivity, and can therefore be widely applied, especially in environmental arena.

The innovation was awarded the Gold Medal with Congratulations of the Jury at the 45th International Exhibition of Inventions of Geneva, held on 29 March to 2 April this year.

A research team led by Prof. Wallace Leung develops novel semiconductor nanotubes with superb charge conductivity which can be widely used in different applications, especially in environmental arena. (PRNewsfoto/The Hong Kong Polytechnic Univer)

A research team led by Prof. Wallace Leung develops novel semiconductor nanotubes with superb charge conductivity which can be widely used in different applications, especially in environmental arena. (PRNewsfoto/The Hong Kong Polytechnic Univer)

Issues to address

Semiconductor made into nanofiber of diameter as small as 60nm (less than 1/1,000 of a human hair) have been widely used in modern daily life photonic devices (such as solar cells, photocatalyst for cleaning the environment), and non-photonic devices (such as chemical-biological sensor, lithium battery). However, electrons and holes generated by light or energy in semiconductor would readily recombine, thus reduce the current or device effectiveness. Such nature has limited the further development and applications of semiconductor nanofibers.

The novel technology developed by the research team led by Ir. Professor Wallace Leung, Chair Professor of Innovative Products and Technologies of the Department, have overcome such limitation. Applying electrospinning, the team succeeds in inserting highly conductive nano-structure (such as carbon nanotubes, graphene) into semiconductor nanofiber (such as Titanium Dioxide (TiO2 ). The novel nano-composite so produced thus provides a dedicated super-highway for electron transport, eliminating the problem of electron-hole recombination.

Amidst the potentially wide applications of the innovation in many spectrum, Professor Leung’s team has initially embarked on research of applying the novel nano-composite in two environmental aspects: solar cells, and photocatalysts for cleaning air.

Enhanced solar cell efficiency

The latest generation of solar cells (e.g. dye sensitized solar cell (DSSC), perovskite solar cell) are promising clean and renewable energy sources. Yet, for more wide applications, there are still much room for further enhancing their power conversion efficiency and producing in more cost-efficient ways.

By applying PolyU’s novel technology, carbon nanotube/graphene is embedded into the TiO2 component of DSSC and perovskite solar cell, boosting an increase of energy conversion from 40-66%. Compared to commercially available multi-crystalline silicon solar cell common in the market, with current price at US$0.25 (HK$1.94)/kWh, the cost of DSSC with carbon nanotube embedded is 12-32% higher (HK$2.18 – 2.56); while perovskite solar cell embedded with graphene is 28-40% lower (HK$1.17 – 1.40).

Given the superb charge conductivity of the novel semiconductor nanofiber, there is great potential for prompt development of more efficient solar cells, and at lower cost, than the silicon cells.

Enhanced photocatalyst performance in cleaning the air

TiO2 is the most commonly used photocatalyst material in commercially available air-purifying or disinfection devices in the market. However, TiO2 can only be activated by ultraviolet light (i.e. about 6% of solar energy), thus limiting its wider application as it is less effective in indoor environment. It is also relatively ineffective in converting nitric oxide (NO) into nitrogen dioxide (NO2), at a rate of less than 5%.

By applying PolyU’s novel technology, graphene roll is embedded into TZB composite (which mainly compose of TiO2). The novel semiconductor nanofiber so produced has superb conductivity, which provides a graphene superhighway for electrons to transport more quickly to oxide the absorbed pollutants. The technology also significantly increases the novel nano-fiber’s surface exposed for light absorption and trapping harmful molecules.

Such novel semiconductor nanofiber can convert about 90% of NO to NO2, a 35% increase compared to composite without graphene. If compared to high-standard TiO2 nano-particles commonly available in the market, the conversion rate is even 10 times more, yet 10 times more cost-efficient.

Readily available for wide applications

Given the wide uses of semiconductor nanofiber now and in the future, the PolyU groundbreaking technology that develops semiconductor nanofiber with superb charge conductivity has great potential for further development for different applications.

Besides in solar cells and photocatalysts, other obvious examples of making use of such novel technology include the development of biological-chemical sensors with enhanced sensitivity and sensing speed, and lithium batteries with lower impedance and increased storage.

A new method to improve semiconductor fiber optics may lead to a material structure that might one day revolutionize the global transmission of data, according to an interdisciplinary team of researchers.

Researchers are working with semiconductor optical fibers, which hold significant advantages over silica-based fiber optics, the current technology used for transmitting nearly all digital data. Silica — glass — fibers can only transmit electronic data converted to light data. This requires external electronic devices that are expensive and consume enormous amounts of electricity. Semiconductor fibers, however, can transmit both light and electronic data and might also be able to complete the conversion from electrical to optical data on the fly during transmission, improving delivery speed.

Amorphous silicon core is inside a 1.7-micron inner-diameter glass capillary. Credit: Penn State

Amorphous silicon core is inside a 1.7-micron inner-diameter glass capillary. Credit: Penn State

Think of these conversions as exit ramps on the information superhighway, said Venkatraman Gopalan, professor of materials science and engineering, Penn State. The fewer the exits the data takes, the faster the information travels. Call it “fly-by optoelectronics,” he said.

In 2006, researchers, led by John Badding, professor of chemistry, physics, and materials science and engineering, first developed silicon fibers by embedding silicon and other semiconductor materials into silica-fiber capillaries. The fibers, comprised of a series of crystals, were limited in their ability to transmit data because imperfections, such as grain boundaries at the surfaces where the many crystals within the fiber core bonded together, forced portions of the light to scatter, disrupting the transmission.

A method designed by Xiaoyu Ji, doctoral candidate in materials science and engineering, improves on the polycrystalline core of the fiber by melting a high-purity amorphous silicon core deposited inside a 1.7-micron inner-diameter glass capillary using a scanning laser, allowing for formation of silicon single crystals that were more than 2,000 times as long as they were thick. This method transforms the core from a polycrystal with many imperfections to a single crystal with few imperfections that transmits light much more efficiently.

That process, detailed in a trio of articles published in ACS Photonics, Advanced Optical Materials, and Applied Physics Letters early this year, demonstrates a new methodology to improve data transfer by eliminating imperfections in the fiber core that can be made of various materials. Gopalan said equipment constraints kept the crystals from being longer.

Because of the ultra-small core, Ji was able to melt and refine the crystal structure of the core material at temperatures of about 750 to 930 degrees Fahrenheit, lower than a typical fiber-drawing process for silicon core fibers. The lower temperatures and the short heating time that can be controlled by the laser power and the laser scanning speed also prevented the silica capillary, which has different thermal properties, from softening and contaminating the core.

“High purity is fundamentally important for high performance when dealing with materials designated for optical or electrical use,” said Ji.

The important takeaway, said Gopalan, is that this new method lays out the methodology for how a host of materials can be embedded into fiber optics and how voids and imperfections can be reduced to increase light-transfer efficiency, necessary steps to advancing the science from its infancy.

“Glass technology has taken us this far,” said Gopalan. “The ambitious idea that Badding and my group had about 10 years ago was that glass is great, but can we do more by using the numerous electronically and optically active materials other than plain glass. That’s when we began trying to embed semiconductors into glass fiber.”

Like fiber-optic cable, which took decades to become a reliable data-delivery device, decades of work likely remains to create commercially viable, semiconductor fiber networks. It took 10 years for researchers to reach polycrystalline fibers to specifications that are far better, but are still not competitive with traditional fiber-optic cable.

“Xiaoyu has been able to start from nicely deposited amorphous silicon and germanium core and use a laser to crystallize them, so that the whole semiconductor fiber core is one nice single crystal with no boundaries,” said Gopalan. “This improved light and electronic transfer. Now we can make some real devices, not just for communications, but also for endoscopy, imaging, fiber lasers and many more.”

Gopalan said he is not only in the business of creating commercially viable materials. He is interested in dreaming big and taking the long view on new technologies. Perhaps one day, every new home constructed might have a semiconductor fiber, bringing faster internet to it.

“This is why we got into this in the first place,” said Gopalan. “Badding’s group was able to figure out how to put silicon and germanium and metals and other semiconductors into the fiber, and this method improves on that.”

Despite the many advances in portable electronic devices, one thing remains constant: the need to plug them into a wall socket to recharge. Now researchers, reporting in the journal ACS Nano, have developed a light-weight, paper-based device inspired by the Chinese and Japanese arts of paper-cutting that can harvest and store energy from body movements.

paper cutting

Researchers have developed a paper-based device inspired by the Chinese and Japanese arts of paper-cutting that can harvest and store energy from body movements. Credit: American Chemical Society

Portable electronic devices, such as watches, hearing aids and heart monitors, often require only a little energy. They usually get that power from conventional rechargeable batteries. But Zhong Lin Wang, Chenguo Hu and colleagues wanted to see if they could untether our small energy needs from the wall socket by harvesting energy from a user’s body movements. Wang and others have been working on this approach in recent years, creating triboelectric nanogenerators (TENGs) that can harness the mechanical energy all around us, such as that created by our footsteps, and then use it to power portable electronics. But most TENG devices take several hours to charge small electronics, such as a sensor, and they’re made of acrylic, which is heavy.

So the researchers turned to an ultra-light, rhombic paper-cut design a few inches long and covered it with different materials to turn it into a power unit. The four outer sides, made of gold- and graphite-coated sand paper, comprised the device’s energy-storing supercapacitor element. The inner surfaces, made of paper and coated in gold and a fluorinated ethylene propylene film, comprised the TENG energy harvester. Pressing and releasing it over just a few minutes charged the device to 1 volt, which was enough to power a remote control, temperature sensor or a watch.

The SOI market is expected to be valued at USD 1,859.3 Million by 2022, growing at a CAGR of 29.1% between 2017 and 2022, according to a new market research report “Silicon on Insulator Market by Wafer Size (200mm, 300mm), Wafer Type (RFSOI, FDSOI), Technology (BESOI, ELTRAN, SoS, SiMOX, Smart Cut), Product, Application (Automotive, Computing & Mobile, Entertainment & Gaming, Photonics) – Global Forecast to 2022,” published by MarketsandMarkets,

The factors that are driving the growth of this market include the growth in the consumer electronics market, low wafer and gate cost, low operating voltage, and miniaturization of semiconductor devices.

“300mm SOI wafers expected to hold the largest size of the SOI market by 2022“

300mm SOI wafers are expected to lead the overall SOI market by 2022. 300mm wafers is the latest size category in the SOI market. FDSOI wafers-the latest addition to the SOI wafer type segments-are built on the 300mm wafers. Besides that, the production of 300mm RF chips has already been started, which will further boost the demand for 300mm wafers. Soitec, in partnership with its Chinese partner Simgui, is planning to roll out the production of 300 mm RFSOI wafers. Also, the leading chip manufacturers, including Broadcom (U.S.), Qorvo (U.S.), Qualcomm (U.S.), and Murata (Japan), are planning to start the production of 300mm wafers.

“SOI market for FDSOI wafers expected to grow at a high rate between 2017 and 2022“

The SOI market for FDSOI wafers is expected to grow at a significant rate between 2017 and 2022. FDSOI is the next version of PDSOI wafers. FDSOI wafers stand out from the conventional bulk CMOS wafers as they have two additional layers. FDSOI wafers are around 4-5 times costlier than the conventional bulk CMOS, but they provide enhanced performance of the chips produced, power efficiency, and reduction in the energy consumption. FDSOI wafers are produced over the 300 mm SOI wafers and are competing with the FinFET technology.

“APAC expected to lead the SOI market between 2017 and 2022“

APAC is one of the key growth regions for the SOI market. APAC has been the fastest in adopting SOI products compared with other regions. This early start has kick-started the market; thus, from the demand side, APAC is a major player. APAC is witnessing high applicability of SOI owing to the presence of a large number of consumer electronics companies, smartphone manufacturers, and advanced ICT technologies. The high demand for smartphones is one of the key factors contributing to the market growth, as 99% of the smartphones make use of SOI wafers.

The major players operating in the SOI market are Soitec (France), Shin-Etsu (Japan), GlobalWafers (Taiwan), GlobalFoundries (U.S.), STMicroelectronics (Switzerland), NXP Semiconductors (Netherlands), Murata Manufacturing (Japan), Sony Corporation (Japan), MagnaChip Semiconductor (South Korea), TSMC (Taiwan), and Qualcomm (U.S.).

Two-dimensional materials, or 2D materials for short, are extremely versatile, although – or often more precisely because – they are made up of just one or a few layers of atoms. Graphene is the best-known 2D material. Molybdenum disulphide (a layer consisting of molybdenum and sulphur atoms that is three-atoms thick) also falls in this category, although, unlike graphene, it has semiconductor properties. With his team, Dr Thomas Mueller from the Photonics Institute at TU Wien is conducting research into 2D materials, viewing them as a promising alternative for the future production of microprocessors and other integrated circuits.

Stefan Wachter, Dmitry K. Polyushkin and Thomas Mueller (f.l.t.r.). Credit: TU Wien, Marco Furchi

Stefan Wachter, Dmitry K. Polyushkin and Thomas Mueller (f.l.t.r.). Credit: TU Wien, Marco Furchi

The whole and the sum of its parts

Microprocessors are an indispensable and ubiquitous component in the modern world. Without their continued development, many of the things we take for granted these days, such as computers, mobile phones and the internet, would not be possible at all. However, while silicon has always been used in the production of microprocessors, it is now slowly but surely approaching its physical limits. 2D materials, including molybdenum disulphide, are showing promise as potential replacements. Although research into individual transistors – the most basic components of every digital circuit – made of 2D materials has been under way since graphene was first discovered back in 2004, success in creating more complex structures has been very limited. To date, it has only been possible to produce individual digital components using a few transistors. In order to achieve a microprocessor that operates independently, however, much more complex circuits are required which, in addition also need to interact flawlessly.

Thomas Mueller and his team have now managed to achieve this for the first time. The result is a 1-bit microprocessor consisting of 115 transistors over a surface area of around 0.6 mm2 that can run simple programs. “Although, this does of course seem modest when compared to the industry standards based on silicon, this is still a major breakthrough within this field of research. Now that we have a proof of concept, in principle there is no reason that further developments can’t be made,” says Stefan Wachter, a doctoral student in Dr Mueller’s research group. However, it was not just the choice of material that resulted in the success of the research project. “We also gave careful consideration to the dimensions of the individual transistors,” explains Mueller. “The exact relationships between the transistor geometries within a basic circuit component are a critical factor in being able to create and cascade more complex units.”

Future prospects

It goes without saying that much more powerful and complex circuits with thousands or even millions of transistors will be required for this technology to have a practical application. Reproducibility continues to be one of the biggest challenges currently being faced within this field of research along with the yield in the production of the transistors used. After all, both the production of 2D materials in the first place as well as the methods for processing them further are still at the very early stages. “As our circuits were made more or less by hand in the lab, such complex designs are of course pretty much beyond our capability. Every single one of the transistors has to function as planned in order for the processor to work as a whole,” explains Mueller, stressing the huge demands placed on state-of-the-art electronics. However, the researchers are convinced that industrial methods could open up new fields of application for this technology over the next few years. One such example might be flexible electronics, which are required for medical sensors and flexible displays. In this case, 2D materials are much more suitable than the silicon traditionally used owing to their significantly greater mechanical flexibility.

Silicon Integration Initiative, Inc. (Si2), a integrated circuit research and development joint venture, has contributed new power modeling technology to the IEEE P2416 System Level Power Model Working Group. The transfer is aimed at creating a standardized means for modeling systems-on-chip (SoC) designed for lower power consumption.

Jerry Frenkil, Si2 director of OpenStandards, said that the Si2 Low Power Working Group developed the new technology to fill several holes in the flow for estimating and controlling SoC power consumption. “This new modeling technology provides accurate and efficient, early estimation of both static and dynamic power, including critical temperature dependencies, using a consistent model throughout the design flow. There’s currently no standard way to represent power data for use at the system level, especially across a range of process, voltage and temperature points in a single model.”

IEEE P2416 is an essential component of IEEE’s coordinated effort to improve system-level design. This effort also includes the IEEE 1801 standard, which expresses design intent. Its latest update, IEEE 1801-2015, includes support for power-state modeling. “P2416 provides power data representations to complement 1801 power-state modeling. Together, 1801 and 2416 will form a complete power model for hardware IP at any level of abstraction,” Frenkil added.

Organizations that contributed to the model development are: ANSYS, Cadence, Intel, IBM, Entasys, and North Carolina State University.

Nagu Dhanwada, senior technical staff member at IBM, chairs both the IEEE P2416 and Si2 Power Modeling Working Groups. According to Dhanwada, “This is a major contribution to the P2416 effort. As the first technology contribution to the P2416 Working Group, it’s expected to form a solid foundation for the resulting standard.”

“This new modeling technology is the first significant advance in power modeling in quite a long time,” said Paul Traynar, technical fellow at ANSYS and a contributor to the Si2 effort. “It will enable SoC designers to get consistent power estimates across design abstractions and especially early in the system design process.”

Julien Sebot, CPU architect at Intel and a member of the IEEE P2416 Working Group, added, “The Si2 contribution addresses the top priorities identified by the P2416 Working Group. The ability to create accurate, early estimates and to reuse and refine those estimates during the design process is essential in creating energy efficient systems-on-chip. Si2’s contribution is a major step toward addressing that need.”

The IEEE P2416 Working Group has already started reviewing the Si2 contribution. In parallel, Si2 will further develop, for its members, the technology with expanded model semantics, proof-of-concept demonstrations, and reference design implementations.

This model and its use will be described as part of a DAC 2017 tutorial, “How Power Modeling Standards Power Your Designs,” Monday, June 19, 3:30-5:00 p.m., Room 18AB, Austin Convention Center.

ON Semiconductor (Nasdaq: ON) announced it is expanding its portfolio of Interline Transfer Electron Multiplication CCD (IT-EMCCD) image sensors with new options that target not only low-light industrial applications such as medical and scientific imaging, but also commercial and military applications for high-end surveillance.

The new 4 megapixel KAE-04471 uses larger 7.4 micron pixels than those found in existing IT-EMCCD devices, doubling the light gathering capability of the new device and improving image quality under light starved conditions. The KAE-04471 is pin and package compatible with the existing 8 megapixel KAE-08151, allowing camera manufacturers to easily leverage existing camera designs to support the new device.

The new KAE-02152 shares the same 1080p resolution and 2/3” optical format as the existing KAE-02150, but incorporates an enhanced pixel design that increases sensitivity in near-infrared (NIR) wavelengths – an improvement that can be critical in applications such as surveillance, microscopy and ophthalmology. The KAE-02152 is fully drop-in compatible with the existing KAE-02150, and both devices are available in packages that incorporate an integrated thermoelectric cooler, simplifying the work required by camera manufacturers to develop a cooled camera design.

“As the need for sub-lux imaging solutions expands in surveillance, medical, scientific and defense markets, customers are looking for new options that provide the critical performance required in these applications,” said Herb Erhardt, Vice President and General Manager, Industrial Solutions Division, Image Sensor Group at ON Semiconductor. “The new products allow customers to choose from a variety of resolutions, pixel sizes, sensitivities, color configurations and packaging options in our IT-EMCCD portfolio to meet their low-light imaging needs.”

Interline Transfer EMCCD devices combine two established imaging technologies with a unique output structure to enable a new class of low-noise, high-dynamic range imaging. While Interline Transfer CCDs provide excellent image quality and uniformity with a highly efficient electronic shutter, this technology is not always ideal for very low-light imaging. And while EMCCD image sensors excel under low-light conditions, they historically have only been available as low resolution devices with limited dynamic range. Combining these technologies allows the low-noise architecture of EMCCD to be extended to multi-megapixel resolutions, and an innovative output design allows both standard CCD (normal-gain) and EMCCD (high-gain) outputs to be utilized for a single image capture – extending dynamic range and scene detection from sunlight to starlight in a single image.

Engineering grade versions of the KAE-04471 are now available, with production versions available in 2Q17. Engineering grade versions of the KAE-02152 in both a standard package as well as a package incorporating an integrated thermoelectric cooler are also available, with production versions of both configurations available in 3Q17. All IT-EMCCD devices ship in ceramic micro-PGA packages, and are available in both Monochrome and Bayer Color configurations.

Evaluation kits for devices in the IT-EMCCD portfolio allow the full performance of this technology to be examined and reviewed under real-world conditions. Customers can purchase an evaluation kit, or inquire about an on-site demonstration of IT-EMCCD devices, by contacting their local ON Semiconductor sales representative.

MagnaChip Semiconductor Corporation (NYSE: MX), a Korea-based designer and manufacturer of analog and mixed-signal semiconductor products, announced today that it will host its Annual U.S. Foundry Technology Symposium at Hilton Santa Clara, California, on June 7th, 2017.

The primary purpose of the Foundry Technology Symposium is to showcase MagnaChip’s most up-to-date technology offerings and to provide an in-depth understanding of MagnaChip’s manufacturing capabilities, its specialty technology processes, target applications and end-markets. Furthermore, during the symposium, MagnaChip plans to discuss current and future semiconductor foundry business trends, and also cover presentations in key markets through guest speeches.

While providing an in-depth overview of its specialty processes, MagnaChip will also highlight its technology portfolio and its future roadmap, including technologies such as mixed-signal, which supports applications in the Internet of Things (IoT) and RF switch sector and Bipolar-CMOS-DMOS (BCD) for high-performance analog and power management applications. In addition, MagnaChip will also feature applications regarding Ultra-High Voltage (UHV), such as LED lighting and AC-DC chargers, and cover Non-Volatile Memory (NVM)-related technologies, such as Touch IC, Automotive MCUs and other customer specific applications. Furthermore, MagnaChip will present its technologies used in applications including smartphones, tablet PCs, automotive, industrial, LED lighting and the wearables segments. MagnaChip will also review its customer-friendly design environment and an on-line customer service tool known as “iFoundry.”

“We are very pleased to host MagnaChip’s Annual Foundry Technology Symposium in the US again this year,” said YJ Kim, Chief Executive Officer of MagnaChip. “We plan to offer participants an opportunity to better understand the foundry and the application market dynamics, and to provide insights into MagnaChip’s specialty process technologies.” MagnaChip has approximately 466 proprietary process flows it can utilize and offer to its foundry customers.

Computer electronics are shrinking to small-enough sizes that the very electrical currents underlying their functions can no longer be used for logic computations in the ways of their larger-scale ancestors. A traditional semiconductor-based logic gate called a majority gate, for instance, outputs current to match either the “0” or “1” state that comprise at least two of its three input currents (or equivalently, three voltages). But how do you build a logic gate for devices too small for classical physics?

One recent experimental demonstration, the results of which are published this week in Applied Physics Letters, from AIP Publishing, uses the interference of spin-waves — synchronous waves of electron spin alignment observed in magnetic systems. The spin-wave majority gate prototype, made of Yttrium-Iron-Garnet, comes out of a new collaborative research center funded by the German Research Foundation, named Spin+X. The work has also been supported by the European Union within the project InSpin and has been conducted in collaboration with the Belgian nanotechnology research institute IMEC.

The brass block serves as an electric ground plate ensuring an efficient insertion of the RF currents to the antennae and, on the other hand, microwave connectors mounted to the block allow for the embedding of the device into our microwave setup. Credit: Fischer/Kewenig/Meyer

The brass block serves as an electric ground plate ensuring an efficient insertion of the RF currents to the antennae and, on the other hand, microwave connectors mounted to the block allow for the embedding of the device into our microwave setup. Credit: Fischer/Kewenig/Meyer

“The motto of the research center Spin+X is ‘spin in its collective environment,’ so it basically aims at investigating any type of interaction of spins — with light and matter and electrons and so on,” said Tobias Fischer, a doctoral student at the University of Kaiserslautern in Germany, and lead author of the paper. “More or less the main picture we are aiming at is to employ spin-waves in information processing. Spin waves are the fundamental excitations of magnetic materials.”

So instead of using classical electric currents or voltages to send input information to a logic gate, the Kaiserslautern-based international team uses vibrations in a magnetic material’s collective spin — essentially creating nanoscale waves of magnetization that can then interfere to produce Boolean calculations.

“You have atomic magnetic moments in your magnetic material which interact with each other and due to this interaction, there are wave-like excitations that can propagate in magnetic materials,” Fischer said. “The particular device we were investigating is based on the interference of these waves. If you use wave excitations instead of currents […] then you can make use of wave interference, and that comes with certain advantages.”

Using wave interference to produce the majority gate’s output provides two parameters to use in controlling information: the wave’s amplitude, and phase. In principle, that makes this concept more efficient also since a majority gate can substitute up to 10 transistors in modern electronic devices.

“The device we were investigating consists of three inputs where we excite waves and they combine,” Fischer said. “Depending on the input phases where you encode the information, that determines the phase of the output signal, hence, defining the logic output state ‘0’ or ‘1’. That is actually information processing and that’s what we want.”

This first device prototype, though physically larger than what Fischer and his colleagues see for eventual large-scale use, clearly demonstrates the applicability of spin-wave phenomena for reliable information processing at GHz frequencies.

Because the wavelengths of these spin waves are easily reduced to the nanoscale, so too (though perhaps not quite as easily) can be the gate device itself. Doing so may actually improve the functionality, reducing its sensitivity to unwanted field fluctuations. Besides, nano-scaling will increase spin-wave velocities that will allow for an increase in computing speed.

“What we aim for is the miniaturization of the device, and the smaller you make the device, the less sensitive it becomes to these influences,” Fischer said. “If you look at how many wavelengths fit into this propagation length, the fewer there are, the less influence a change of the wavelength has on the output. So basically downscaling the device would also come with more benefits.”

Furthermore, much like antennae, a single device can be operated at multiple frequencies simultaneously. This will allow for parallel computing using the same “core” of a future spin-wave processor.

“One of my colleagues in Kaiserslautern is into spin-wave multiplexing and de-multiplexing,” Fischer said. “We are also going in that direction, to use multiple frequencies and that would be a good compliment […] to this majority gate.”

SEMI, the global industry association representing the electronics manufacturing supply chain, today announced that the worldwide semiconductor photomask market was $3.32 billion in 2016 and is forecasted to reach $3.57 billion in 2018. After increasing 1 percent in 2015, the photomask market increased 2 percent in 2016. The mask market is expected to grow 4 and 3 percent in 2017 and 2018, respectively, according to the SEMI report. Key drivers in this market continue to be advanced technology feature sizes (less than 45nm) and increased manufacturing in Asia-Pacific. Taiwan remains the largest photomask regional market for the sixth year in a row and is expected to be the largest market for the duration of the forecast.

Revenues of $3.32 billion place photomasks at 13 percent of the total wafer fabrication materials market, behind silicon and semiconductor gases. By comparison, SEMI reports that photomasks represented 18 percent of the total wafer fabrication materials market in 2003. Another trend highlighted in the report is the increasing importance of captive mask shops. Captive mask shops, aided by intense capital expenditures in 2011 and 2012 continue to gain market share at merchant suppliers’ expense. Captive mask suppliers accounted for 63 percent of the total photomask market last year, up from 56 percent in 2015. Captive mask shops represented 31 percent of the photomask market in 2003.

A recent published SEMI report, 2016 Photomask Characterization Summary, provides details on the 2016 Photomask Market for seven regions of world including North America, Japan, Europe, Taiwan, Korea, China, and Rest of World. The report also includes data for each of these regions from 2003 to 2018 and summarizes lithography developments over the past year.