Category Archives: Device Architecture

IEEE, the world’s largest technical professional organization dedicated to advancing technology for humanity, this week announced the next milestone phase in the development of the International Roadmap for Devices and Systems (IRDS)—an IEEE Standards Association (IEEE-SA) Industry Connections (IC) Program sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative—with the launch of a series of nine white papers that reinforce the initiative’s core mission and vision for the future of the computing industry. The white papers also identify industry challenges and solutions that guide and support future roadmaps created by IRDS.

IEEE is taking a lead role in building a comprehensive, end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software. In May 2016, IEEE announced the formation of the IRDS under the sponsorship of IEEE RC. The historical integration of IEEE RC and the International Technology Roadmap for Semiconductors (ITRS) 2.0 addresses mapping the ecosystem of the new reborn electronics industry. The new beginning of the evolved roadmap—with the migration from ITRS to IRDS—is proceeding seamlessly as all the reports produced by the ITRS 2.0 represent the starting point of IRDS.

While engaging other segments of IEEE in complementary activities to assure alignment and consensus across a range of stakeholders, the IRDS team is developing a 15-year roadmap with a vision to identify key trends related to devices, systems, and other related technologies.

“Representing the foundational development stage in IRDS is the publishing of nine white papers that outline the vital and technical components required to create a roadmap,” said Paolo A. Gargini, IEEE Fellow and Chairman of IRDS. “As a team, we are laying the foundation to identify challenges and recommendations on possible solutions to the industry’s current limitations defined by Moore’s Law. With the launch of the nine white papers on our new website, the IRDS roadmap sets the path for the industry benefiting from all fresh levels of processing power, energy efficiency, and technologies yet to be discovered.”

“The IRDS has taken a significant step in creating the industry roadmap by publishing nine technical white papers,” said IEEE Fellow Elie Track, 2011-2014 President, IEEE Council on Superconductivity; Co-chair, IEEE RC; and CEO of nVizix. “Through the public availability of these white papers, we’re inviting computing professionals to participate in creating an innovative ecosystem that will set a new direction for the greater good of the industry. Today, I open an invitation to get involved with IEEE RC and the IRDS.”

The series of white papers delivers the starting framework of the IRDS roadmap—and through the sponsorship of IEEE RC—will inform the various roadmap teams in the broader task of mapping the devices’ and systems’ ecosystem:

“IEEE is the perfect place to foster the IRDS roadmap and fulfill what the computing industry has been searching for over the past decades,” said IEEE Fellow Thomas M. Conte, 2015 President, IEEE Computer Society; Co-chair, IEEE RC; and Professor, Schools of Computer Science, and Electrical and Computer Engineering, Georgia Institute of Technology. “In essence, we’re creating a new Moore’s Law. And we have so many next-generation computing solutions that could easily help us reach uncharted performance heights, including cryogenic computing, reversible computing, quantum computing, neuromorphic computing, superconducting computing, and others. And that’s why the IEEE RC Initiative exists: creating and maintaining a forum for the experts who will usher the industry beyond the Moore’s Law we know today.”

The IRDS leadership team hosted a winter workshop and kick-off meeting at the Georgia Institute of Technology on 1-2 December 2016. Key discoveries from the workshop included the international focus teams’ plans and focus topics for the 2017 roadmap, top-level needs and challenges, and linkages among the teams. Additionally, the IRDS leadership invited presentations from the European and Japanese roadmap initiatives. This resulted in the 2017 IRDS global membership expanding to include team members from the “NanoElectronics Roadmap for Europe: Identification and Dissemination” (NEREID) sponsored by the European Semiconductor Industry Association (ESIA), and the “Systems and Design Roadmap of Japan” (SDRJ) sponsored by the Japan Society of Applied Physics (JSAP).

The IRDS team and its supporters will convene 1-3 April 2017 in Monterey, California, for the Spring IRDS Workshop, which is part of the 2017 IEEE International Reliability Physics Symposium (IRPS). The team will meet again for the Fall IRDS Conference—in partnership with the 2017 IEEE International Conference on Rebooting Computing (ICRC)—scheduled for 6-7 November 2017 in Washington, D.C. More information on both events can be found here: http://irds.ieee.org/events.

IEEE RC is a program of IEEE Future Directions, designed to develop and share educational tools, events, and content for emerging technologies.

IEEE-SA’s IC Program helps incubate new standards and related products and services, by facilitating collaboration among organizations and individuals as they hone and refine their thinking on rapidly changing technologies.

Technavio market research analysts forecast the global MRAM market to grow at a CAGR of close to 94% during the forecast period, according to their latest report.

The market study covers the present scenario and growth prospects of the global MRAM market for 2017-2021. The report also lists STT-MRAM and Toggle MRAM as the two major product segments, of which STT-MRAM accounted for more than 63% of the market share in 2016. STT-MRAM devices are more efficient, faster, and easier to scale down as compared to toggle MRAM devices.

“MRAM is a type of nonvolatile memory that utilizes magnetic charges for storing data instead of electric charges as in the case of DRAM and SRAM technologies. MRAM offers the added advantage of higher density in terms of writing and reading speed. In addition, MRAM retains the data even when turned off and consumes less amount of electricity, unlike DRAM and SRAM,” says Navin Rajendra, an industry expert for embedded systems research at Technavio.

Technavio’s sample reports are free of charge and contain multiple sections of the report including the market size and forecast, drivers, challenges, trends, and more.

Technavio hardware and semiconductor analysts highlight the following three market drivers that are contributing to the growth of the global MRAM market:

  • Increasing demand for data centers
  • Growing Internet of things (IoT) and big data operations
  • Enterprise adoption of cloud-based storage

Increasing demand for data centers

High amount of system memory has become crucial for the proper functioning of new types of enterprise and data center applications. DRAM cannot provide the required capacity and low energy required for these data centers. MRAM has advanced features like low-power consumption and higher memory capacity than DRAM. Thus, MRAM is expected to replace DRAM in data centers and enterprise storages during the forecast period.

The demand for data centers among CSPs, government agencies, and telecommunications organizations is growing. Thus, with an increase in the demand for data centers globally, the manufacturers will invest in new technologies that will be equipped with MRAMs, which will drive the global MRAM market.

Growing Internet of things (IoT) and big data operations

There will be around 30 billion Internet-connected devices worldwide by 2020, which will be a major revenue generator for data center storage market as growing connected devices will lead to the generation of high volumes of data. Terms such as a connected car, connected home, connected health, and smart cities are gaining popularity. Many industries such as manufacturing, utilities, retail, automotive, and social media use IoT.

IoT devices demand an energy-efficient network of smart nodes that need to be always powered on, always connected, and always aware, with low active duty cycles. The present IoT devices rely on both nonvolatile storage and volatile working memory simultaneously.

“Manufacturers have introduced a unified memory subsystem that is built on embedded STT-MRAM. This system offers faster processing and is cost and energy efficient as compared to the older technologies,” says Navin.

Enterprise adoption of cloud-based storage

Storing data on the cloud is proving to be an effective medium for enterprises worldwide. Many enterprises started moving their data to the cloud (storage-as-a-service) by selecting service providers such as Amazon Web Service, Microsoft Azure, and Google Cloud Platform. DRAM has been used in cloud computing applications. However, MRAM has better features like fast read-write and low error rate compared with DRAM, and thus, it is expected that DRAM will soon be replaced by MRAM in the future.

An innovative new technique to produce the quickest, smallest, highest-capacity memories for flexible and transparent applications could pave the way for a future golden age of electronics.

Engineering experts from the University of Exeter have developed innovative new memory using a hybrid of graphene oxide and titanium oxide. Their devices are low cost and eco-friendly to produce, are also perfectly suited for use in flexible electronic devices such as ‘bendable’ mobile phone, computer and television screens, and even ‘intelligent’ clothing.

Crucially, these devices may also have the potential to offer a cheaper and more adaptable alternative to ‘flash memory’, which is currently used in many common devices such as memory cards, graphics cards and USB computer drives.

The research team insist that these innovative new devices have the potential to revolutionise not only how data is stored, but also take flexible electronics to a new age in terms of speed, efficiency and power.

The research is published in the leading scientific journal ACS Nano.

Professor David Wright, an Electronic Engineering expert from the University of Exeter and lead author of the paper said: “Using graphene oxide to produce memory devices has been reported before, but they were typically very large, slow, and aimed at the ‘cheap and cheerful’ end of the electronics goods market.

“Our hybrid graphene oxide-titanium oxide memory is, in contrast, just 50 nanometres long and 8 nanometres thick and can be written to and read from in less than five nanoseconds — with one nanometre being one billionth of a metre and one nanosecond a billionth of a second.”

Professor Craciun, a co-author of the work, added: “Being able to improve data storage is the backbone of tomorrow’s knowledge economy, as well as industry on a global scale. Our work offers the opportunity to completely transform graphene-oxide memory technology, and the potential and possibilities it offers.”

Researchers at North Carolina State University have developed a technique for converting positively charged (p-type) reduced graphene oxide (rGO) into negatively charged (n-type) rGO, creating a layered material that can be used to develop rGO-based transistors for use in electronic devices.

“Graphene is extremely conductive, but is not a semiconductor; graphene oxide has a bandgap like a semiconductor, but does not conduct well at all — so we created rGO,” says Jay Narayan, the John C. Fan Distinguished Chair Professor of Materials Science and Engineering at NC State and corresponding author of a paper describing the work. “But rGO is p-type, and we needed to find a way to make n-type rGO. And now we have it for next-generation, two-dimensional electronic devices.”

Specifically, Narayan and Anagh Bhaumik — a Ph.D. student in his lab — demonstrated two things in this study. First, they were able to integrate rGO onto sapphire and silicon wafers — across the entire wafer.

Second, the researchers used high-powered laser pulses to disrupt chemical groups at regular intervals across the wafer. This disruption moved electrons from one group to another, effectively converting p-type rGO to n-type rGO. The entire process is done at room temperature and pressure using high-power nanosecond laser pulses, and is completed in less than one-fifth of a microsecond. The laser radiation annealing provides a high degree of spatial and depth control for creating the n-type regions needed to create p-n junction-based two-dimensional electronic devices.

The end result is a wafer with a layer of n-type rGO on the surface and a layer of p-type rGO underneath.

This is critical, because the p-n junction, where the two types meet, is what makes the material useful for transistor applications.

A coalition of leaders from the global tech, defense, and aerospace industries, led by the Semiconductor Industry Association (SIA) and Semiconductor Research Corporation (SRC), today released a report identifying the key areas of scientific research needed to advance innovation in semiconductor technology and fulfill the promise of emerging technologies such as artificial intelligence (AI), the Internet of Things (IoT), and supercomputing. The report, titled Semiconductor Research Opportunities: An Industry Vision and Guide, also calls for robust government and industry investments in research to unlock new technologies beyond conventional, silicon-based semiconductors and to advance next-generation semiconductor manufacturing methods.

“Semiconductor technology is foundational to America’s innovation infrastructure and global technology leadership,” said John Neuffer, president and CEO of SIA, which represents U.S. leadership in semiconductor manufacturing, design, and research. “Our industry has pushed Moore’s Law to levels once unfathomable, enabling technologies that have driven economic growth and transformed society. Now, as it becomes increasingly challenging and costly to maintain the breakneck pace of putting more transistors on the same size of silicon real estate, industry, academia, and government must intensify research partnerships to explore new frontiers of semiconductor innovation and to foster the continued growth of emerging technologies. Taking swift action to implement the recommendations from the Vision report will help usher in a new era of semiconductor technology and keep America at the head of the class in technological advancement.”

Neuffer also noted concern in the tech, research, and academic communities about proposed cuts to basic scientific research outlined in the Trump Administration’s fiscal year 2018 budget blueprint. Basic scientific research funded through agencies such as the National Science Foundation (NSF), the National Institute of Standards and Technology (NIST), the Defense Advanced Research Projects Agency (DARPA), and the Department of Energy (DOE) Office of Science has yielded tremendous dividends, helping launch technologies that underpin America’s economic strength and global competiveness. The U.S. semiconductor industry invests about one-fifth of revenue each year in R&D – the highest share of any industry. Neuffer expressed the semiconductor industry’s readiness to work with the Administration and Congress to enact a budget that embraces the strategic importance of research investments to America’s continued economic and technological strength.

“Continued and predictable advancements in semiconductor technology have fueled the growth of many industries, including those historically based on mechanics such as automotive,” said Ken Hansen, president & CEO of SRC. “As the rate of dimensional scaling has slowed, the need to reinvigorate the investment in semiconductor research has become increasingly clear. Now is the time for industry, government, and academia to double down their resources and efforts to ensure the pace of renewal continues. Alternative strategies and techniques to the traditional scaling for performance are now being explored by SRC. Furthermore, with the support of SIA, SRC is building research programs that align with the Vision report, including complimentary technologies such as advanced packaging and communications. An infusion of funding is vital to expand the research breadth beyond the historical focus areas, enabling the industry to keep its promise of a continuous stream of products with improved performance at reduced cost. As industries look to future areas of growth and innovation, SIA and SRC are laying the groundwork for new discoveries through fundamental research.”

The Vision report is the culmination of work by a diverse group of industry experts and leaders, including chief technology officers at numerous leading semiconductor companies, who came together over a nine-month period in 2016-2017 to identify areas in which research is essential to progress. The report, which will be updated periodically moving forward, has active participation from the industry’s leading chip makers, fabless companies, IP providers, equipment and material suppliers, and research organizations. It will serve as a foundational guide for defining the semiconductor industry’s future research paths in 14 distinct but complimentary research areas. These areas, outlined in the Vision report, are as follows:

1. Advanced Devices, Materials, and Packaging2. Interconnect Technology and Architecture

3. Intelligent Memory and Storage

4. Power Management

5. Sensor and Communication Systems

6. Distributed Computing and Networking

7. Cognitive Computing

 8. Bio-Influenced Computing and Storage9. Advanced Architectures and Algorithms

10. Security and Privacy

11. Design Tools, Methodologies, and Test

12. Next-Generation Manufacturing Paradigm

13. Environmental Health and Safety: Materials and Processes

14. Innovative Metrology and Characterization

 

IC Insights has raised its worldwide IC market growth forecast for 2017 to 11%—more than twice its original 5% outlook—based on data shown in the March Update to the 20th anniversary 2017 edition of The McClean Report. The revision was necessary due to a substantial upgrade to the 2017 growth rates forecast for the DRAM and NAND flash memory markets.

IC Insights currently expects DRAM sales to grow 39% and NAND flash sales to increase 25% this year, with upside potential from those forecasts.  DRAM market growth is expected to be driven almost entirely by a huge 37% increase in the DRAM average selling price (ASP), as compared to 2016, when the DRAM ASP dropped by 12%. Moreover, NAND flash ASPs are forecast to rebound and jump 22% this year after falling by 1% last year.

The DRAM market started 2017 the way it ended 2016—with strong gains in DRAM ASP.  In April 2016, the DRAM ASP was $2.41 but rapidly increased to $3.60 in January 2017, a 49% jump.  A pickup in DRAM demand from PC suppliers during the second half of 2016 caused a significant spike in the ASP of PC DRAM.  Currently, strengthening ASPs are also evident in the mobile DRAM market segment.

With total DRAM bit volume demand expected to increase by 30% this year and DRAM bit volume production capacity forecast to increase by 20%, IC Insights believes that quarterly DRAM ASPs could still surprise on the upside in 2017. Furthermore, DRAM output is also being slowed, at least temporarily, by the ongoing transition of DRAM production to ≤20nm feature sizes by the major DRAM producers this year.

At $57.3 billion, the DRAM market is forecast to be by far the largest IC product category in 2017, exceeding the expected MPU market for standard PCs and servers ($47.1 billion) by $10.2 billion this year.  Figure 1 shows that the DRAM market has been both a significant tailwind (i.e., positive influence) and headwind (i.e., negative influence) on total worldwide IC market growth in three out of the past four years.

Figure 1

Figure 1

Spurred by a 12% decline in the DRAM ASP in 2016, the DRAM market slumped 8% last year.  The DRAM segment became a headwind to worldwide IC market growth in 2016 instead of the tailwind it had been in 2013 and 2014. As shown, the DRAM market shaved two percentage points off of total IC industry growth last year.  In contrast, the DRAM segment is forecast to have a positive impact of four percentage points on total IC market growth this year. It is interesting to note that the total IC market growth rate forecast for 2017, when excluding the DRAM and NAND flash markets, would be only 4%, about one-third of the current worldwide IC market growth rate forecast including these memory devices.

The March Update to the 2017 edition of The McClean Report further describes IC Insights’ IC market forecast revision, updates its 2017-2021 semiconductor capital spending forecast, and shows the final 2016 top 10 OSAT company ranking.

aicha-evans_1Intel Corporation today announced the appointment of Aicha S. Evans as chief strategy officer, effective immediately. She will be responsible for driving Intel’s long-term strategy to transform from a PC-centric company to a data-centric company, as well as leading rapid decision making and company-wide execution of the strategy.

“Aicha is an industry visionary who will help our senior management team and the board of directors focus on what’s next for Intel,” Intel CEO Brian Krzanich said. “Her new role reflects her strong strategic leadership across Intel’s business, most importantly in 5G and other communications technology. Her invaluable expertise will contribute to the company’s long-term strategy and product portfolio.”

“I look forward to working across the company to advance Intel’s ongoing transformation,” Evans said. “We have an exciting future ahead us.”

Evans is an Intel senior vice president and has been responsible for wireless communications for the past nine years. Most recently, she was the general manager of the Communication and Devices Group. Evans joined Intel in 2006 and is based in Santa Clara, Calif. In her new role, she will report to Intel CFO Bob Swan.

An internal and external search is underway for a new general manager of Intel’s Communication and Devices Group.

For the last few decades, microchip manufacturers have been on a quest to find ways to make the patterns of wires and components in their microchips ever smaller, in order to fit more of them onto a single chip and thus continue the relentless progress toward faster and more powerful computers. That progress has become more difficult recently, as manufacturing processes bump up against fundamental limits involving, for example, the wavelengths of the light used to create the patterns.

Now, a team of researchers at MIT and in Chicago has found an approach that could break through some of those limits and make it possible to produce some of the narrowest wires yet, using a process that could easily be scaled up for mass manufacturing with standard kinds of equipment.

The new findings are reported this week in the journal Nature Nanotechnology, in a paper by postdoc Do Han Kim, graduate student Priya Moni, and Professor Karen Gleason, all at MIT, and by postdoc Hyo Seon Suh, Professor Paul Nealey, and three others at the University of Chicago and Argonne National Laboratory. While there are other methods that can achieve such fine lines, the team says, none of them are cost-effective for large-scale manufacturing.

The new approach uses a self-assembly technique in which materials known as block copolymers are covered by a second polymer. They are deposited on a surface by first heating the precursor so it vaporizes, then allowing it to condense on a cooler surface, much as water condenses on the outside of a cold drinking glass on a hot day.

“People always want smaller and smaller patterns, but achieving that has been getting more and more expensive,” says Gleason, who is MIT’s associate provost as well as the Alexander and I. Michael Kasser (1960) Professor of Chemical Engineering. Today’s methods for producing features smaller than about 22 nanometers (billionths of a meter) across generally require building up an image line by line, by scanning a beam of electrons or ions across the chip surface — a very slow process and therefore expensive to implement at large scale.

The new process uses a novel integration of two existing methods. First, a pattern of lines is produced on the chip surface using standard lithographic techniques, in which light shines through a negative mask placed on the chip surface. That surface is chemically etched so that the areas that were illuminated get dissolved away, leaving the spaces between them as conductive “wires” that connect parts of the circuit.

Then, a layer of material known as a block copolymer — a mix of two different polymer materials that naturally segregate themselves into alternating layers or other predictable patterns — is formed by spin coating a solution. The block copolymers are made up of chain-like molecules, each consisting of two different polymer materials connected end-to-end.

“One half is friendly with oil, the other half is friendly with water,” Kim explains. “But because they are completely bonded, they’re kind of stuck with each other.” The dimensions of the two chains predetermine the sizes of layers or other patterns they will assemble themselves into when they are deposited.

Finally, a top, protective polymer layer is deposited on top of the others using chemical vapor deposition (CVD). This top coat, it turns out, is a key to the process: It constrains the way the block copolymers self-assemble, forcing them to form into vertical layers rather than horizontal ones, like a layer cake on its side.

The underlying lithographed pattern guides the positioning of these layers, but the natural tendencies of the copolymers cause their width to be much smaller than that of the base lines. The result is that there are now four (or more, depending on the chemistry) lines, each of them a fourth as wide, in place of each original one. The lithographed layer “controls both the orientation and the alignment” of the resulting finer lines, explains Moni.

Because the top polymer layer can additionally be patterned, the system can be used to build up any kind of complex patterning, as needed for the interconnections of a microchip.

Most microchip manufacturing facilities use the existing lithographic method, and the CVD process itself is a well-understood additional step that could be added relatively easily. Thus, implementing the new method could be much more straightforward than other proposed methods of making finer lines, such as the use of extreme ultraviolet light, which would require the development of new light sources and new lenses to focus the light. With the new method, Gleason says, “you wouldn’t need to change all those machines. And everything that’s involved are well-known materials.”

Silego Technology, a developer of Configurable Mixed-signal Integrated Circuits (CMICs), announced today an extension of its performance-driven GFET3 Integrated Power Switch (IPS) portfolio. Addressing extremely PCB-space-constrained, high-performance applications in tablet PC, smartphones and fitness band markets, these three new WLCSP products cover high-side power control applications from 1 A to 4 A.

For smartphone and fitness band applications, the 0.64 mm2 (0.8 mm x 0.8 mm) SLG59M1730C (33 mΩ/1 A) and the SLG59M1736C (33 mΩ/2.2 A) are low-leakage, self-powered pFET IPSs that can operate from 2.5 V to 5.5 V supply voltages and draw very little supply current. Both products offer low-threshold ON/OFF control, fast output voltage discharge, and a novel, controlled input current profile on startup. Since small form-factor Li-ion batteries exhibit very low amp-hour capacities, the SLG59M1730C/SLG59M1736C’s controlled 16.5 mA inrush current profile on startup prevents Li-ion battery voltage sag when Bluetooth radios or other high current-demand operations are enabled. When compared to other 4-ball WLCSPs in the market with fast, fixed output voltage rise times, the magnitude of the inrush current – directly proportional to the load capacitor value – can be quite large. If the resultant inrush current is large enough to cause the Li-ion battery voltage to sag, an inadvertent system reset can result. Thus, the SLG59M1730C/SLG59M1736C’s controlled inrush current attribute prevents unintended system resets from occurring.

For higher-power tablet pc applications, the SLG59M1735C is a 10.5 mΩ/4 A nFET IPS with a full suite of protection features. Powered from 2.5 V to 5.5 V supplies, the input voltage range extends down to 0.9 V to accommodate 1.0 V high-current rails found in FPGA, ASIC, and processor power sequencing applications. The SLG59M1735C feature set includes: ON/OFF control, soft-start control, undervoltage detection, and two-level current-limit protection. When compared to other packaged products in Silego’s GFET3 portfolio with similar features, the 1.5 mm2 SLG59M1735C is a 50% smaller footprint. When compared to other 4 A WLCSP/DFN products in the market with similar protection features, the SLG59M1735C is a 14% to 32% smaller footprint.

Using Silego’s proprietary MOSFET design IP, these highly-reliable integrated protection devices offer world-class nFET and pFET low RDSON performance. Applying Silego’s proprietary CuFETTM technology, the Company’s design engineers deftly craft these products into very-small WLCSP footprints that maximize system-level performance while minimizing thermal gradients in space-constrained, medium-current applications.

ATTOPSEMI Technology, Ltd. today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator Partner Program, to provide a scalable, non-volatile one-time programmable (OTP) memory IP to be compatible with GF’s 22FDX technology. ATTOPSEMI’s I-fuse OTP IP offers increased reliability, smaller cell size, low programming voltage/current, and high data security enabling customers and designers the ability to utilize an advanced OTP for harsh applications such as automotive, 3D IC, and IoT applications.

The opportunity for advanced OTP memory technology is greater than ever. As the volumes and technical demands increase for Internet of Things (IoT), processing performance grows and memory intensive applications advance, ATTOPSEMI’s I-fuse fills the need. Consumer, communications, automotive and wireless markets require smaller sizing, ease of programmability and high levels of reliability. With its patent-proven structure, the I-fuse can guarantee zero-program defect giving customers the needed knowledge of reliability and execution.

“ATTOPSEMI’s new offering should benefit our 22FDX customers in all the key market segments we address, especially for IoT and processor intensive applications,” said Alain Mutricy, senior vice president of product management at GF. “Their commitment continues to demonstrate strong industry interest in GF’s FDXcelerator program and the 22FDX value proposition.”

“We are excited to expand our engagements with GF and believe that our technology will help their customers deliver the functionality the market has been asking for,” said Chung Shine, Chairman, ATTOPSEMI. “We believe that our development has given us the ability to generate a smaller cell size and more reliability than our competitors along with a very scalable solution.”

ATTOPSEMI’s I-fuse is a fuse-based OTP technology that offers up to 100x reliability, 1/100 the cell size, and 1/10th the program current than traditional e-fuse technologies. Highlights of the I-fuse include:

  • Limited program current below a catastrophic breaking point
  • Use of junction diode, instead of MOS, as a program selector in an OTP cell
  • Smaller cell improving program efficiency enabling program current reduction