Category Archives: Device Architecture

Synopsys, Inc. (Nasdaq:  SNPS) today announced the availability of a key technology in virtual prototyping which enables architecture performance requirements to be easily shared through the supply chain. The latest release of its Platform Architect solution introduces new Task Graph Generator (TGG) technology, which automatically extracts key performance characteristics from software applications to enable architecture exploration to optimize performance and power for next generation multicore system-on-chips (SoCs). TGG enables system architecture teams to more easily share accurate application workload models with their semiconductor suppliers, enabling much more efficient collaboration in the supply chain.

“To address growing software content, the use of multicore architectures in automotive electronic systems is increasing,” said Takashi Abe, project manager, Basis Electronics R&D Division at Denso. “Using the TGG capability in Platform Architect, we are able to capture the key characteristics of our existing software and derive the performance of next generation multicore architectures with high accuracy. By applying this approach early in the planning phase, we are able to ensure that system specifications will meet the demanding performance requirements of these applications.”

Using Platform Architect, semiconductor suppliers can define the architecture specification for next generation SoCs based on the software application requirements from their system customers. System designers can map a software workload model generated by TGG, called a task graph, to the processing resources in the SoC. This allows them to explore, analyze and optimize the performance and power of next generation multicore SoC architectures very early in the development cycle. And, because task graphs are abstract workload models and not the actual software, systems design teams can more easily share them with their semiconductor suppliers as executable specifications, benefiting collaboration in the supply chain.

TGG is application profiling technology that takes software execution traces as its input. By running the application program of interest on an existing system, designers can record their input using a supported TGG format, including:

  • OS-level traces for programs executing on any Linux, Android, and QNX based system, including existing hardware devices
  • Function-level traces for programs executing on x86 based systems (Windows or Linux), using the Pin instrumentation tool from Intel, and on ARM-based systems using Synopsys Virtualizer Development Kit (VDK) virtual prototypes or ARM® DS-5 Development Studio

TGG analyzes the execution trace to extract the processing and communication requirements of the application of interest, including task level parallelism and dependencies, processing cycles per task, and read/write memory accesses, to generate the resulting task graph workload model for performance analysis and benchmarking of new architectures in Platform Architect.

“Delivering the right balance of performance and energy efficiency is critical to avoid under- and over-design,” said Eshel Haritan, vice president, virtual prototyping R&D for the Synopsys Verification Group. “With Task Graph Generator in Platform Architect, system designers gain a realistic, system-level benchmark view of critical SoC applications, enabling system design teams to explore and optimize the performance and power of their new architecture months before final hardware and software are available, reducing risk and improving results.”

NXP Semiconductors N.V. (NASDAQ:NXPI) today announced the world’s smallest single-chip SoC solution – the MC9S08SUx microcontroller (MCU) family – with an integrated 18V-to-5V LDO and MOSFET pre-driver that delivers ultra-high-voltage solution for drones, robots, power tools, DC fan, healthcare and other low-end brushless DC electric motor control (BLDC) applications. Extending the company’s S08 family of MCUs, the robust 8-bit MC9S08SUx microcontroller family offers 4.5V~18V supply voltage range with lower bill of materials (BOM) cost and tighter integration for higher performance and reliability. The new SoC units address the growing demand to replace multiple device solutions with a single MCU to reduce cost and system size, while simplifying integration and layout for space-constrained use cases.

“The market trend is pointing towards integrated solutions that save system size and cost, and NXP is leading the industry as the only provider to offer a single-chip offering with integrated microcontroller and MOSFET pre-driver in a 4x4x0.65mm form factor, which also makes it possible to cut the printed circuit board size in half,” said Geoff Lees, senior vice president and general manager of the microcontroller business line at NXP. “Historically, several devices were needed to address the needs of BLDC motor control applications, which can be expensive and large in size; our latest addition to the S08 MCU family underscores our dedication to solving unique challenges by introducing new microcontrollers for the broad market.”

Based on the HCS08 core, the MC9S08SUx leverages the enhanced S08L central processor unit with three-phase MOSFET pre-drivers to deliver all-in-one unit for 4.5V-18V motor control applications. The single-chip MC9S08SUx MCU removes the need for Low Drop Out (LDO) voltage regulator(s), operational amplifiers, and pre-drivers for a streamlined, cost-effective solution. Additionally, NXP has integrated virtually all of the necessary features in BLDC motor control, including zero crossing point detection, pulse width measurement, over voltage protection and over current protection, enabling developers to simply configure registers and easily use the functions in applications. The MC9S08SUx family also includes amplifiers for current measurement and supports three high-side PMOSes as well as three low-side NMOSes.

NXP’s S08 microcontrollers, including the new MC9S08SUx family, are supported by CodeWarrior IDE. FreeMASTER support is offered as run-time debugging tool. In addition, IAR Embedded Workbench supports the NXP S08 MCU portfolio, offering a single toolbox complete with configuration files, code examples and project templates. IAR Embedded Workbench support for the MC9S08SUx MCU family will be available March 2017.

“The leading optimization technology in IAR Embedded Workbench helps developers to maximize performance and minimize power consumption for applications based on the new MC9S08SUx MCU family from NXP,” said Jan Nyrén, Product Manager, IAR Systems.

Leti, a research institute of CEA Tech, today announced it has developed a shield that can help protect electronic devices against physical attacks from the chips’ backside. Integrated circuits (ICs) embedded in connected objects, smart cards or other systems dealing with sensitive data would benefit from this technology, which brings more privacy, safety and security to the users.

Physical attacks may occur when hackers have access to the device and can exploit weaknesses of the embedded IC to steal sensitive information or to corrupt its functioning. The shield proposed by Leti protects chips from invasive and semi-invasive attacks by infrared lasers, focused ion beams (FIB), chemicals and other means.

The shield consists of a metal serpentine sandwiched between two polymers, one being opaque to infrared and serving as a physical barrier against FIB attacks. It also hides the design of the chips’ serpentine and combines with the polymer underneath to detect chemical attacks. Altering the serpentine typically triggers the IC to delete sensitive data.

The shield is fabricated using standard packaging processes, which demonstrates that hardware cybersecurity can be implemented at low additional cost. Leti’s research results will be presented at this week’s Device Packaging Conference inFountain Hills, Arizona, in a paper entitled “Backside Shield against Physical Attacks for Secure ICs”.

“Implementation of multiple hardware and software countermeasures is making integrated circuits more secure, but the backside of a chip is still considered to be vulnerable to physical attacks,” said Alain Merle, Leti’s Security Strategic Marketing Manager. “Our team designed, fabricated and tested a novel protection structure combining several elements that will trigger an alert if hackers use the backside of a chip to access the active parts of the IC.”

Surface roughness reduction is a really big deal when it comes to fundamental surface physics and while fabricating electronic and optical devices. As transistor dimensions within integrated circuits continue to shrink, smooth metallic lines are required to interconnect these devices. If the surfaces of these tiny metal lines aren’t smooth enough, it substantially reduces their ability to conduct electrical and thermal energy — decreasing functionality.

A group of engineers at the University of Massachusetts Amherst are now reporting an advance this week in Applied Physics Letters, from AIP Publishing, in the form of modeling results that establish electrical surface treatment of conducting thin films as a physical processing method for reducing surface roughness.

Sequence of snapshots from a computer simulation of electric-field-driven morphological evolution of a copper thin film, demonstrating current-induced smooth surface. Credit: Du and Maroudas

Sequence of snapshots from a computer simulation of electric-field-driven morphological evolution of a copper thin film, demonstrating current-induced smooth surface. Credit: Du and Maroudas

“We’ve been thinking hard about this roughness problem for many years, since showing that electric currents can be used to inhibit surface cracking,” said Dimitrios Maroudas, co-author and a professor in the Department of Chemical Engineering. “So as soon as we developed the computational tools to attack the full film roughness problem, we got to work.”

The group’s work focused on using a copper film on a silicon nitride layer to quantify the model parameters for their simulations and make comparisons with available experimental findings, which they were able to reproduce.

“Surface electromigration is the key physical concept involved,” Maroudas explained. “It’s the directed transport of atoms on the metal surface due to the so-called electron wind force, which expresses the transfer of momentum from the electrons of the metal moving under the action of an electric field to the atoms (ions) — biasing atomic migration.”

Think of it as akin to the diffusion of ink in flowing water. “Electromigration’s role in the transport of surface atoms is analogous to that of convection due to flow on the transport of ink within the water,” Maroudas said. “The combined effects of a well-controlled applied electric field and rough surface geometry drive the atoms on the metal surface to move from the hills of the rough surface morphology to the neighboring valleys, which eventually smooth away the rough surfaces.”

This work is significant, particularly within the microelectronics realm, because it establishes the electrical treatment of metallic (conducting) films as a viable physical processing strategy for reducing their surface roughness.

“Our approach is qualitatively different than traditional mechanical polishing or ion-beam irradiation techniques,” said Lin Du, co-author and a doctoral student working with Maroudas. “It directly influences the driven diffusion of surface atoms precisely, which affects surface atomic motion and enables a smooth surface all the way down to the atomic level.”

The required electric field action can be conveniently controlled macroscopically: simply choose a direction, adjust the voltage, and flip a switch “on.”

“While studying the phenomenon, we discovered that a sufficiently strong electric field can bring the metallic surface to an atomically smooth state,” Du said. “The required electric field strength depends largely on the field direction and surface material properties of the metallic film — such as film texture and surface diffusional anisotropy, because in surfaces of crystalline materials diffusion is faster along certain preferred directions.”

A true irony here is that “electromigration is best known for its damaging effects within metallic interconnects — underlying crucial materials reliability problems in many generations of microelectronics,” Maroudas said.

As far as applications, since this work establishes the principles to create smoother conducting material surfaces, “it can be used for fabricating and processing nanoscale-thick metallic components within electronic and optical devices, which require atomic-scale smoothness,” Maroudas said. “The ability to reduce the surface roughness of metallic components, such as interconnects within integrated circuits, will significantly improve their performance as well as durability and reliability.”

What’s the next step for the engineers? “We’re currently exploring how the effectiveness of the method depends on the metallic film texture (or surface crystallographic orientation), the film’s wetting of the substrate, and the electric field direction with respect to certain surface crystallographic directions,” Maroudas said.

The group’s immediate goal is “to optimize the electrical treatment technique, and to identify the conditions for minimizing the required electric field strength, as well as the cost of applying this technique,” he added. “Our next natural step should be a partnership with an experimental laboratory with the proper expertise to carry out tests that will help us move from proof of concept to an enabling technology.”

Imec, the research and innovation hub in nano-electronics and digital technologies, today announced that their 200mm gallium nitride-on-silicon (GaN-on-Si) e-mode power devices with a pGaN gate architecture showed no degradation after heavy ion and neutron irradiation. The irradiation tests were performed in collaboration with Thales Alenia Space, a leader in innovative space systems. The results demonstrate that imec’s 200mm GaN-on-Si platform delivers state-of-the-art GaN-based power devices for earth as well as for space applications.

GaN-on-silicon transistors operate at higher voltages, frequencies and temperatures than their silicon counterparts. This makes them the ideal candidates for power conversion devices as they show less power losses in electricity conversion. First-generation GaN-based power devices are used today and will play a key role in the power conversion of future electronic devices such as battery chargers, smartphones, computers, servers, automotive, lighting systems and photovoltaics.

Imec has been  developing the next-generation of GaN-based power devices with improved performance and reliability. Imec’s latest 200mm GaN-on-Si platform shows good  wafer-to-wafer reproducibility and low dynamic Rdson. The platform is currently available for dedicated development or technology transfer to imec’s current and future partners.

imec Ron

Imec’s latest generation of  200mm GaN-on-Si e-mode pGaN devices were irradiated with heavy ions (Xenon) and neutrons. Pre and post irradiation tests revealed that there was no permanent degradation of transistor characteristics: no shifts in threshold voltage nor gate rupture. The excellent radiation hardness of imec’s devices is important, as it enables applications in space, where fluxes of heavy ions and neutrons can damage electronic circuits in satellites and space stations.

Thales Alenia Space Belgium has surveyed, since many years, the evolution in the field of wide band gap devices. These family of components is promising for a significant increase in performances. But, robustness to space radiation is mandatory for electronic devices in our equipment’s. The result obtained with Imec’s GaN-on-Si devices is an important step in the way to space based power conversion applications.

“These results are important to start using this promising technology for space applications. Also, it demonstrates that our 200mm GaN-on-Si platform has reached a high level of technology readiness and can be adopted by industry,” stated Rudi Cartuyvels, Executive Vice President at imec. “At imec, we use 200mm silicon substrates for GaN epitaxy and this technology can be used on 200mm CMOS-compatible infrastructure. Thanks to innovations in transistor architecture and substrate technology, we’ve succeeded in making GaN devices on larger wafer diameters than used today, which brings lower cost perspectives for the second generation of GaN-on-Si power devices. Imec is also looking beyond today’s technology, exploring novel substrates, higher level of integrations and novel devices.”

These results were achieved in the framework of the European Space Agency (ESA) project “ESA AO/1-7688/13/NL/RA”, GaN devices for space based DC-DC power conversion applications.

Andrew Barnes ESA Technical Officer overseeing the project stated: “GaN is a critical technology for future space missions with a wide range of potential applications, including smaller size, higher efficiency DC-DC power conversion subsystems. These results, obtained from the first phase of an ESA GSTP project, are important and show that the p-GaN devices developed by imec offer excellent radiation robustness for operation in space. In the second phase of the project it is planned to industrialize this technology in readiness for a future space qualification program”. The European Space Agency (ESA) is Europe’s gateway to space. Its mission is to shape the development of Europe’s space capability and ensure that investment in space continues to deliver benefits to the citizens of Europe and the world.

Today, SEMI announced updates to its World Fab Forecast report, revealing that fab equipment spending is expected to reach an industry all-time record − more than US$46 billion in 2017.  The record is expected to be broken again in 2018, nearing the $50 billion mark. These record-busting years are part of three consecutive years of growth (2016, 2017 and 2018), which has not occurred since the mid-1990s. The report has been the industry’s most trusted data source for 24 years, observing and analyzing spending, capacity, and technology changes for all front-end facilities worldwide. See Figure 1.

fab equipment spending

Figure 1: Fab Equipment Spending (Front End Facilities)

SEMI‘s World Fab Forecast report (end of February 2017) provides updates to 282 facilities and lines equipping in 2017, 11 of which are expected to spend over $1 billion each in 2017. In 2018, SEMI’s data reflect 270 fabs to equip, with 12 facilities spending over $1 billion each.  The spending is mainly directed towards memory (3D NAND and DRAM), Foundry and MPU.  Other strong product segments are Discretes (with LED and Power), Logic, MEMS (with MEMS/RF), and Analog/Mixed Signal.

SEMI (www.semi.org) forecasts that China will be third for regional spending in 2017, although China’s annual growth is minimal in 2017 (about 1 percent), as many of the new fab projects are in the construction phase.  China is busy constructing 14 new fabs in 2017 and these new fabs will be equipping in 2018. China’s annual spending growth rate in 2018 will be over 55 percent (more than $10 billion), and ranking in second place for worldwide spending in 2018.  In total for 2017, China is equipping 48 fabs, with equipment spending of $6.7 billion; looking ahead to 2018, SEMI predicts that 49 fabs to be equipped, with spending of about $10 billion.

Other regions also show solid growth rates.  The SEMI World Fab Forecast indicates that Europe/Mideast and Korea are expected to make the largest leaps in terms of growth rates this year with 47 percent growth and 45 percent growth, respectively, year-over-year (YoY).  Japan will increase spending by 28 percent, followed by the Americas with 21 percent YoY growth.

The SEMI Industry Research & Statistics team has made 195 changes on 184 facilities/lines in the last quarter, with eight new facilities added and three fab projects cancelled. SEMI’s World Fab Forecast provides detailed information about each of these fab projects, such as milestone dates, spending, technology node, products, and capacity information. The World Fab Forecast Report, in Excel format, tracks spending and capacities for over 1,100 facilities including future facilities across industry segments.  The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, in-house equipment, and spending on facilities for equipment. Also check out the Opto/LED Fab Forecast.

Cypress Semiconductor Corp. (Nasdaq:  CY) today announced it has sold the subsidiary that owns its semiconductor wafer fabrication facility in Bloomington, Minnesota to SkyWater Technology Foundry for $30 million. Backed by Minnesota-based holding company Oxbow Industries, LLC, SkyWater Technology has purchased the capital stock of the subsidiary and will operate the fab as a standalone business that will manufacture wafers for Cypress and for other semiconductor manufacturers. The transaction allows Cypress to reduce its manufacturing footprint and cost structure while increasing the utilization of its Fab 25 in Austin, Texas, in line with the company’s plan to improve gross margins. Seattle-based ATREG, Inc. acted as Cypress’ advisor in this operational fab sale.

“This transaction demonstrates our commitment to reshape Cypress and improve gross margin, in line with our long-term financial model,” said Hassane El-Khoury, Cypress President and CEO. “The sale of Fab 4 in Minnesota allows us to reduce our manufacturing costs as we exit the fab while using the proceeds to pay down debt. We will also be able to improve the utilization and efficiency of Fab 25 in Texas, into which we have been transitioning products over the last 18 months. We believe this agreement represents another milestone in our path to achieving higher gross margins.

“In addition to looking at a potential deal’s impact on Cypress’ bottom line, we set out to ensure uninterrupted supply for our customers,” continued El-Khoury. “This agreement allows Cypress to maintain uninterrupted wafer supply for our products manufactured at the fab, with no disruptions for our customers, and it gives our former employees in Minnesota the opportunity to help the new business flourish and continue the fab’s tradition of quality U.S.-based manufacturing.”

“Given the proven history of efficiency at Fab 4, the expertise and dedication of its workforce and its established success in delivering specialized wafers on time to a diverse customer base, the SkyWater management team sees a strong foundation for growing a standalone business,” said Dr. Scott Nelson, Chief Technology Officer of SkyWater Technology Foundry. “We are committed to continuing the fab’s support of Cypress and its customers with superior quality and on-time delivery.”

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $30.6 billion for the month of January 2017, an increase of 13.9 percent compared to the January 2016 total of $26.9 billion. Global sales in January were 1.2 percent lower than the December 2016 total of $31.0 billion, reflecting normal seasonal market trends. January marked the global market’s largest year-to-year growth since November 2010. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor industry is off to a strong and encouraging start to 2017, posting its highest-ever January sales and largest year-to-year sales increase in more than six years,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Sales into the China market increased by more than 20 percent year-to-year, and most other regional markets posted double-digit growth. Following the industry’s highest-ever revenue in 2016, the global market is well-positioned for a strong start to 2017.”

Year-to-year sales increased substantially across all regions: China (20.5 percent), the Americas (13.3 percent), Japan (12.3 percent), Asia Pacific/All Other (11.0 percent), and Europe (4.8 percent). Month-to-month sales increased in Europe (1.2 percent), but fell slightly in China (-0.2 percent), Japan (-1.6 percent), Asia Pacific/All Other (-1.6 percent), and the Americas (-3.1 percent).

January 2017

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

6.33

6.13

-3.1%

Europe

2.80

2.84

1.2%

Japan

2.84

2.79

-1.6%

China

10.17

10.15

-0.2%

Asia Pacific/All Other

8.86

8.72

-1.6%

Total

31.01

30.63

-1.2%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

5.41

6.13

13.3%

Europe

2.71

2.84

4.8%

Japan

2.49

2.79

12.3%

China

8.42

10.15

20.5%

Asia Pacific/All Other

7.86

8.72

11.0%

Total

26.89

30.63

13.9%

Three-Month-Moving Average Sales

Market

Aug/Sept/Oct

Nov/Dec/Jan

% Change

Americas

6.06

6.13

1.2%

Europe

2.82

2.84

0.7%

Japan

2.89

2.79

-3.2%

China

9.78

10.15

3.7%

Asia Pacific/All Other

8.88

8.72

-1.8%

Total

30.43

30.63

0.7%

 

At the CS International Conference (Brussels, March 7-8), imec will present promising device results with a InGaAs-only TFET (tunnel field-effect transistor). Achieving a sub-60 mV/decade sub-threshold swing at room temperature, these devices are promising candidates to replace MOSFET transistors in future chip generations for ultralow-power applications operating on ultralow supply voltages.

TFETs exploit a different mechanism to inject carriers than MOSFETs, the most dominant transistor type today. While MOSFETs introduce carriers from the source into the conducting channel by thermal injection, a TFET works through band-to-band tunneling (BTBT). With that, they promise sub-threshold swings smaller than 60mV/dec, which is below the limit of what is possible with MOSFETs. This would allow operating them at ultralow supply voltages (below 0.5V).

The device developed at imec is an InGaAs homojunction TFET. It shows a minimum sub-threshold swing of 54mV/dec at 100pA/mm. The sub-threshold swing remains sub-60mV/dec over 1.5 orders of magnitude of current at room temperature. The EOT of the devices is 0.8nm, which plays a major role in achieving the desired sub-60 mV/dec performance.

“We have entered an era where new chip technologies require making trade-offs between power, performance, cost and area. And these trade-offs will be considered separately for different application domains,” says Nadine Collaert, distinguished member of technical staff at imec. “TFETs will most probably find their place in the ultralow-power segment. Many applications in the future require transistors to work at low power and low voltage, such as the many Internet of Things applications.

At CS International, imec’s expert Nadine Collaert will discuss the progress made and challenges ahead in processing TFETs, focusing on the materials and integration, but also on the impact of using TFETs in electronic circuits.

Semiconductor manufacturing thought leaders will convene at the annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2017) on May 15-18 in Saratoga Springs, New York. The conference will feature 35 hours of technical presentations and over 100 experts addressing all aspects of advanced semiconductor manufacturing. This year’s event features a panel discussion on “The Next Big Thing: Technology Drivers for Next-Gen Manufacturing − Where will the Road take Us?” and a tutorial on Piezoelectric MEMS by Professor Gianluca Piazza, director of Nanofabrication Facility, Carnegie Mellon University.

SEMI‘s ASMC continues to provide a venue for industry professionals to network, learn and share knowledge on new and best-method semiconductor manufacturing practices and concepts.  The conference is co-chaired by Delphine LeCunff of STMicroelectronics and Russell Dover of Lam Research.  ASMC 2017 offers keynotes by Roberto Rapp, VP of Manufacturing at Robert Bosch GmbH; William Miller, VP of Engineering of Qualcomm; and Robert Maire, president of Semiconductor Advisors.

The topical areas that ASMC 2017 will address include:

  • 3D and Power Technologies
  • Advanced Equipment and Materials Processes
  • Advanced Metrology
  • Advanced Patterning
  • Advanced Process Control (APC)
  • Contamination Free Manufacturing (CFM)
  • Yield Management; Defect Inspection
  • Equipment Reliability and Productivity Enhancement
  • Factory Optimization

ASMC includes an interactive poster session and reception, which provides an ideal opportunity for networking between presenters and conference attendees.

The new ‘Women in Semiconductors‘ program takes place on May 15 in conjunction with ASMC 2017.  Sponsored by Applied Materials, GLOBALFOUNDRIES, IBM, Nikon and TEL, the program will focus on “The Power of Talk: Getting a Seat at the Table.”  Registration is complimentary for ASMC attendees.

ASMC 2017 is presented by SEMI with technical sponsors: Institute of Electrical & Electronics Engineers (IEEE), IEEE Electron Devices Society (EDS), and IEEE Components, Packaging and Manufacturing Technology Society (CPMT). Corporate sponsors include: BisTEL, Edwards, GreeneTweed, KLA-Tencor, Mellor Consulting Group, Nikon, and Valqua America.

Registration for the SEMI Advanced Semiconductor Manufacturing Conference (ASMC) is available at www.semi.org/asmc.  For more information, contact Margaret Kindling at [email protected] or phone 1.202.393.5552. Qualified members of the media are invited to contact Deborah Geiger (SEMI Public Relations) at [email protected] for media registration information.