Category Archives: Device Architecture

Unwavering in its drive to build a strong, self-sufficient semiconductor supply chain, China plans more new fab projects than any other region in the world from 2017 to 2020, and its expansion of fab capacity recently picked up pace on the strength of new foundry and memory projects from both domestic and foreign companies, according to SEMI’s 2018 China Semiconductor Silicon Wafer Outlook report. China’s installed fab capacity is forecast to grow at a 12 percent CAGR from 2.3 million wafers per month (wpm) in 2015 to 4 million wpm in 2020, faster than all other regions.

Well known for its semiconductor packaging prowess, China in recent years shifted its focus to front-end semiconductor fabs and a few key material markets. In 2018, the region’s surge in fab investment thrust it past Taiwan as the second largest capital equipment market in the world, behind only Korea.

However, China’s semiconductor manufacturing growth faces strong headwinds. Chief among them is the tight supply of silicon wafers over the past two years due in large part to the sector oligopoly’s firm control of global production, with the top five wafer manufacturers accounting for over 90 percent of market revenue. In response, China’s central and local governments has made the development of its domestic silicon wafer supply chain a key initiative, funding multiple silicon wafer manufacturing projects.

According to the 2018 China Semiconductor Silicon Wafer Outlook report, many of China’s domestic silicon suppliers capably provide wafers 150mm in size and smaller. And the while the region lags peers in 200m and 300mm processing technology and capacity, strong domestic demand and favorable policies have fueled progress in 200mm and 300mm silicon manufacturing with some Chinese suppliers having reached key large-diameter manufacturing milestones.

However, it will take these new suppliers several years before they can meet capacity and yield requirements of the larger-diameter silicon wafer market. Company plans and announcements indicate that by the end of 2020, total silicon supply capacity in China will reach 1.3 million wpm for 200mm, possibly leading to a slight oversupply, and 750,000 wpm for 300mm.

China’s equipment suppliers, particularly crystal furnace vendors, are also investing in the development of 300mm wafer manufacturing, and domestic tool suppliers have developed most of the necessary tools for wafer manufacturing, except for inspection.

While China’s silicon wafer suppliers continue to lag international peers in manufacturing capabilities, the region’s silicon manufacturing ecosystem is maturing and becoming better integrated. The sector’s growth is driven and accelerated by significant domestic market demand and favorable policies.

Today, Mobile Semiconductor announced their new 22nm FDX ULP (Ultra Low Power) Memory Compiler complete with a comprehensive set of features that cement their leadership position in FDX Memory Compiler offerings.

This new Memory Compiler offers an Ultra-Low Power mode at 0.65V that is useful to a wide range of wearable and battery powered devices.  The 22nm FDX ULP joins their expanding 22nm FDX Memory Compiler family that currently covers a wide range of speeds, power requirements, and ultra-low leakage offerings.  The 22nm ULP product draws from the expertise developed over the past three years with our successful 28nm and 55nm Memory Compilers.

Cameron Fisher, CEO and Founder of Mobile Semiconductor, said, “We believe our approach to anticipating the needs of engineers, and building in industry leading features, set us apart.  Examples mentioned by current customers includes low power level shifters and isolation cells.  Without these features, the designer cannot power off the memory entirely resulting in wasted energy and a substandard product.  Mobile Semiconductor Memory Compilers truly allow for complete power down and rapid start-up.”

The Mobile Semiconductor / GlobalFoundries 22FDX platform include 100% of what a design team demands:

  • 0.65V and 0.5V Logic Support
  • Integrated Power Solutions
  • Output Isolation
  • Multiple Power Modes
  • Single Port and Register File Compilers
  • Pseudo Dual Port Support
  • Flexible Reverse Body Bias Support

Fisher continued, “Mobile Semiconductor remains the leader in providing low power memory complier solutions.  But it’s not enough to have a feature rich offering on one product like the 22nm FDX ULP, we also believe that it’s our obligation to provide a range of other products such as 28nm and 55nm AND to design them with the features that best support the demands of the market segments.”

By Junko Collins

The SEMI International Standards program is operated in all major electronics manufacturing regions including the Americas, Europe, Japan, Korea, Taiwan and China to increase the manufacturing efficiency and interoperability. More than 5,000 volunteers representing over 2,000 companies work in 20 global technical committees and over 200 task forces to find solutions to common technology challenges.

At SEMICON Japan 2019 – December 12-14 at Tokyo Big Sight, Tokyo – SEMI recognized two industry veterans active in the Japan chapter for their longtime contributions to the SEMI International Standards program. The award ceremony took place on December 13 with 56 Standards committee members and SEMI executives including Ajit Manocha, president and CEO of SEMI, and Jim Hamajima, president of SEMI Japan, in attendance.

Hiromichi Enami of Hitachi High-Technologies Corporation and Isao Suzuki of MKS Japan Receive SEMI Japan Honor Award. Left to right: Jim Hamajima (SEMI), Ajit Manocha (SEMI), Hiromichi Enami (Hitachi High-Technologies), Isao Suzuki, James Amano (SEMI) and Mike Ciesinski (SEMI)

Contributing to SEMI Standards for more than 20 years, Mr. Hiromichi Enami of Hitachi High-Technologies Corporation has been dedicated to committee management by acting as co-chair of the Gases Technical Committee and the Facilities Technical Committee. In addition, as chairman of the division, he has strived for harmonization with other committees and regions. (The current SEMI International Standards program has no division structure).

Mr. Isao Suzuki, formerly of MKS Japan, is also a long-time contributor to the SEMI standards activities, having demonstrated his commitment to the management of the Gases Technical Committee and as a co-chair of the Facilities Technical Committee. He has also made significant efforts towards cooperation with Information & Control Committee activities related to sensor bus activities.

The SEMI Japan Honor Award is given to members who has contributed to the SEMI International Standards program as a member of Japan Regional Standards Committee or as a Global Technical Committee Japan Chapter co-chair for more than four years.

By Junko Collins, director of Standards and EHS, SEMI Japan

A research study on low noise and high-performance transistors led by Suprem Das, assistant professor of industrial and manufacturing systems engineering, in collaboration with researchers at Purdue University, was recently published by Physical Review Applied.

The study has demonstrated micro/nano-scale transistors made of two-dimensional atomic thin materials that show high performance and low noise. The devices are less than one-hundredth of the diameter of a single human hair and could be key to innovating electronics and precision sensing.

Many researchers worldwide are focusing attention on building the next generation of transistors from atomic scale “exotic” 2D materials such as molybdenum di-selenide. These materials are promising because they show high-performance transistor-action that may, in the future, replace today’s silicon electronics. However, very few of them are looking at yet another important aspect: the inherent electronic noise in this new class of materials. Electronic noise is ubiquitous to all devices and circuits and only worsens when the material becomes atomic thin.

A recent study conducted by Das’ research team has systematically shown that if one can control the layer thickness between 10 and 15-atomic thin in a transistor, the device will not only show high performance — such as turning the switch “on” — but also experience very low electronic noise. This unique finding is essential to building several enabling technologies in electronics and sensing using a number of emerging 2D materials. This research is a comprehensive effort of a previous finding, where Das’ team conducted the first study on noise in MoSe2 transistors.

Synopsys, Inc. (Nasdaq: SNPS) today announced that the Liberty Technical Advisory Board (LTAB) and Interconnect Modeling Technical Advisory Board (IMTAB) have ratified new modeling constructs to address timing and parasitic extraction challenges at process nodes down to two nanometers (nm). Mobile device requirements for ultra-low power and manufacturing challenges require new approaches to ensure the best accuracy at signoff while enabling design tools to optimize for the lowest power consumption. In addition, device architectures, mask, and patterning techniques at these nodes result in artifacts that must be modeled by new extensions in the interconnect technology file (ITF).

In power analysis, the Liberty standard has been enhanced to provide better insight into the assumptions use for computation of dynamic power values in the library models. Extraction modeling in the ITF file now addresses gate resistance for new device architectures, as well as patterning extensions on interconnect and trench contact structures.

“Through close collaboration with leading foundries and IDMs, we are able to keep modeling standards out in front of the next wave of advanced process nodes,” said Jacob Avidan, senior vice president of engineering in Synopsys’ Digital Group. “The latest modeling enhancements ratified by the Liberty and ITF technical advisory boards are essential to achieving timing and power requirements that allow our partners to bring the highest quality designs to market in the shortest time possible.”

All LTAB/IMTAB proposals have been quickly incorporated into Synopsys’ Fusion Design Platform™to enable support for early technology adopters. Tools in the Fusion Design Platform include Design Compiler® synthesis, IC Compiler™ II place-and-route, StarRC® extraction, PrimeTime®signoff, and PrimePower power analysis.

North America-based manufacturers of semiconductor equipment posted $1.94 billion in billings worldwide in November 2018 (three-month average basis), according to the November Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 4.2 percent lower than the final October 2018 level of $2.03 billion, and is 5.3 percent lower than the November 2017 billings level of $2.05 billion.

“For the first time in over two years, billings of North American equipment manufacturers are down relative to the same month the year before,” said Ajit Manocha, president and CEO of SEMI. “After reaching historical revenues earlier this year, billings activity is decelerating in line with weaker growth expectations for 2019.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg.)
Year-Over-Year
June 2018
$2,484.3
8.0%
July 2018
$2,377.9
4.8%
August 2018
$2,236.8
2.5%
September 2018 (final)
$2,078.6
1.2%
October 2018 (final)
$2,029.2
0.5%
November 2018 (prelim)
$1,943.9
5.3%

Source: SEMI (www.semi.org), December 2018

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

In microelectronic devices, the bandgap is a major factor determining the electrical conductivity of the underlying materials. Substances with large bandgaps are generally insulators that do not conduct electricity well, and those with smaller bandgaps are semiconductors. A more recent class of semiconductors with ultrawide bandgaps (UWB) are capable of operating at much higher temperatures and powers than conventional small-bandgap silicon-based chips made with mature bandgap materials like silicon carbide (SiC) and gallium nitride (GaN).

In the Journal of Applied Physics, from AIP Publishing, researchers at the University of Florida, the U.S. Naval Research Laboratory and Korea University provide a detailed perspective on the properties, capabilities, current limitations and future developments for one of the most promising UWB compounds, gallium oxide (Ga2O3).

Gallium oxide possesses an extremely wide bandgap of 4.8 electron volts (eV) that dwarfs silicon’s 1.1 eV and exceeds the 3.3 eV exhibited by SiC and GaN. The difference gives Ga2O3 the ability to withstand a larger electric field than silicon, SiC and GaN can without breaking down. Furthermore, Ga2O3 handles the same amount of voltage over a shorter distance. This makes it invaluable for producing smaller, more efficient high-power transistors.

“Gallium oxide offers semiconductor manufacturers a highly applicable substrate for microelectronic devices,” said Stephen Pearton, professor of materials science and engineering at the University of Florida and an author on the paper. “The compound appears ideal for use in power distribution systems that charge electric cars or converters that move electricity into the power grid from alternative energy sources such as wind turbines.”

Pearton and his colleagues also looked at the potential for Ga2O3 as a base for metal-oxide-semiconductor field-effect transistors, better known as MOSFETs. “Traditionally, these tiny electronic switches are made from silicon for use in laptops, smart phones and other electronics,” Pearton said. “For systems like electric car charging stations, we need MOSFETs that can operate at higher power levels than silicon-based devices and that’s where gallium oxide might be the solution.”

To achieve these advanced MOSFETs, the authors determined that improved gate dielectrics are needed, along with thermal management approaches that will more effectively extract heat from the devices. Pearton concluded that Ga2O3 will not replace SiC and GaN as the as the next primary semiconductor materials after silicon, but more likely will play a role in extending the range of powers and voltages accessible to ultrawide bandgap systems.

“The most promising application might be as high-voltage rectifiers in power conditioning and distribution systems such as electric cars and photovoltaic solar systems,” he said.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of an update to JESD235 High Bandwidth Memory (HBM) DRAM standard. HBM DRAM is used in Graphics, High Performance Computing, Server, Networking and Client applications where peak bandwidth, bandwidth per watt, and capacity per area are valued metrics to a solution’s success in the market. The standard was developed and updated with support from leading GPU and CPU developers to extend the system bandwidth growth curve beyond levels supported by traditional discrete packaged memory. JESD235B is available for download from the JEDEC website.

JEDEC standard JESD235B for HBM leverages Wide I/O and TSV technologies to support densities up to 24 GB per device at speeds up to 307 GB/s. This bandwidth is delivered across a 1024-bit wide device interface that is divided into 8 independent channels on each DRAM stack. The standard can support 2-high, 4-high, 8-high, and 12-high TSV stacks of DRAM at full bandwidth to allow systems flexibility on capacity requirements from 1 GB – 24 GB per stack.

This update extends the per pin bandwidth to 2.4 Gbps, adds a new footprint option to accommodate the 16 Gb-layer and 12-high configurations for higher density components, and updates the MISR polynomial options for these new configurations. Additional clarifications are provided throughout the document to address test features and compatibility across generations of HBM components.

An international research team, co-led by a physicist at the University of California, Riverside, has discovered a new mechanism for ultra-efficient charge and energy flow in graphene, opening up opportunities for developing new types of light-harvesting devices.

Shining light on graphene: Although graphene has been studied vigorously for more than a decade, new measurements on high-performance graphene devices have revealed yet another unusual property. In ultra-clean graphene sheets, energy can flow over great distances, giving rise to an unprecedented response to light. Credit: Max Grossnickle and QMO Labs, UC Riverside.

The researchers fabricated pristine graphene — graphene with no impurities — into different geometric shapes, connecting narrow ribbons and crosses to wide open rectangular regions. They found that when light illuminated constricted areas, such as the region where a narrow ribbon connected two wide regions, they detected a large light-induced current, or photocurrent.

The finding that pristine graphene can very efficiently convert light into electricity could lead to the development of efficient and ultrafast photodetectors — and potentially more efficient solar panels.

Graphene, a 1-atom thick sheet of carbon atoms arranged in a hexagonal lattice, has many desirable material properties, such as high current-carrying capacity and thermal conductivity. In principle, graphene can absorb light at any frequency, making it ideal material for infrared and other types of photodetection, with wide applications in bio-sensing, imaging, and night vision.

In most solar energy harvesting devices, a photocurrent arises only in the presence of a junction between two dissimilar materials, such as “p-n” junctions, the boundary between two types of semiconductor materials. The electrical current is generated in the junction region and moves through the distinct regions of the two materials.

“But in graphene, everything changes,” said Nathaniel Gabor, an associate professor of physics at UCR, who co-led the research project. “We found that photocurrents may arise in pristine graphene under a special condition in which the entire sheet of graphene is completely free of excess electronic charge. Generating the photocurrent requires no special junctions and can instead be controlled, surprisingly, by simply cutting and shaping the graphene sheet into unusual configurations, from ladder-like linear arrays of contacts, to narrowly constricted rectangles, to tapered and terraced edges.”

Pristine graphene is completely charge neutral, meaning there is no excess electronic charge in the material. When wired into a device, however, an electronic charge can be introduced by applying a voltage to a nearby metal. This voltage can induce positive charge, negative charge, or perfectly balance negative and positive charges so the graphene sheet is perfectly charge neutral.

“The light-harvesting device we fabricated is only as thick as a single atom,” Gabor said. “We could use it to engineer devices that are semi-transparent. These could be embedded in unusual environments, such as windows, or they could be combined with other more conventional light-harvesting devices to harvest excess energy that is usually not absorbed. Depending on how the edges are cut to shape, the device can give extraordinarily different signals.”

The research team reports this first observation of an entirely new physical mechanism — a photocurrent generated in charge-neutral graphene with no need for p-n junctions — in Nature Nanotechnology today.

Previous work by the Gabor lab showed a photocurrent in graphene results from highly excited “hot” charge carriers. When light hits graphene, high-energy electrons relax to form a population of many relatively cooler electrons, Gabor explained, which are subsequently collected as current. Even though graphene is not a semiconductor, this light-induced hot electron population can be used to generate very large currents.

“All of this behavior is due to graphene’s unique electronic structure,” he said. “In this ‘wonder material,’ light energy is efficiently converted into electronic energy, which can subsequently be transported within the material over remarkably long distances.”

He explained that, about a decade ago, pristine graphene was predicted to exhibit very unusual electronic behavior: electrons should behave like a liquid, allowing energy to be transferred through the electronic medium rather than by moving charges around physically.

“But despite this prediction, no photocurrent measurements had been done on pristine graphene devices — until now,” he said.

The new work on pristine graphene shows electronic energy travels great distances in the absence of excess electronic charge.

The research team has found evidence that the new mechanism results in a greatly enhanced photoresponse in the infrared regime with an ultrafast operation speed.

“We plan to further study this effect in a broad range of infrared and other frequencies, and measure its response speed,” said first author Qiong Ma, a postdoctoral associate in physics at the Massachusetts Institute of Technology, or MIT.

Advances in the technology of material growth allow fabricating sandwiches of materials with atomic precision. The interface between the two materials can sometimes exhibit physical phenomena which do not exist in both parent materials. For example, a magnetic interface found between two non-magnetic materials. A new discovery, published today in Nature Physics, shows a new way of controlling this emergent magnetism which may be the basis for new types of magnetic electronic devices.

Sensitive magnetic imaging detects strain tunable magnetism. Credit: Kalisky Lab

Using very sensitive magnetic probes, an international team of researchers led by Prof. Beena Kalisky, of Bar-Ilan University’s Department of Physics and Institute of Nanotechnology and Advanced Materials (BINA), has found surprising evidence that magnetism which emerges at the interfaces between non-magnetic oxide thin layers can be easily tuned by exerting tiny mechanical forces. The team also includes Prof. Lior Klein, of Bar-Ilan’s Department of Physics and BINA, and researchers from DTU (Denmark) and Stanford University (USA).

Magnetism already plays a central role in storing the increasing amount of data produced by humanity. Much of our data storage today is based on tiny magnets crammed into our memory drive. One of the promising means in the race to improve memory, in terms of quantity and speed, is the use of smaller magnets. Until today the size of memory cells can be as small as a few tens of nanometers — almost a millionth of the width of a strand of hair! Further reduction in size is challenging in three main respects: the stability of the magnetic cell, the ability to read it, and the ability to write into it without affecting its neighboring cells. This recent discovery provides a new and unexpected handle to control magnetism, thus enabling denser magnetic memory.

These oxide interfaces combine a number of interesting physical phenomena, such as two-dimensional conductance and superconductivity. “Coexistence of physical phenomena is fascinating because they do not always go hand in hand. Magnetism and superconductivity, for example, are not expected to coexist,” says Kalisky. “The magnetism we saw did not extend throughout the material but appeared in well-defined areas dominated by the structure of the materials. Surprisingly, we discovered that the strength of magnetism can be controlled by applying pressure to the material”.

Coexistence between magnetism and conductivity has great technological potential. For example, magnetic fields can affect the current flow in certain materials and, by manipulating magnetism, we can control the electrical behavior of electronic devices. An entire field called Spintronics is dedicated to this subject. The discovery that tiny mechanical pressures can effectively tune the emerging magnetism at the studied interfaces opens new and unexpected routes for developing novel oxide-based spintronic devices.