Category Archives: Device Architecture

By Paula Doe, SEMI

The explosive growth in demand for internet bandwidth and cloud computing capacity brings a new set of technology challenges and opportunities for the semiconductor supply chain. “Azure grew by 2X last year, but we can’t pull more performance out of the existing architecture,” noted Kushagra Vaid, Microsoft’s GM Hardware Engineering, Cloud & Enterprise, at last week’s Linley Cloud Hardware Conference in Santa Clara, Calif.  “We are at a junction point where we have to evolve the architecture of the last 20-30 years.” He stressed that the traditional way of designing chips and systems to optimize for particular workloads isn’t working anymore. “We can’t design for a workload so huge and diverse. It’s not clear what part of it runs on any one machine,” he noted. “How do you know what to optimize? Past benchmarks are completely irrelevant.”

Explosive growth in demand for data storage and processing in the cloud means change across the chip world. Source: Cisco VNI Global IP Traffic Forecast

Explosive growth in demand for data storage and processing in the cloud means change across the chip world. Source: Cisco VNI Global IP Traffic Forecast

Roadmap accelerates for networking chips 

Look for accelerating change in the networking chip market. Now that merchant chip suppliers have taken over 75 percent of the networking chip market from the proprietary suppliers, intense competition has meant astonishing improvements in reducing size and power, and two-year technology cycles, reported keynote speaker Andreas Bechtolsheim, Arista Networks Chief Development Officer and Chairman.  “The cloud is accelerating transitions, as the big data centers demand low cost,” he noted, explaining that new technologies no longer see gradual adoption through different applications. They have to start out cheaper to get any traction at all, but then ramp sharply to high volume in six months as high-volume data centers convert.

Data center networks expect transition to 400G to start in 2018. Source: MACOM

Data center networks expect transition to 400G to start in 2018. Source: MACOM

Bechtolsheim said the majority of the network link market will convert from 40G to 100G this year, and to 400G in 2019.  For 800G two years later, chip design will have to start this year. Luckily there’s a clear path for scaling on the chip side, from the current generation’s 28nm technology down to 16nm and 7nm.  But it could be a push for some of the ecosystem. “It’s pushing the packaging vendors, as 1.0mm solder balls are about the limit,” said Bechtolsheim. Companies are also forming a group to speed the standards process by making the 800G standard simply 2X that for 400G, as the 400B standard took eight years.

The 40G chips at the server layer are moving to pulse amplitude modulation (PAM4) to send and receive four signals at once, which will require moving to digital signal processing. Moving from analog bipolar to digital CMOS technology also enables significant scaling of chip size and power, with significant reduction in die area (~50 percent) and power (~40 percent) with 16nm FinFET compared to 28nm, noted MACOM’s Chris Collins, director of Marketing. The company plans 7nm 800G devices next year.

New layers and new types of memory

One likely change is new types and new placement for memory, for higher speeds, different levels of non-volatile cache, and designs and accelerator subsystems that limit the need to move large amounts of data back and forth over limited pipelines. “Data is doubling every 2-2.5 years, but DRAM bandwidth is only doubling every 5 years. It’s not keeping up,” noted Steven Woo, Rambus VP, Systems and Solutions. “We’ll see the addition of more tiers of memory over the next few years.” He suggested the emerging challenge would be what data to place where, using what technology, and how to move memory in general closer to the processing. Racks may become the basic unit instead of servers, so each can be optimized with more memory or more processors as needed.

Handling big data in the cloud means more opportunity for new memory technologies in an emerging tier between DRAM and solid state drives. Source: Rambus

Handling big data in the cloud means more opportunity for new memory technologies in an emerging tier between DRAM and solid state drives. Source: Rambus

Specialized accelerators speed particular applications

Another emerging solution is specialized chips or subsystem boards to accelerate particular types of cloud processing by taking over some jobs from the CPU cores, typically with different types of processors and lots of localized memory. Google and Wave Computing have their accelerator chips optimized for neural network processing. Mellanox offers offload adopter cards based on ASICs, FPGAs or RISC, with increasingly complex functions, claiming the potential to offload as much as of 80 percent of the overhead function of the CPU, to get a 2.7X increase in throughput per server.  MoSys proposes replacing conventional content addressable memory with a programmable search engine, based on an FPGA, a lot of SRAM, and software to search and route with different strategies for different types of applications to significantly increase speeds. Chelsio offers a module to handle encryption and decryption off the CPU without having to shuttle information back and forth to memory. Amazon even is renting FPGAs in its cloud so users can design their own accelerators for their particular workloads. But Microsoft’s Vaid remained skeptical that a proliferation of solutions for particular applications would be the best approach for the general use in the cloud.

300mm production and passive fiber alignment improve silicon photonics

Silicon photonics technology continues to make progress, and may find application in the market for very high bandwidth, mid to long haul transmission (30 meters to 80 kilometer), where spectral efficiency is the key driver, suggested Ted Letavic, Global Foundries, Senior Fellow. “4.5 and 5G communications will use photonics solutions similar to those needed in the data center, for volume that will drive down cost,” he noted. The foundry has now transferred its monolithic process to 300mm wafers, where the immersion lithography enables better overlay and line edge roughness, to reduce losses by 3X.  The company has an automated, passive solution to attach the optical fiber to the edge of the chip, pushing ribbons of multiple fibers into MEMS groves in the chip with an automated pick and place tool.  Letavic said the edge coupling process was in production for a telecommunications application.

Array of optical fibers are passively aligned by sliding into MEMS grooves at the side of the chip for 100Gpbs x 12 = 1.2Tb interconnect in flat form factor. Source: Global Foundries

Array of optical fibers are passively aligned by sliding into MEMS grooves at the side of the chip for 100Gpbs x 12 = 1.2Tb interconnect in flat form factor. Source: Global Foundries

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Intel continued to top all other chip companies in R&D expenditures in 2016 with spending that reached $12.7 billion and represented 22.4% of its semiconductor sales last year.  Intel accounted for 36% of the top-10 R&D spending and about 23% of the $56.5 billion total worldwide semiconductor R&D expenditures in 2016, according to the 20th anniversary 2017 edition of The McClean Report that was released in January 2017.  Figure 1 shows IC Insights’ ranking of the top semiconductor R&D spenders based on semiconductor manufacturers and fabless suppliers with $1 billion or more spent on R&D in 2016.

Figure 1

Figure 1

Intel’s R&D spending is lofty and exceeded the combined R&D spending of the next three companies on the list. However, the company’s R&D expenditures increased 5% in 2016, below its 9% average increase in spending per year since 2011 and less than its 8% annual growth rate since 2001, according to the new report.

Underscoring the growing cost of developing new IC technologies, Intel’s R&D-to-sales ratio has climbed significantly over the past 20 years.  In 2010, Intel’s R&D spending as a percent of sales was 16.4%, compared to 22.4% in 2016. Intel’s R&D-to-sales ratios were 14.5% in 2005, 16.0% in 2000, and just 9.3% in 1995.

Among other top-10 R&D spenders, Qualcomm—the industry’s largest fabless IC supplier—remained the second-largest R&D spender, a position it first achieved in 2012.  Qualcomm’s semiconductor-related R&D spending was down 7% in 2016 compared to an adjusted total in 2015 that included expenditures by U.K.-based CSR and Ikanos Communications in Silicon Valley, which were acquired in 2015.  Broadcom Limited—which is the new name of Avago Technologies after it completed its $37 billion acquisition of U.S-based Broadcom Corporation in early 2016—was third in the R&D ranking. Excluding Broadcom’s expenditures in 2015, Avago by itself was ranked 13th in R&D spending that year (at nearly $1.1 billion).

Memory IC leader Samsung was ranked fourth in R&D spending in 2016 with expenditures increasing 11% from 2015. Among the $1 billion-plus “R&D club,” the South Korean company had the lowest investment-intensity level with 6.5% of its total semiconductor revenues going to chip-related research and development in 2016, which was up from just 6.2% in 2015.

Toshiba in Japan moved up two positions to fifth as it aimed its R&D spending at 3D NAND flash memories.  Foundry giant Taiwan Semiconductor Manufacturing Co. (TSMC) was sixth with a 7% increase in 2016 R&D spending, followed by fabless IC supplier MediaTek in Taiwan, which moved up one position to seventh with 13% growth in R&D expenditures. U.S.-based memory supplier Micron Technology advanced from ninth to eighth in the ranking with its research and development spending rising 5% in 2016.

Rounding out the top 10, NXP in Europe was ninth in 2016, slipping from sixth in 2015 and SK Hynix grew its R&D spending 9% to complete the list.   Fabless Nvidia just missed the cut with a 10% increase in expenditures for research and development.

Semiconductor consolidation played a factor in industry R&D spending rising just 1% in 2016 to a record-high $56.5 billion after a 1% increase in 2015 to $56.2 billion.  The slowdown in industry-wide R&D spending growth also corresponded with weakness in worldwide semiconductor sales, which declined 1% in 2015 and then recovered with a low single-digit increase in 2016.

A new spin on electronics


February 15, 2017

Modern computer technology is based on the transport of electric charge in semiconductors. But this technology’s potential will be reaching its limits in the near future, since the components deployed cannot be miniaturized further. But, there is another option: using an electron’s spin, instead of its charge, to transmit information. A team of scientists from Munich and Kyoto is now demonstrating how this works.

The extremely thin, electrically conducting layer between the materials lanthanum-aluminate (LaAlO2) and strontium-titanate (SrTiO3) transports spin-information from the point of injection to a detector. Credit: Christoph Hohmann / Nanosystems Initiative Munich

The extremely thin, electrically conducting layer between the materials lanthanum-aluminate (LaAlO2) and strontium-titanate (SrTiO3) transports spin-information from the point of injection to a detector. Credit: Christoph Hohmann / Nanosystems Initiative Munich

Computers and mobile devices continue providing ever more functionality. The basis for this surge in performance has been progressively extended miniaturization. However, there are fundamental limits to the degree of miniaturization possible, meaning that arbitrary size reductions will not be possible with semiconductor technology.

Researchers around the world are thus working on alternatives. A particularly promising approach involves so-called spin electronics. This takes advantage of the fact that electrons possess, in addition to charge, angular momentum – the spin. The experts hope to use this property to increase the information density and at the same time the functionality of future electronics.

Together with colleagues at the Kyoto University in Japan scientists at the Walther-Meißner-Institute (WMI) and the Technical University of Munich (TUM) in Garching have now demonstrated the transport of spin information at room temperature in a remarkable material system.

A unique boundary layer

In their experiment, they demonstrated the production, transport and detection of electronic spins in the boundary layer between the materials lanthanum-aluminate (LaAlO2) and strontium-titanate (SrTiO3). What makes this material system unique is that an extremely thin, electrically conducting layer forms at the interface between the two non-conducting materials: a so-called two-dimensional electron gas.

The German-Japanese team has now shown that this two-dimensional electron gas transports not only charge, but also spin. “To achieve this we first had to surmount several technical hurdles,” says Dr Hans Hübl, scientist at the Chair for Technical Physics at TUM and Deputy Director of the Walther-Meißner-Institute. “The two key questions were: How can spin be transferred to the two-dimensional electron gas and how can the transport be proven?”

Information transport via spin

The scientists solved the problem of spin transfer using a magnetic contact. Microwave radiation forces its electrons into a precession movement, analogous to the wobbling motion of a top. Just as in a top, this motion does not last forever, but rather, weakens in time – in this case by imparting its spin onto the two-dimensional electron gas.

The electron gas then transports the spin information to a non-magnetic contact located one micrometer next to the contact. The non-magnetic contact detects the spin transport by absorbing the spin, building up an electric potential in the process. Measuring this potential allowed the researchers to systematically investigate the transport of spin and demonstrate the feasibility of bridging distances up to one hundred times larger than the distance of today’s transistors.

Based on these results, the team of scientists is now researching to what extent spin electronic components with novel functionality can be implemented using this system of materials.

Engineering researchers at Michigan State University have developed the first stretchable integrated circuit that is made entirely using an inkjet printer, raising the possibility of inexpensive mass production of smart fabric.

Imagine: an ultrathin smart tablet that can be stretched easily from mini-size to extra large. Or a rubber band-like wrist monitor that measures one’s heartbeat. Or wallpaper that turns an entire wall into an electronic display.

Chuan Wang, a Michigan State University engineering researcher, displays the stretchable electronic material he and colleagues developed in his lab. Credit: Michigan State University

Chuan Wang, a Michigan State University engineering researcher, displays the stretchable electronic material he and colleagues developed in his lab. Credit: Michigan State University

These are some of the potential applications of the stretchable smart fabric developed in the lab of Chuan Wang, assistant professor of electrical and computer engineering. And because the material can be produced on a standard printer, it has a major potential cost advantage over current technologies that are expensive to manufacture.

“We can conceivably make the costs of producing flexible electronics comparable to the costs of printing newspapers,” said Wang. “Our work could soon lead to printed displays that can easily be stretched to larger sizes, as well as wearable electronics and soft robotics applications.”

The smart fabric is made up of several materials fabricated from nanomaterials and organic compounds. These compounds are dissolved in solution to produce different electronic inks, which are run through the printer to make the devices.

From the ink, Wang and his team have successfully created the elastic material, the circuit and the organic light-emitting diode, or OLED. The next step is combining the circuit and OLED into a single pixel, which Wang estimates will take one to two years. There are generally millions of pixels just underneath the screen of a smart tablet or a large display.

Once the researchers successfully combine the circuit and OLED into a working pixel, the smart fabric can be potentially commercialized.

Conceivably, Wang said, the stretchable electronic fabric can be folded and put in one’s pocket without breaking. This is an advantage over current “flexible” electronics material technology that cannot be folded.

“We have created a new technology that is not yet available,” Wang said. “And we have taken it one big step beyond the flexible screens that are about to become commercially available.”

Vertical-cavity surface-emitting lasers (VCSELs) are small, semiconductor-based lasers that emit optical beams from their top surface, and one of their main applications is in gas sensing. Gases each have a unique set of energies they can absorb, derived from their molecular structure. These sets of absorption lines are akin to fingerprints, which enables unambiguous and sensitive detection with a suitable tunable laser like a tunable VCSEL.

There are several important gases that are detectable with mid-infrared (mid-IR) light, having wavelengths between 3 and 4 micrometers (microns), including methane, carbon dioxide and nitrogen dioxide. Application-grade VCSELs, however, aren’t yet available for this wavelength range, but the increasing need for compact, portable and affordable gas sensors is spurring demand for energy-efficient semiconductor sources of mid-IR light.

Addressing this demand, a group of researchers from the Walter Schottky Institute at the Technical University of Munich (TUM) in Germany set out to develop a concept to extend the wavelength coverage of VCSELs into this important regime, which they report this week in Applied Physics Letters, from AIP Publishing.

Typical VCSELs suffer in performance for the relatively long wavelengths of the mid-IR range, in part due to side effects of heating that disproportionally affect IR wavelengths. These effects are minimized by the “buried tunnel junction” configuration of VCSELs, where a material barrier is embedded between the standard p- and n-type materials of the semiconductor. This structuring results in resistancelike behavior for the device and provides tunability of the optical properties in the desired range.

“The buried tunnel junction VCSEL concept has already yielded high-performance VCSELs within the entire 1.3- to 3-micron wavelength range,” said Ganpath K. Veerabathran, a doctoral student at the Walter Schottky Institute. “And so-called type-II ‘W’ quantum well active regions have been used successfully to make conventional edge-emitting semiconductor lasers with excellent performance within the 3- to 6-micron wavelength range.”

By combining the tunnel junction VCSEL concept with these conventional edge-emitting laser designs, where the beam is emitted in parallel with the bottom surface, in this wavelength regime, the researchers created a buried tunnel junction VCSEL with a single-stage, type-II material active region to extend the wavelength coverage of electrically pumped VCSELs.

This advance is particularly noteworthy because it’s the first known demonstration of electrically pumped, single-mode, tunable VCSELs emitting continuous wave up to 4 microns.

“It marks a significant step from state-of-the-art devices emitting at three microns in a continuous wave, and up to 3.4 microns in pulsed mode, respectively,” said Veerabathran. “Further, our demonstration at four microns paves the way for application-grade VCSELs within the entire 3- to 4-micron wavelength range, because the performance of these VCSELs generally improves at shorter wavelengths.”

It’s important to note that although gas-sensing systems within this wavelength range are already available using other types of lasers, they’re considered to be power hogs compared to VCSELs. They also tend to be cost-prohibitive, and are mainly used by industries to detect trace gases for safety and monitoring applications.

“The 4-micron VCSEL demonstrates that low-power, battery-operated, portable and inexpensive sensing systems are within reach,” Veerabathran also said. “Once sensing systems become more affordable, there’s great potential for deployment by industries, such as the auto industry for emission monitoring and control, and these systems may even find uses within our homes.”

Next, the group will focus on making improvements “in terms of the maximum operation temperature and optical output power of the VCSELs,” Veerabathran said. “In the future, it may be possible to extend this concept to make VCSELs emit further into the mid-infrared region beyond 4 microns. This would be beneficial because the absorption strength of gases typically becomes orders of magnitude stronger, even for relatively small wavelength increases.”

Semtech Corporation (Nasdaq:SMTC), a supplier of analog and mixed-signal semiconductors, today announced the latest family of load switches in its FemtoSwitch product platform. The new, ultra-low RDS(on) load switches are ideal for 5V, 15W USB Power Delivery (USB-PD) type-C port controller applications and other power rail switching applications, such as battery-powered portable electronics.

This product family extends Semtech’s FemtoSwitch platform of high-performance analog load switch ICs. It features slow, soft start when the switch is turned-on to limit the in-rush current. Its output pin provides an auto-discharge function for H-version products, and it is protected from overload faults with a 3A current-limit, as well as from over-temperature with a shutdown circuit.

“This expansion to our FemtoSwitch load switch platform enhances Semtech’s high performance, low power product portfolio,” said Francois Ricodeau, Product Line Manager for Semtech’s Power and High-Reliability Products Group. “By providing ultra-low RDS(on) load switches geared toward USB-PD type-C port controller applications, we are able to meet the demands of the fast-growing portable electronics market.”

Worldwide semiconductor wafer foundry leader GLOBALFOUNDRIES published its global manufacturing business expansion plan today. The company will continue investing in its wafer plants in the United States and Germany, expand its capacity in Singapore, and construct a facility to produce 12–inch wafers in Chengdu, China in order to satisfy Chinese and global demands for the company’s 22FDX technology.

According to the cooperation plan of the two parties, the Chengdu plant will start production in Q4 of 2018, with fabrication of the advanced 22FDX to begin in Q4 of 2019.

CEO of GLOBALFOUNDRIES, Sanjay Jha, indicated that, “From the world-class RF-SOI platform used for wireless Internet devices, to the technical roadmaps of the state-of-the-art FD-SOI and FinFET, they all serve as evidence of the market’s tremendous demands for our main staple and progressive technologies. The construction of the 12–inch wafer plant in the High and New Technology Development Area of Chengdu will be conducive to accelerating our expansion in the Chinese market.”

The High and New Technology Development Area of Chengdu is home to one of China’s most prominent IT industry clusters, hosting a plethora of global IT giants including Intel, Texas Instrument, AMD, MediaTek, Dell, Lenovo and Foxconn, as well as 115 of the Fortune Global 500 companies. In 2016, the High and New Technology Development Area posted total trade amounting to USD 24.9 billion.

On the same day, GLOBALFOUNDRIES also unveiled its brand new trade name for the Chinese market: “Ge Xin“, and announced the establishment of a new joint venture — Gexin (Chengdu) Integrated Circuit Manufacturing Co., Ltd. In Chinese, the name “Ge Xin” shares the same pronunciation as the Chinese word for “innovation” and signifies rebirth, reinvigoration and reform.

Applied Materials, Inc. announced today that Dr. Om Nalamasu, Senior Vice President and Chief Technology Officer, has been elected to the U.S. National Academy of Engineering (NAE), one of the highest professional honors for engineers. Dr. Nalamasu received the distinction for technical innovation spanning materials development, atomically controlled thin-film fabrication, and commercialization in microelectronics and energy generation and storage.

“Om has a passion for inspiring innovation and developing engineering talent,” said Gary Dickerson, President and CEO of Applied Materials. “This well-deserved recognition honors the many contributions Om has made throughout his career to pursue technical breakthroughs and advance the technology that is now part of our everyday lives.”

Dr. Nalamasu is a world-renowned expert in materials science and has made seminal contributions to the fields of optical lithography and polymeric materials science and technology. As a champion for a global innovation culture, he has built a world-class team to support Applied’s leadership in materials engineering, and solidified strategic relationships with universities, government organizations and research institutes around the world. He also serves as president of Applied Ventures, LLC, the venture capital fund of Applied Materials, where he oversees investments in early- and growth-stage companies. Prior to joining Applied in 2006, Om was a NYSTAR Distinguished Professor of materials science and engineering at Rensselaer Polytechnic Institute, where he also served as Vice President of Research. Before that he served in several leadership roles at Bell Laboratories.

“It is a tremendous honor to join such a distinguished community of engineers and technologists,” said Dr. Nalamasu. “There has never been a more exciting time to be an engineer and develop innovative solutions that help solve the world’s toughest challenges.”

Dr. Nalamasu has received numerous awards, authored more than 180 papers, review articles and books, and holds more than 200 worldwide issued or pending patent applications. He is a member of the board of directors of The Tech Museum in Silicon Valley and serves on several national and international advisory boards. Born in Hyderabad, Telangana, India, he earned a B.Sc. from Osmania University, a M.Sc. from the University of Hyderabad and received his Ph.D. from the University of British Columbia, Vancouver, Canada.

Founded in 1964, the NAE strives to advance the well-being of the nation by promoting a vibrant engineering profession and by marshalling the expertise and insights of eminent engineers to provide independent advice to the federal government on matters involving engineering and technology.

GLOBALFOUNDRIES yesterday announced plans to expand its global manufacturing footprint in response to growing customer demand for its comprehensive and differentiated technology portfolio. The company is investing in its existing leading-edge fabs in the United States and Germany, expanding its footprint in China with a fab in Chengdu, and adding capacity for mainstream technologies in Singapore.

“We continue to invest in capacity and technology to meet the needs of our worldwide customer base,” said GF CEO Sanjay Jha. “We are seeing strong demand for both our mainstream and advanced technologies, from our world-class RF-SOI platform for connected devices to our FD-SOI and FinFET roadmap at the leading edge. These new investments will allow us to expand our existing fabs while growing our presence in China through a partnership in Chengdu.”

In the United States, GF plans to expand 14nm FinFET capacity by an additional 20 percent at its Fab 8 facility in New York, with the new production capabilities to come online in the beginning of 2018. This expansion builds on the approximately $13 billion invested in the United States over the last eight years, with an associated 9,000 direct jobs across four locations and 15,000 jobs within the regional ecosystem. New York will continue to be the center of leading-edge technology development for 7nm and extreme ultraviolet (EUV) lithography, with 7nm production planned for Q2 2018.

In Germany, GF plans to build up 22FDX 22nm FD-SOI capacity at is Fab 1 facility in Dresden to meet demand for the Internet of Things (IoT), smartphone processors, automotive electronics, and other battery-powered wirelessly connected applications, growing the overall fab capacity by 40 percent by 2020. Dresden will continue to be the center for FDX technology development. GF engineers in Dresden are already developing the company’s next-generation 12FDX technology, with customer product tape-outs expected to begin in the middle of 2018.

In China, GF and the Chengdu municipality have formed a partnership to build a fab in Chengdu. The partners plan to establish a 300mm fab to support the growth of the Chinese semiconductor market and to meet accelerating global customer demand for 22FDX. The fab will begin production of mainstream process technologies in 2018 and then focus on manufacturing GF’s commercially available 22FDX process technology, with volume production expected to start in 2019.

In Singapore, GF will increase 40nm capacity at its 300mm fab by 35 percent, while also enabling more 180nm production on its 200mm manufacturing lines. The company will also add new capabilities to produce its industry-leading RF-SOI technology.

“GF has had a strong foundry relationship with Qualcomm Technologies for many years across a wide range of process nodes,” said Roawen Chen, senior vice president, QCT global operations, Qualcomm Technologies, Inc. “We are excited to see GF making these new investments in differentiated technology and expanding global capacity to support Qualcomm Technologies in delivering the next wave of innovation across a range of integrated circuits that support our business.”

“Collaborative foundry partnerships are critical for us to differentiate ourselves in the competitive market for mobile SoCs,” said Min Li, chief executive officer of Rockchip. “We are pleased to see GF bringing its innovative 22FDX technology to China and investing in the capacity necessary to support the country’s growing fabless semiconductor industry.”

“As our customers increasingly demand more from their mobile experiences, the need for a strong manufacturing partner is greater than ever,” said Joe Chen, co-chief operating officer of MediaTek. “We are thrilled to have a partner like GF that invests in the global capacity we need to deliver powerful and efficient mobile technologies for markets ranging from networking and connectivity to the Internet of Things.”

Researchers in Singapore and China have collaborated to develop a self-powered photodetector that can be used in a wide range of applications such as chemical analysis, communications, astronomical investigations and much more.

Typically, photodetectors require an external voltage to provide the driving force for separating and measuring photo-generated electrons that comprise the detection. To eliminate this need, the research team led by Junling Wang and Le Wang at Nanyang Technological University in Singapore developed a novel, sensitive and stable photodetector based on a semiconducting junction called a GdNiO3/Nb-doped SrTiO3 (GNO/NSTO) p-n heterojunction. An inherent electric field at the GNO/NSTO interface provides the driving force for efficient separation of photo-generated carriers, eliminating the need for an external power source.

In addition to its self-powered feature, Wang and his team report tuning the material properties to achieve broad sensitivity. For these compounds, most research work thus far has focused on studying the origin of metal-insulator transition, but this team took a different approach.

The properties of perovskite nickelates, the category of solar cell materials in which this structure falls, are very sensitive to oxygen content. This sensitivity enables fine tuning of the final electronic structures by varying the oxygen environment during film deposition (constructing the heterojunction).

“Our work is novel and confirms that nickelates films have tunable band gaps with changing of the oxygen vacancy concentration, which makes them ideal as light absorbing materials in optoelectronic devices,” said Wang. “Using the self-powered photodetector we designed, we study its photo responsivity using light sources with different wavelengths, with significant photo-response appearing when the light wavelength decreases to 650 nanometers.” Wang said.

A significant challenge in developing this photodetector was determining the correct band structure, or energy structure available to electrons, of the 10 nanometer thick GNO films.

“To obtain the band structures, we used both spectroscopic ellipsometry measurements and ultraviolet photoelectron spectroscopy (UPS) measurements,” said Wang. Using the deduced values for the optical bandgap from these measurements, along with known limits and values for GNO films, they could plot the energy levels and work functions of the various components in the devices.

The team hopes to explore more materials with similar features. “One of the remarkable features of nickelates […] is the dependence of their physical properties on the chosen rare earth element,” said Wang. “Thus far, we have only studied GdNiO3 film, but besides that we can also investigate other “R”-NiO3 films where “R” can be Nd (neodymium), Sm (animony), Er (erbium) and Lu (lutetium) and study their potential applications in the photodetector.”

The team also plans to improve the performance of the photodetector by adding an insulating SrTiO3 (STO) layer sandwiched between the GdNiO3 film and NSTO substrate.

This novel work has great potential for applications using optoelectronic devices. “We believe that this paper will stimulate further studies and enlarge the potential applications of systems based on nickelates,” said Wang.