Category Archives: Device Architecture

At this week’s IEEE IEDM conference, imec, the research and innovation hub in nano-electronics and digital technologies showed for the first time a silicon (Si)-passivated germanium (Ge) nMOS gate stack with dramatically reduced interface defect density (DIT) reaching the same level as a Si gate stack and with high mobility and reduced positive bias temperature instability (PBTI). These promising results pave the way to Ge-based finFETs and gate all-around devices, as promising options for 5nm and beyond logic devices.

Today’s results were achieved by band engineering using an interface dipole at high-k/SiO2 interface, and a H2 high-pressure anneal (HPA) finalizing the process flow. The interface dipole was formed on SiO2 layer by depositing a Lanthanum (La)SiO layer by atomic layer deposition (ALD), which is a 3D-compatible process. While a high DIT has been the leading concern for Si-passivated Ge nFET, it was dramatically reduced, for the first time, from 2×1012 cm-2eV-1 down to 5×1010 cm-2eV-1 around midgap using a combination of the LaSiO insertion and a H2 HPA. Consequently, electron mobility was increased (approximately 50 percent at peak) while PBTI reliability was improved thanks to the interface dipole-induced band engineering.

At IEEE IEDM, imec also presents a model for heterostructure interface resistivity (Rhi) analysis for highly doped semiconductors. Using this novel model, imec predicted that high-doping Si:P in a TiSix/Si:P/n-Ge contact stack helps to overcome the high contact resistance problem in Ge nMOS. With development of an advanced low-temperature Si:P epitaxy technique, imec demonstrated a TiSix/Si:P/n-Ge contact stack with record-low contact resistivity for n-Ge.

“Dedicated to push the boundaries of Moore’s Law, Ge-based devices are a key focus area or our research,” stated An Steegen, Executive Vice President Semiconductor Technology and Systems. “These breakthrough achievements underscore our dedication to understanding the fundamental roadblocks that need to be overcome in order for Ge-based devices to become a viable solution for 5nm and beyond.”

This work was performed in collaboration with ASM, Poongsan and Nanyang Technological University. Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony and TSMC.

Vigorous M&A activity in 2015 and 2016 has reshaped the landscape of the semiconductor industry, with the top companies now controlling a much greater percentage of marketshare.  Not including foundries, IC Insights forecasts to top five semiconductor suppliers—Intel, Samsung, Qualcomm, Broadcom, and SK Hynix— will account for 41% marketshare in 2016 (Figure 1).  This represents a nine-point increase from the 32% marketshare held by the top five suppliers ten years ago. Furthermore, the top 10 semiconductor suppliers are forecast to account for 56% marketshare in 2016, an 11-point swing from 45% in 2006, and the top 25 companies are forecast to account for more than three-quarters of all semiconductor sales this year.

semiconductor sales leaders

Figure 1

Following an historic surge in semiconductor merger and acquisition agreements in 2015, the torrid pace of transactions eased a bit in the first half of 2016.  However, 2016 is now forecast to be the second-largest year ever for chip industry M&A announcements, thanks to three major deals struck in 3Q16 that have a combined total value of $51.0 billion.  These deals were SoftBank’s purchase of ARM, Analog Devices’ intended purchase of Linear Technology, and Renesas’ potential acquisition of Intersil. With the surge in mergers and acquisitions expected to continue over the next few years, IC Insights believes that the consolidation will raise the shares of the top suppliers to even loftier levels.

Leti researchers have demonstrated that memristive devices are excellent candidates to emulate synaptic plasticity, the capability of synapses to enhance or diminish their connectivity between neurons, which is widely believed to be the cellular basis for learning and memory.

The breakthrough was presented today at IEDM 2016 in San Francisco in the paper, “Experimental Demonstration of Short and Long Term Synaptic Plasticity Using OxRAM Multi k-bit Arrays for Reliable Detection in Highly Noisy Input Data”.

Neural systems such as the human brain exhibit various types and time periods of plasticity, e.g. synaptic modifications can last anywhere from seconds to days or months. However, prior research in utilizing synaptic plasticity using memristive devices relied primarily on simplified rules for plasticity and learning.

The project team, which includes researchers from Leti’s sister institute at CEA Tech, List, along with INSERM and Clinatec, proposed an architecture that implements both short- and long-term plasticity (STP and LTP) using RRAM devices.

“While implementing a learning rule for permanent modifications – LTP, based on spike-timing-dependent plasticity – we also incorporated the possibility of short-term modifications with STP, based on the Tsodyks/Markram model,” said Elisa Vianello, Leti non-volatile memories and cognitive computing specialist/research engineer.  “We showed the benefits of utilizing both kinds of plasticity with visual pattern extraction and decoding of neural signals. LTP allows our artificial neural networks to learn patterns, and STP makes the learning process very robust against environmental noise.”

Resistive random-access memory (RRAM) devices coupled with a spike-coding scheme are key to implementing unsupervised learning with minimal hardware footprint and low power consumption. Embedding neuromorphic learning into low-power devices could enable design of autonomous systems, such as a brain-machine interface that makes decisions based on real-time, on-line processing of in-vivo recorded biological signals. Biological data are intrinsically highly noisy and the proposed combined LTP and STP learning rule is a powerful technique to improve the detection/recognition rate. This approach may enable the design of autonomous implantable devices for rehabilitation purposes.

Leti, which has worked on RRAM to develop hardware neuromorphic architectures since 2010, is the coordinator of the H2020 European project NeuRAM3. That project is working on fabricating a chip with architecture that supports state-of-the-art machine-learning algorithms and spike-based learning mechanisms.

Leti will present 13 papers at the conference, three of which are invited.

Scientists often discover interesting things without completely understanding how they work. That has been the case with an experimental memory technology in which temperature and voltage work together to create the conditions for data storage. But precisely how was unknown.

But when a Stanford team found a way to untangle the chip’s energy and heat requirements, their tentative findings revealed a pleasant surprise: The process may be more energy efficient than was previously supposed. That’s good news for next-generation mobile devices whose batteries would last longer if they were powering lower energy chips.

The group that made this discovery, led by Stanford electrical engineer H.-S. Philip Wong, is presenting the paper when the IEEE International Electron Devices Meeting (IEDM) brings leading researchers to San Francisco Dec. 5.

The new technology the team investigated is called resistive random-access memory, or RRAM for short. RRAM is based on a new type of semiconductor material that forms digital zeros and ones by resisting or permitting the flow of electrons. RRAM has the potential to do things that aren’t possible with silicon: for instance, being layered on top of computer transistors in new three-dimensional, high-rise chips that would be faster and more energy efficient than current electronics, which is ideal for smartphones and other mobile devices where energy efficiency is a vital feature.

But while engineers can observe that RRAM does store data, they don’t know exactly how these new materials work. “We need much more precise information about the fundamental behavior of RRAM before we can hope to produce reliable devices,” Wong said.

Jolting memory

So to help engineers understand some of the unknowns, Wong’s team built a tool to measure the basic forces that make RRAM chips work.

Graduate student Zizhen Jiang of the Stanford team explained the basics: RRAM materials are insulators, which normally do not allow electricity to flow, she said. But under certain circumstances, insulators can be induced to let electrons flow. Past research had shown how: Jolting RRAM materials with an electric field causes a pathway to form that permitted electron flows. This pathway is called a filament. To break the filament, researchers apply another jolt and the material becomes an insulator again. So each jolt switched the RRAM from zero to one or back, which is what makes the material useful for data storage.

But electricity is not the only force at play in RRAM switching. Pumping electrons into any material raises its temperature. That’s the principle behind electric stoves. In the case of RRAM, it was the elevated temperature caused by introducing voltage that induced filaments to form or break. The question was what voltage-induced temperature was needed to cause the switching. No one knew.

Before the new Stanford study researchers thought short bursts of voltage, sufficient to generate temperatures of about 1,160 degrees Fahrenheit – hot enough to melt aluminum – was the switching point. But those were estimates because there was no way to measure the heat generated by an electric jolt.

“In order to begin to answer our questions, we had to decouple the effects of voltage and temperature on filament formation,” said Ziwen Wang, another graduate student on the team.

Dissecting the heat needs

Essentially, the Stanford researchers had to heat the RRAM material without using an electric field. So they put an RRAM chip on a micro thermal stage (MTS) device – a sophisticated hot plate capable of generating a wide range of temperatures inside the material. Of course the objective was not merely to heat the material, but also to measure how filaments formed. Here they took advantage of the fact that RRAM materials are insulators in their natural state. That makes them digital zeros. As soon as a filament formed electrons would flow. The digital zero would become a digital one, which the researchers could detect.

Using this experimental model, the team put RRAM chips on the burner and cranked up the heat, starting at about 80 F – roughly the temperature of a warm room – all the way up to 1,520 F, hot enough to melt a silver coin. Heating the RRAM to various temperatures in between these extremes, the researchers measured precisely if and how RRAM switched from its native zero to a digital one.

To their pleasant surprise, the researchers observed that filaments could form more efficiently at ambient temperatures between 80 F and 260 F, which is hotter than boiling water – contrary to prior expectation that hotter was better.

If confirmed by subsequent research, this would be good news because in a working chip the switching temperature would be created by the voltage and duration of the electric jolt. Efficient switching at lower temperatures would require less electricity and make RRAM more energy efficient and extend battery life when used as the memory in mobile devices.

Much work remains to be done to make RRAM memory practical but this research provides the test bed to vary conditions systematically instead of relying on hit-and-miss hunches.

“Now we can use voltage and temperature as design inputs in a predictive manner and that is going to enable us to design a better memory device,” Wang said.

Henry Chen, a Stanford alumnus who earned his PhD in Wang’s lab, gave this research a big assist and was a co-author on the paper. Chen, now with the Chinese memory chip-manufacturing firm GigaDevices Semiconductor Inc., helped develop the concepts and instruments that enabled the researchers to make the measurements being reported at IEDM.

Leti, an institute of CEA Tech, presented two papers at IEDM 2016 today that demonstrate its ability to provide industry with all the elements required for building a competitive 5nm node with nanowire architectures.

Nanowire architectures are seen as the best candidates for that node, and Leti is addressing some of its biggest challenges, such as of performance and parasitic capacitances. Its results suggest that strain can be introduced into stacked nanowire and that parasitic capacitances can be reduced thanks to inner spacer integration.

The paper, “Vertically Stacked-Nanowires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain”, is the first demonstration of functional devices with SiGe source and drain to induce strain in the channel to boost performance, and inner spacer to reduce parasitic capacitances. Both building blocks are required for the 5-nm node. This MOSFET architecture extends the scaling limits of CMOS technology, and is also seen as a possible extension to FinFET.

Leti, at IEDM 2008, was among the world’s first organizations to report stacked nanowire and nanosheet results.

The second paper, “NSP: Physical Compact Model for Stacked-planar and Vertical Gate-All-Around MOSFETs”, presents a predictive and physical compact model for nanowire and nanosheet gate-all-around MOSFETs.

“This is the first compact model, or SPICE model, that can simulate stacked nanowire and nanosheet devices with various geometries,” said Olivier Faynot, Leti’s microelectronics section manager and a co-author of both papers. “It also enables the simulation of vertical nanowire, which is one of the key achievements of this model.”

The paper presents a physically based SPICE model for stacked nanowires that can enable circuit designers to accurately project their existing circuits into the 5-nm node, and investigate novel designs.

SEMI, the global industry association representing more than 2,000 companies in the electronics manufacturing supply chain, today reported that worldwide semiconductor manufacturing equipment billings reached US$11.0 billion in the third quarter of 2016. The billings figure is 5 percent higher than the second quarter of 2016 and 14 percent higher than the same quarter a year ago. The data is gathered jointly with the Semiconductor Equipment Association of Japan (SEAJ) from over 95 global equipment companies that provide data on a monthly basis.

Worldwide semiconductor equipment bookings were $11.3 billion in the third quarter of 2016. The figure is 30 percent higher than the same quarter a year ago and 5 percent lower than the bookings figure for the second quarter of 2016.

The quarterly billings data by region in billions of U.S. dollars, quarter-over-quarter growth and year-over-year rates by region are as follows:

 

3Q2016

2Q2016

 3Q2015

3Q2016/

2Q2016
(Qtr-over-Qtr)

3Q2016/

3Q2015
(Year-over-Year)
Taiwan

3.46

2.73

2.85

27%

22%
Korea

2.09

1.53

1.56

36%

34%
China

1.43

2.27

1.70

-37%

-16%
Japan

1.29

1.05

1.43

22%

-10%
Rest of World

1.13

1.31

0.58

-14%

95%
North America

1.05

1.20

1.18

-12%

-11%
Europe

0.53

0.37

0.34

42%

57%
Total

10.98

10.46

9.64

5%

14%

Totals may not add due to rounding; Source: SEMI/SEAJ

Leti CEO Marie Semeria today delivered a sweeping, optimistic assessment of a rapidly evolving world where “hyperconnectivity” and the Internet of Things – guided by a “human-centered research approach and symbiotic development strategies” – herald profound changes in the way individuals relate to each other and to the physical world.

Her keynote presentation during the opening session of IEDM 2016, one of the high-tech industry’s most prestigious annual events, was based on her invited paper, “Symbiotic Low-Power, Smart and Secure Technologies in the Age of Hyperconnectivity”.

Marie Semeria, Leti CEO

Marie Semeria, Leti CEO

Semeria presented a comprehensive view of ubiquitous connectivity’s vast potential to bring positive change for individuals, society, companies and governments. She envisions a world in which a human-centered research approach combined with symbiotic development strategies “along different technological axes will foster key innovations that address societal challenges with strong impact.”

IoT at ‘Epicenter of the Revolution’

“The vertiginous pace of technological progress has made civilization enter the age of hyperconnectivity, dramatically changing the way people live, interact, share information, work, travel, take care of their health (and) purchase goods,” she notes. “Enabled by the convergence of miniaturization, wireless connectivity, increased data-storage capacity and data analytics, the Internet of Things (IoT) has become the epicenter of a profound social, business and political revolution.”

The IoT, with billions of easy-access and low-cost connected devices, “has transformed the world into a truly global village, enabling people and machines to interact in a symbiotic way – anytime, anywhere – with both the physical and cyber worlds,” she notes. “A new economy has emerged, as new product-as-a-service business models have been enabled by smart, connected products, creating substitutes for product ownership.”

In R&D strategies where technologies are developed symbiotically, the technologies’ associated innovation potential strongly increases. “Leti masters hardware and software technologies that gather, filter, process, store, transfer and analyze information in an efficient way. What is crucial today is not to consider these technologies as independent from one another,” Semeria says.

In her paper, Semeria also addresses the many global challenges that predate the hyperconnectivity era, such as climate change, poverty, diminishing natural resources and pollution, and the major challenges that rapid technological advancements have enabled. These include the negative side effects of cyber-technologies, ranging from “digital addiction” of some young people to cyber attacks on systems and threats to personal data and privacy.

Security Is a Crucial Component

“The hyperconnected society presents challenges which will require collective learning and adaptation, by both the main actors and the users, to develop the literacy and regulatory frameworks that will recreate and sustain the right balance between accountability and freedom for all agents, people and corporations,” Semeria says.

“Hypersecurity is a crucial component needed to counteract the surge in cyber attacks, which affect our modern societies, critically dependent on cyber-infrastructures (banking, communication, business, etc.). Security and unobtrusive surveillance technologies are being developed to provide and maintain peaceful everyday lives.”

Citizen Concerns

Data breaches and unapproved use of private information have raised widespread concerns about privacy. “Information is sometimes exchanged for commercial or national security purposes, leading citizens to perceive a loss of control, freedom and privacy,” Semeria notes. “The hyperconnected society presents challenges which will require collective learning and adaptation, by both the main actors and the users, to develop the literacy and regulatory frameworks that will recreate and sustain the right balance between accountability and freedom for all agents, people and corporations.”

The hyperconnectivity value chain, which includes sensing, communication, computing and storage, energy harvesting, security and services, depends on key building blocks ranging from sensors to communication networks, including 5G, which is expected to provide a full-scale IoT that offers immersive services regardless of geography and time zones. Leti has strategic programs in each of the value chain fields and participates in the core of Europe’s 5G innovation initiatives.

A Major Role for RTOs

Semeria points out that research and technology organizations (RTOs) like Leti are playing a vital role in the twin pursuits of making the IoT and networks both more efficient and more secure. In the 50 years since its founding, Leti has shaped its strategy to tackle the main challenges presented by the evolution of society and the economic and industrial sectors.

RTOs “are ideally positioned to address and harmonize growing individual, private needs and global societal challenges, because they are neither embedded public administration organizations nor industrial corporate labs guided by private interests,” Semeria notes.

Biomimicry’s Natural Role

In addition to partnerships with companies on specific solutions to make them more competitive and its participation in EU research programs with broader strategic impact, Leti pursues multiple lines of inquiry with an eye on technologies for the future. These include bio-mimicry, which aims to adapt for commercial use the sensing efficiencies that insects have developed over billions of years of evolution.

“Bio-inspired ideas, which are currently experiencing an exponential growth, represent an area with very high hopes,” Semeria says.

At the 2016 IEEE International Electron Devices Meeting, in a special poster session on MRAM, world-leading research and innovation hub for nano-electronics and digital technology imec presented a 8nm p-MTJ device with 100 percent tunnel magnetoresistance (TMR) and coercive field as high 1500Oe. This world’s smallest device enables the establishment of a manufacturing process for high-density spin-transfer-torque magnetic random access memory (STT-MRAM) arrays that meet the requirements of the 10nm and beyond logic node for embedded non-volatile memory applications. It also paves the way for high density stand-alone applications.

STT-MRAM has the potential to become the first embedded non-volatile memory technology on advanced logic nodes for advanced applications and is also considered an alternative to conventional dynamic random access memory (DRAM). The core element of an STT-MRAM is a magnetic tunnel junction (MTJ) in which a thin dielectric layer is sandwiched between a magnetic reference layer and a magnetic free layer, where writing of the memory cell is performed by switching the magnetization of the free layer. STT-MRAMs exhibit non-volatility, high-speed, low-voltage switching and nearly unlimited read/write endurance. However, significant challenges towards commercialization remain, primarily in scaling the processes for higher densities and in increasing the device switching current.

In addressing these challenges, imec scientists have demonstrated for the first time an electrical functional p-MTJ device as small as 8nm. Despite the small dimensions, the device exhibits a high TMR of 100 percent, a coercivity (Hc) of 1500Oe and a spin torque efficiency -the ratio of the thermal stability and switching current- as high as three. The p-MTJ stack, featuring a free layer and reference layer of CoFeB-based multilayer stacks, was developed on 300mm silicon wafers and the fabrication process is compatible with the thermal budget of standard CMOS back-end-of-line (BEOL) technology.

Moreover, imec integrated arrays of p-MTJ devices into a 1T1MTJ structure to build STT-MRAM Megabit arrays with pitches down to 100nm, proving that the technology meets the dimensional requirements for the 10nm logic node and beyond.

Imec’s research into advanced memory is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Micron, Qualcomm, Sony and TSMC.

QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power programmable sensor processing, display bridge and programmable logic solutions, today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator Partner Program, a collaborative ecosystem that facilitates 22FDX system-on-chip (SoC) design and reduces time-to-market for customers.

“QuickLogic’s partnership with GLOBALFOUNDRIES adds a unique dimension to the FDX program by offering customers ultra-low power embedded FPGA (eFPGA) Intellectual Property, complete software tools and a compiler,” said Brian Faith, president and CEO at QuickLogic Corporation. “This new capability provides users with a high level of design and product flexibility which will help lower costs and allow products to be easily customized to meet various and evolving market requirements.”

“GLOBALFOUNDRIES’ FDXcelerator program is a comprehensive design ecosystem that provides customers with the support and resources they need to get FDX FD-SOI technologies to market as quickly as possible,” said Alain Mutricy, senior vice president of Product Management at GLOBALFOUNDRIES. “Leveraging QuickLogic’s FPGA expertise will provide inherent hardware flexibility for FDX-based SoC designs and gain a critical time-to-market advantage for a broad range of embedded, battery powered and IoT applications.”

The FDXcelerator Partner Program builds upon GLOBALFOUNDRIES’ industry-first FD-SOI roadmap, a lower-cost migration path for designers on advanced nodes that is optimized for low power applications. By participating, FDXcelerator Partners commit to provide specific resources, including EDA tools, IP, silicon platforms, reference designs, design services and packaging and test solutions. The program is based on an open framework which enables members to minimize development time and cost while simultaneously leveraging the inherent power and performance advantages of FDX technology.

Current members of the FDXcelerator Partner Program also include Synopsys, Cadence, INVECAS, VeriSilicon, CEA Leti, Dream Chip, and Encore Semi.

They’re flexible, cheap to produce and simple to make – which is why perovskites are the hottest new material in solar cell design. And now, engineers at Australia’s University of New South Wales in Sydney have smashed the trendy new compound’s world efficiency record.

Dr. Anita Ho-Baillie, a Senior Research Fellow at the Australian Centre for Advanced Photovoltaics at UNSW, with the new perovskite cell. Credit: Rob Largent/UNSW

Dr. Anita Ho-Baillie, a Senior Research Fellow at the Australian Centre for Advanced Photovoltaics at UNSW, with the new perovskite cell. Credit: Rob Largent/UNSW

Speaking at the Asia-Pacific Solar Research Conference in Canberra on Friday 2 December, Anita Ho-Baillie, a Senior Research Fellow at the Australian Centre for Advanced Photovoltaics (ACAP), announced that her team at UNSW has achieved the highest efficiency rating with the largest perovskite solar cells to date.

The 12.1% efficiency rating was for a 16 cm2 perovskite solar cell, the largest single perovskite photovoltaic cell certified with the highest energy conversion efficiency, and was independently confirmed by the international testing centre Newport Corp, in Bozeman, Montana. The new cell is at least 10 times bigger than the current certified high-efficiency perovskite solar cells on record.

Her team has also achieved an 18% efficiency rating on a 1.2 cm2 single perovskite cell, and an 11.5% for a 16 cm2 four-cell perovskite mini-module, both independently certified by Newport.

“This is a very hot area of research, with many teams competing to advance photovoltaic design,” said Ho-Baillie. “Perovskites came out of nowhere in 2009, with an efficiency rating of 3.8%, and have since grown in leaps and bounds. These results place UNSW amongst the best groups in the world producing state-of-the-art high-performance perovskite solar cells. And I think we can get to 24% within a year or so.”

Perovskite is a structured compound, where a hybrid organic-inorganic lead or tin halide-based material acts as the light-harvesting active layer. They are the fastest-advancing solar technology to date, and are attractive because the compound is cheap to produce and simple to manufacture, and can even be sprayed onto surfaces.

“The versatility of solution deposition of perovskite makes it possible to spray-coat, print or paint on solar cells,” said Ho-Baillie. “The diversity of chemical compositions also allows cells be transparent, or made of different colours. Imagine being able to cover every surface of buildings, devices and cars with solar cells.”

Most of the world’s commercial solar cells are made from a refined, highly purified silicon crystal and, like the most efficient commercial silicon cells (known as PERC cells and invented at UNSW), need to be baked above 800°C in multiple high-temperature steps. Perovskites, on the other hand, are made at low temperatures and 200 times thinner than silicon cells.

But although perovskites hold much promise for cost-effective solar energy, they are currently prone to fluctuating temperatures and moisture, making them last only a few months without protection. Along with every other team in the world, Ho-Baillie’s is trying to extend its durability. Thanks to what engineers learned from more than 40 years of work with layered silicon, they’re are confident they can extend this.

Nevertheless, there are many existing applications where even disposable low-cost, high-efficiency solar cells could be attractive, such as use in disaster response, device charging and lighting in electricity-poor regions of the world. Perovskite solar cells also have the highest power to weight ratio amongst viable photovoltaic technologies.

“We will capitalise on the advantages of perovskites and continue to tackle issues important for commercialisation, like scaling to larger areas and improving cell durability,” said Martin Green, Director of the ACAP and Ho-Baillie’s mentor. The project’s goal is to lift perovskite solar cell efficiency to 26%.

The research is part of a collaboration backed by $3.6 million in funding through the Australian Renewable Energy Agency’s (ARENA) ‘solar excellence’ initiative. ARENA’s CEO Ivor Frischknecht said the achievement demonstrated the importance of supporting early stage renewable energy technologies: “In the future, this world-leading R&D could deliver efficiency wins for households and businesses through rooftop solar as well as for big solar projects like those being advanced through ARENA’s investment in large-scale solar.”

To make a perovskite solar cells, engineers grow crystals into a structure known as ‘perovskite’, named after Lev Perovski, the Russian mineralogist who discovered it. They first dissolve a selection of compounds in a liquid to make the ‘ink’, then deposit this on a specialised glass which can conduct electricity. When the ink dries, it leaves behind a thin film that crystallises on top of the glass when mild heat is applied, resulting in a thin layer of perovskite crystals.

The tricky part is growing a thin film of perovskite crystals so the resulting solar cell absorbs a maximum amount of light. Worldwide, engineers are working to create smooth and regular layers of perovskite with large crystal grain sizes in order to increase photovoltaic yields.

Ho-Baillie, who obtained her PhD at UNSW in 2004, is a former chief engineer for Solar Sailor, an Australian company which integrates solar cells into purpose-designed commercial marine ferries which currently ply waterways in Sydney, Shanghai and Hong Kong.