Category Archives: Device Architecture

A team of physicists from ITMO University, MIPT, and The University of Texas at Austin have developed an unconventional nanoantenna that scatters light in a particular direction depending on the intensity of incident radiation. The research findings will help with the development of flexible optical information processing in telecommunication systems.

Fig. 1. An artist's rendering of nonlinear light scattering by a dimer of two silicon particles with a variable radiation pattern. Credit: Image courtesy of the press office of MIPT

Fig. 1. An artist’s rendering of nonlinear light scattering by a dimer of two silicon particles with a variable radiation pattern. Credit: Image courtesy of the press office of MIPT

Photons–the carriers of electromagnetic radiation–have neither mass nor electric charge. This means that light is relatively hard to control, unlike, for example, electrons: their flow in electronic circuits can be controlled by applying a constant electric field. However, such devices as nanoantennas enable a certain degree of control over the propagation of electromagnetic waves.

One area that requires the “advanced” light manipulation is the development of optical computers. In these devices, the information is carried not by electrons, but by photons. Using light instead of charged particles has the potential to greatly improve the speed of transmitting and processing information. To make these computers a reality, we need specific nanoantennas with characteristics that can be manipulated in some way–by applying a constant electric or magnetic field, for instance, or by varying the intensity of incident light.

In the paper published in Laser & Photonics Reviews, the researchers designed a novel nonlinear nanoantenna that can change the direction of light scattering depending on the intensity of the incident wave (Fig. 1). At the heart of the proposed nanoantenna are silicon nanoparticles, which generate electron plasma under harsh laser radiation. The authors previously demonstrated the possibilities of using these nanoparticles for the nonlinear and ultrafast control of light. The researchers then managed to manipulate portions of light radiation scattered forward and backward. Now, by changing the intensity of incident light, they have found a way to turn a scattered light beam in the desired direction.

To rotate the radiation pattern of the nanoantenna, the authors used the mechanism of plasma excitation in silicon. The nanoantenna is a dimer–two silicon nanospheres of unequal diameters. Irradiated with a weak laser beam, this antenna scatters the light sideways due to its asymmetric shape. The diameters of the two nanoparticles are chosen so that one particle is resonant at the wavelength of the laser light. Irradiated with an intense laser pulse, electron plasma is generated in the resonant particle which causes changes in the optical properties of the particle. The other particle remains nonresonant, and the powerful laser field has little effect on it. Generally speaking, by accurately choosing the relative size of both particles in combination with the parameters of the incident beam (duration and intensity), it is possible to make the size of the particles virtually the same, which enables the antenna to bounce the light beam forward.

“Existing optical nanoantennas can control light in a fairly wide range. However, this ability is usually embedded in their geometry and the materials they are made of, so it is not possible to configure these characteristics at any time,” says Denis Baranov, a postgraduate student at MIPT and the lead author of the paper. “The properties of our nanoantenna, however, can be dynamically modified. When we illuminate it with a weak laser impulse, we get one result, but with a strong impulse, the outcome is completely different.”

The scientists performed numerical modeling of the light scattering mechanism. The simulation showed that when the nanoantenna is illuminated with a weak laser beam, the light scatters sideways. However, if the nanoantenna is illuminated with an intense laser impulse, that leads to the generation of electron plasma within the device and the scattering pattern rotates by 20 degrees (red line). This provides an opportunity to deflect weak and strong incident impulses in different directions.

Sergey Makarov, a senior researcher at the Department of Nanophotonics and Metamaterials at ITMO University concludes: “In this study, we focused on the development of a nanoscale optical chip measuring less than 200×200×500 nanometers. This is much less than the wavelength of a photon, which carries the information. The new device will allow us to change the direction of light propagation at a much better rate compared to electronic analogues. Our device will be able to distribute a signal into two optical channels within a very short space of time, which is extremely important for modern telecommunication systems.”

Today, information is transmitted via optical fibers at speeds of up to hundreds of Gbit/s. However, even modern electronic devices process these signals quite slowly: at speeds of only a few Gbit/s for a single element. The proposed nonlinear optical nanoantenna can solve this problem, as it operates at 250 Gbit/s. This paves the way for ultrafast processing of optical information. The nonlinear antenna developed by the researchers provides more opportunities to control light at nanoscale, which is what is required in order to successfully develop photonic computers and other similar devices.

IC Insights will release its November Update to the 2016 McClean Report later this month and will release its 20th anniversary edition of The McClean Report in January of next year.  The November Update includes the latest semiconductor industry capital spending forecast, a detailed forecast of the IC industry by product type through 2020, and a look at the top-25 semiconductor suppliers expected for 2016. The top-20 2016 semiconductor suppliers are covered in this research bulletin.

The forecasted top-20 worldwide semiconductor (IC and O S D—optoelectronic, sensor, and discrete) sales ranking for 2016 is shown in Figure 1.  It includes eight suppliers headquartered in the U.S., three in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore, a relatively broad representation of geographic regions.

The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and five fabless companies. If the three pure-play foundries were excluded from the top-20 ranking, U.S.-based fabless supplier AMD ($4,238 million), China-based fabless supplier HiSilicon ($3,762 million), and Japan-based IDM Sharp ($3,706 million), would have been ranked in the 18th, 19th, and 20th positions, respectively.  In August 2016, China-based contract assembler Foxconn bought a controlling interest (66%) in Sharp for $3.8 billion.

In total, the 17 non-foundry companies in the forecasted top 20-ranking are expected to represent 68% of the total $357.1 billion worldwide semiconductor market this year, up 10 points from the 58% share the top 17 companies held in 2006.

IC Insights includes foundries in the top-20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted.  With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers.  As shown in the listing, the foundries and fabless companies are identified.  In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-20 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

Figure 1

Figure 1

Nine of the top-20 companies are forecast to have sales of at least $10.0 billion this year.  As shown, it is expected to take about $4.5 billion in sales just to make it into the 2016 top-20 semiconductor supplier list. Moreover, if Qualcomm’s purchase of NXP is completed, as is expected in late 2017, the combined annual semiconductor sales of these two companies will likely be over $25 billion going forward. Overall, no new entrants are expected to make it into the top-20 ranking in 2016 as compared to the 2015 ranking.

Intel is forecast to remain firmly in control of the number one spot in the top-20 ranking in 2016.  In fact, it is expected to increase its lead over Samsung’s semiconductor sales from only 24% in 2015 to 29% in 2016.  The biggest upward move in the ranking is forecast to be made by Apple, which is expected to jump up three positions in the 2016 ranking as compared to 2015.  Other companies that are forecast to make noticeable moves up the ranking include MediaTek and Nvidia, with each company expected to improve by two positions.

Apple is an anomaly in the top-20 ranking with regards to major semiconductor suppliers. The company designs and uses its processors only in its own products—there are no sales of the company’s MPUs to other system makers.  IC Insights estimates that Apple’s custom ARM-based SoC processors will have a “sales value” of $6.5 billion in 2016, which will place them in the 14th position in the forecasted top-20 ranking.

In total, the top-20 semiconductor companies’ sales are forecast to increase by 3% this year, which would be two points higher than IC Insights’ current worldwide semiconductor market forecast for 2016. Although, in total, the top-20 2016 semiconductor companies are expected to register a 3% increase, there are five companies that are forecast to display a double-digit 2016 jump in sales (Nvidia, MediaTek, Apple, Toshiba, and TSMC) and four that are expected to register a double-digit decline (SK Hynix, Micron, GlobalFoundries, and NXP).

The fastest growing top-20 company this year is forecast to be U.S.-based Nvidia, which is expected to post a huge 35% year-over-year increase in sales.  The company is riding a surge of demand for its graphics processor devices (GPUs) and Tegra processors with its year-over-year sales in its latest quarter (ended October 30, 2016) up 63% for gaming, 193% for data center, and 61% for automotive applications.

The second-fastest growing top-20 company in 2016 is expected to be Taiwan-based MediaTek, which is forecast to post a strong 29% increase in sales this year.  Although worldwide smartphone unit volume sales are expected to increase by only 4% this year, MediaTek’s application processor shipments to the fast-growing China-based smartphone suppliers (e.g., Oppo and Vivo), are forecast to help drive its stellar 2016 increase.

As expected, given the possible acquisitions and mergers that could/will occur over the next few years (e.g., Qualcomm and NXP), the top-20 ranking is likely to undergo a significant amount of upheaval as the semiconductor industry continues along its path to maturity.

Researchers at the NYU Tandon School of Engineering have pioneered a method for growing an atomic scale electronic material at the highest quality ever reported. In a paper published in Applied Physics Letters, Assistant Professor of Electrical and Computer Engineering Davood Shahrjerdi and doctoral student Abdullah Alharbi detail a technique for synthesizing large sheets of high-performing monolayer tungsten disulfide, a synthetic material with a wide range of electronic and optoelectronic applications.

“We developed a custom reactor for growing this material using a routine technique called chemical vapor deposition. We made some subtle and yet critical changes to improve the design of the reactor and the growth process itself, and we were thrilled to discover that we could produce the highest quality monolayer tungsten disulfide reported in the literature,” said Shahrjerdi. “It’s a critical step toward enabling the kind of research necessary for developing next-generation transistors, wearable electronics, and even flexible biomedical devices.”

The promise of two-dimensional electronic materials has tantalized researchers for more than a decade, since the first such material — graphene — was experimentally discovered. Also called “monolayer” materials, graphene and similar two-dimensional materials are a mere one atom in thickness, several hundred thousand times thinner than a sheet of paper. These materials boast major advantages over silicon — namely unmatched flexibility, strength, and conductivity — but developing practical applications for their use has been challenging.

Graphene (a single layer of carbon) has been explored for electronic switches (transistors), but its lack of an energy band gap poses difficulties for semiconductor applications. “You can’t turn off the graphene transistors,” explained Shahrjerdi. Unlike graphene, tungsten disulfide has a sizeable energy band gap. It also displays exciting new properties: When the number of atomic layers increases, the band gap becomes tunable, and at monolayer thickness it can strongly absorb and emit light, making it ideal for applications in optoelectronics, sensing, and flexible electronics.

Efforts to develop applications for monolayer materials are often plagued by imperfections in the material itself — impurities and structural disorders that can compromise the movement of charge carriers in the semiconductor (carrier mobility). Shahrjerdi and his student succeeded in reducing the structural disorders by omitting the growth promoters and using nitrogen as a carrier gas rather than a more common choice, argon.

Shahrjerdi noted that comprehensive testing of their material revealed the highest values recorded thus far for carrier mobility in monolayer tungsten disulfide. “It’s a very exciting development for those of us doing research in this field,” he said.

The Center for Integrated Nanostructure Physics, within the Institute for Basic Science (IBS) has developed the world’s thinnest photodetector, that is a device that converts light into an electric current. With a thickness of just 1.3 nanometers – 10 times smaller than the current standard silicon diodes — this device could be used in the Internet of Things, smart devices, wearable electronics and photoelectronics. This 2D technology, published on Nature Communications, uses molybdenum disulfide (MoS2) sandwiched in graphene.

Graphene is a fantastic material: It’s conductive, thin (just one-atom thick), transparent and flexible. However, since it does not behave as a semiconductor, its application in the electronics industry is limited. Therefore, in order to increase graphene’s usability, IBS scientists sandwiched a layer of the 2D semiconductor MoS2 between two graphene sheets and put it over a silicon base. They initially thought the resulting device was too thin to generate an electric current but, unexpectedly, it did. “A device with one-layer of MoS2 is too thin to generate a conventional p-n junction, where positive (p) charges and negative (n) charges are separated and can create an internal electric field. However, when we shine light on it, we observed high photocurrent. It was surprising! Since it cannot be a classical p-n junction, we thought to investigate it further,” explains YU Woo Jong, first author of this study.

To understand what they found, the researchers compared devices with one and seven layers of MoS2 and tested how well they behave as a photodetector, that is, how they are able to convert light into an electric current. They found that the device with one-layer MoS2 absorbs less light than the device with seven layers, but it has higher photoresponsitivity. “Usually the photocurrent is proportional to the photoabsorbance, that is, if the device absorbs more light, it should generate more electricity, but in this case, even if the one-layer MoS2 device has smaller absorbance than the seven-layer MoS2, it produces seven times more photocurrent,” describes Yu.

Why is the thinner device working better than the thicker one? The research team proposed a mechanism to explain why this is the case. They recognized that the photocurrent generation could not be explained with classical electromagnetism, but could be with quantum physics. When light hits the device, some electrons from the MoS2 layer jump into an excited state and their flow through the device produces an electric current. However in order to pass the boundary between MoS2 and graphene, the electrons need to overcome an energy barrier (via quantum tunnelling), and this is where the one-layer MoS2 device has an advantage over the thicker one.

The monolayer is thinner and therefore more sensitive to the surrounding environment: The bottom SiO2 layer increases the energy barrier, while the air on top reduces it, thus electrons in the monolayer device have a higher probability to tunnel from the MoS2 layer to the top graphene (GrT). The energy barrier at the GrT/MoS2 junction is lower than the one at the GrB/MoS2, so the excited electrons transfer preferentially to the GrT layer and create an electric current. Conversely, in the multi-layer MoS2 device, the energy barriers between GrT/MoS2 and GrB/MoS2 are symmetric, therefore the electrons have the same probability to go either side and thus reduce the generated current.

Imagine a group of people in a valley surrounded by two mountains. The group wants to get to the other side of the mountains, but without making too much effort. In one case ( the seven-layers MoS2 device), both mountains have the same height so whichever mountain is crossed, the effort will be the same. Therefore half the group crosses one mountain and the other half the second mountain.

In the second case (analogue to the one-layer MoS2 device), one mountain is taller than the other, so the majority of the group decide to cross the smaller mountain. However, because we are considering quantum physics instead of classical electromagnetism, they do not need to climb the mountain until they reach the top (as they would need to do with classical physics), but they can pass through a tunnel. Although electron tunneling and walking a tunnel in a mountain are very different of course, the idea is that electric current is generated by the flow of electrons, and the thinner device can generate more current because more electrons flow towards the same direction.

Actually, when light is absorbed by the device and MoS2 electrons jump into an excited state, they leave the so-called holes behind. Holes behave like positive mobile charges and are essentially positions left empty by electrons that absorbed enough energy to jump to a higher energy status. Another problem of the thicker device is that electrons and holes move too slowly through the junctions between graphene and MoS2, leading to their undesired recombination within the MoS2 layer.

For these reasons, up to 65% of photons absorbed by the thinner device are used to generate a current. Instead, the same measurement (quantum efficiency) is only 7% for the seven-layer MoS2 apparatus.

“This device is transparent, flexible and requires less power than the current 3D silicon semiconductors. If future research is successful, it will accelerate the development of 2D photoelectric devices,” explains the professor.

Engineers at the University of California San Diego have fabricated the first semiconductor-free, optically-controlled microelectronic device. Using metamaterials, engineers were able to build a microscale device that shows a 1,000 percent increase in conductivity when activated by low voltage and a low power laser.

The discovery paves the way for microelectronic devices that are faster and capable of handling more power, and could also lead to more efficient solar panels. The work was published Nov. 4 in Nature Communications.

The capabilities of existing microelectronic devices, such as transistors, are ultimately limited by the properties of their constituent materials, such as their semiconductors, researchers said.

For example, semiconductors can impose limits on a device’s conductivity, or electron flow. Semiconductors have what’s called a band gap, meaning they require a boost of external energy to get electrons to flow through them. And electron velocity is limited, since electrons are constantly colliding with atoms as they flow through the semiconductor.

A team of researchers in the Applied Electromagnetics Group led by electrical engineering professor Dan Sievenpiper at UC San Diego sought to remove these roadblocks to conductivity by replacing semiconductors with free electrons in space. “And we wanted to do this at the microscale,” said Ebrahim Forati, a former postdoctoral researcher in Sievenpiper’s lab and first author of the study.

However, liberating electrons from materials is challenging. It either requires applying high voltages (at least 100 Volts), high power lasers or extremely high temperatures (more than 1,000 degrees Fahrenheit), which aren’t practical in micro- and nanoscale electronic devices.

To address this challenge, Sievenpiper’s team fabricated a microscale device that can release electrons from a material without such extreme requirements. The device consists of an engineered surface, called a metasurface, on top of a silicon wafer, with a layer of silicon dioxide in between. The metasurface consists of an array of gold mushroom-like nanostructures on an array of parallel gold strips.

The gold metasurface is designed such that when a low DC voltage (under 10 Volts) and a low power infrared laser are both applied, the metasurface generates “hot spots”–spots with a high intensity electric field–that provide enough energy to pull electrons out from the metal and liberate them into space.

Tests on the device showed a 1,000 percent change in conductivity. “That means more available electrons for manipulation,” Ebrahim said.

“This certainly won’t replace all semiconductor devices, but it may be the best approach for certain specialty applications, such as very high frequencies or high power devices,” Sievenpiper said.

According to researchers, this particular metasurface was designed as a proof-of-concept. Different metasurfaces will need to be designed and optimized for different types of microelectronic devices.

“Next we need to understand how far these devices can be scaled and the limits of their performance,” Sievenpiper said. The team is also exploring other applications for this technology besides electronics, such as photochemistry, photocatalysis, enabling new kinds of photovoltaic devices or environmental applications.

Researchers at the Fraunhofer Institute for Solar Energy Systems ISE together with the Austrian company EV Group (EVG) have successfully manufactured a silicon-based multi-junction solar cell with two contacts and an efficiency exceeding the theoretical limit of silicon solar cells. For this achievement, the researchers used a “direct wafer bonding” process to transfer a few micrometers of III-V semiconductor material to silicon, a well-known process in the microelectronics industry. After plasma activation, the subcell surfaces are bonded together in vacuum by applying pressure. The atoms on the surface of the III-V subcell form bonds with the silicon atoms, creating a monolithic device. The efficiency achieved by the researchers presents a first-time result for this type of fully integrated silicon-based multi-junction solar cell. The complexity of its inner structure is not evident from its outer appearance: the cell has a simple front and rear contact just as a conventional silicon solar cell and therefore can be integrated into photovoltaic modules in the same manner.

Wafer-bonded III-V / Si multi-junction solar cell with 30.2 percent efficiency ©Fraunhofer ISE/A. Wekkeli

Wafer-bonded III-V / Si multi-junction solar cell with 30.2 percent efficiency ©Fraunhofer ISE/A. Wekkeli

“We are working on methods to surpass the theoretical limits of silicon solar cells,” says Dr. Frank Dimroth, department head at Fraunhofer ISE. “It is our long-standing experience with silicon and III-V technologies that has enabled us to reach this milestone today.” A conversion efficiency of 30.2 percent for the III-V / Si multi-junction solar cell of 4 cm² was measured at Fraunhofer ISE’s calibration laboratory. In comparison, the highest efficiency measured to date for a pure silicon solar cell is 26.3 percent, and the theoretical efficiency limit is 29.4 percent.

The III-V / Si multi-junction solar cell consists of a sequence of subcells stacked on top of each other. So-called “tunnel diodes” internally connect the three subcells made of gallium-indium-phosphide (GaInP), gallium-arsenide (GaAs) and silicon (Si), which span the absorption range of the sun’s spectrum. The GaInP top cell absorbs radiation between 300 and 670 nm. The middle GaAs subcell absorbs radiation between 500 and 890 nm and the bottom Si subcell between 650 and 1180 nm, respectively. The III-V layers are first epitaxially deposited on a GaAs substrate and then bonded to a silicon solar cell structure. Subsequently the GaAs substrate is removed, and a front and rear contact as well as an antireflection coating are applied.

“Key to the success was to find a manufacturing process for silicon solar cells that produces a smooth and highly doped surface which is suitable for wafer bonding as well as accounts for the different needs of silicon and the applied III-V semiconductors,” explains Dr. Jan Benick, team leader at Fraunhofer ISE.

“In developing the process, we relied on our decades of research experience in the development of highest efficiency silicon solar cells.” Institute Director Prof. Eicke Weber expresses his delight: “I am pleased that Fraunhofer ISE has so convincingly succeeded in breaking through the glass ceiling of 30 percent efficiency with its fully integrated silicon-based solar cell with two contacts. With this achievement, we have opened the door for further efficiency improvements for cells based on the long-proven silicon material.”

“The III-V / Si multi-junction solar cell is an impressive demonstration of the possibilities of our ComBond® cluster for resistance-free bonding of different semiconductors without the use of adhesives,” says Markus Wimplinger, Corporate Technology Development and IP Director at EV Group. “Since 2012, we have been working closely with Fraunhofer ISE on this development and today are proud of our team’s excellent achievements.” The direct wafer-bonding process is already used in the microelectronics industry to manufacture computer chips.

On the way to the industrial manufacturing of III-V / Si multi-junction solar cells, the costs of the III-V epitaxy and the connecting technology with silicon must be reduced. There are still great challenges to overcome in this area, which the Fraunhofer ISE researchers intend to solve through future investigations. Fraunhofer ISE’s new Center for High Efficiency Solar Cells, presently being constructed in Freiburg, will provide them with the perfect setting for developing next-generation III-V and silicon solar cell technologies. The ultimate objective is to make high efficiency solar PV modules with efficiencies of over 30 percent possible in the future.

The young researcher Dr. Romain Cariou carried out research on this project at Fraunhofer ISE with the support of a Marie Curie Postdoctoral Fellowship. Funding was provided by the EU project HISTORIC. The work at EVG was supported by the Austrian Ministry for Technology.

Since President Obama took office in 2009, the Administration has focused on promoting innovation for the purposes of strengthening the economy, improving quality of life, and protecting the safety and security of our country.

Last week, the President’s Council of Advisors on Science and Technology (PCAST) announced the formation of a new working group focused on strengthening the U.S. semiconductor industry in ways that benefit the nation’s economic and security interests.

Semiconductors are essential to many aspects of modern life, from cellphones and automobiles to medical diagnostics to reconnaissance satellites and weapon systems. The semiconductor industry directly employs 250,000 workers, is the third largest source of U.S. manufactured exports, and has the highest level of investment in research and development (R&D) as a percentage of sales of any major industry. In addition, the semiconductor industry creates foundational technologies that enable innovation in virtually every sector of the U.S. economy. A loss of leadership in semiconductor innovation and manufacturing could have significant adverse impacts on the U.S. economy and even on national security.

In a world where the supply chains are global, policies being pursued by other countries are posing new challenges to the U.S. semiconductor industry. Specifically, some countries that are important in this domain are subsidizing their domestic semiconductor industry or requiring implicit transfer of technology and intellectual property in exchange for market access. Such policies could lead to overcapacity and dumping, reduce incentives for private-sector R&D in the United States, and thereby slow the pace of semiconductor innovation and realization of the economic and security benefits that such innovation could bring.

The industry may also be approaching technological and economic inflection points. Based on the currently commercialized approach to semiconductor technology, the industry may soon be unable to continue the pace of advance described by “Moore’s Law”—doubling the processing power of chips every 18–24 months—a pace that has brought with it rapid advances in the capabilities of systems that use semiconductors, opened up new applications, and thus fueled economic growth while increasing quality of life and strengthening national security. Indeed, the exponentially growing cost of designing and fabricating higher-performance chips in the conventional mold is already stifling innovation, making it more difficult for startups and new ideas from university research to create new markets—a key source of competitive advantage for America’s entrepreneurial economy.

Additional public and private investments in R&D are almost certain to be required if the past remarkable pace of improvements in price and performance of semiconductors and the benefits deriving therefrom are to continue—R&D that looks to create new technologies that can leapfrog beyond the limits of today’s technology and explore entirely new computer architectures and their integration into systems well beyond the traditional computing sphere, including automotive and other mobile applications.

The time is therefore right for a fresh look at the policy issues shaping innovation and global competition in the semiconductor industry. The new PCAST working group will identify the core challenges facing the semiconductor industry at home and abroad and identify major opportunities for sustaining U.S. leadership. Based on its findings, the working group will deliver a set of recommendations on initial actions the Federal government, industry, and academia could pursue to maintain U.S. leadership in this crucial domain.

The full working group includes the following members:

  • John Holdren (Director, OSTP; PCAST Co-Chair); Working Group Co-Chair
  • Paul Otellini (Former President and CEO, Intel); Working Group Co-Chair
  • Richard Beyer (Former Chairman and CEO, Freescale Semiconductor)
  • Wes Bush (Chairman, CEO, and President, Northrop Grumman)
  • Diana Farrell (President and CEO, JP Morgan Chase Institute)
  • John Hennessy (President Emeritus, Stanford University)
  • Paul Jacobs (Executive Chairman, Qualcomm)
  • Ajit Manocha (Former CEO, GlobalFoundries)
  • Jami Miscik (Co-CEO and Vice Chairman, Kissinger Associates; Co- Chair, President’s Intelligence Advisory Board)
  • Craig Mundie (President, Mundie and Associates; Former Senior Advisor, Microsoft; Member of PCAST)
  • Mike Splinter (Former CEO and Chairman, Applied Materials)
  • Laura Tyson (Distinguished Professor of the Graduate School, UC Berkeley; Former CEA Chair and NEC Director)

Astronics Corporation (NASDAQ:ATRO), through its wholly-owned subsidiary Astronics Test Systems, introduced its new breakthrough System-Level Test (SLT) platform that is expected to revolutionize the testing of high volume integrated semiconductor devices.  The new ATS 5034 System-Level Test (SLT) Platform improves production efficiency and greatly reduces the cost of test by processing up to 396 devices simultaneously.

This new platform is ideal for testing the latest semiconductor devices for mobile, automotive, wearable and industrial applications.  The ATS 5034 SLT Platform can be tailored to meet precise production test requirements.  Customers will benefit from the dramatically reduced footprint of the ATS 5034 SLT Platform and the ability to test up to 5,000 units per hour (UPH).

“For the past 20 years, we’ve provided system-level and burn-in testers that have tested more than 9 billion semiconductor devices globally,” explained Jon Sinskie, Executive Vice President of Astronics Test Systems.  “The ATS 5034 SLT Platform is our newest tester, which for the first time offers an affordable method for semiconductor manufacturers to improve yields by implementing a 100% SLT test insertion in production.”

Affordable 100% SLT through a Massively Parallel Platform

The new ATS 5034 SLT Platform tests integrated semiconductors in “mission mode” to verify performance of the semiconductor at the operating level.  Traditionally a difficult, expensive test insertion, the new ATS 5034 makes it simple for manufacturers to now transition to 100% SLT affordably.  An engineer can design a test sequence for a single site, and the ATS 5034 SLT Platform easily scales that sequence to hundreds of sites.

“With the increasing complexity of today’s semiconductor devices and pressures to cost effectively hit aggressive time to market schedules, customers are looking for new ways to find defects that are missed during traditional ATE functional testing,” explained Anil Bhalla, Senior Marketing Manager for Astronics Test Systems.  “We’ve built a platform that enables customers to find these defects with SLT in a way that previously was not cost effective.”

Customizable and adaptable, this versatile modular platform satisfies a variety of manufacturing test functions including system characterization, validation, and qualification, system-level test and RMA/failure debug.

Key features include:

  • Testing of integrated semiconductor devices, such as microprocessors, microcontrollers, and embedded systems
  • Test up to 396 devices simultaneously, at a rate of up to 5,000 UPH
  • Support for popular package types: system on chip (SoC), module, and heterogeneous system in package (SiP)
  • Turnkey automation with JEDEC trays input and outputs, including lot cascading
  • Astronics’ ActivATE™ software, an easy-to-use test executive
  • Extremely accurate thermal stress testing capability (+/- 1° C)
  • Small factory footprint

Astronics can further customize this platform for various low, medium or high volume system-level test scenarios.  This platform also includes support from the Astronics program management organization, which oversees installation and maintenance at any global location.  Units are in production and shipping in the first quarter of 2017.

Lattice Semiconductor Corporation (NASDAQ:LSCC) and Canyon Bridge Capital Partners, Inc. today announced that Lattice and Canyon Bridge Acquisition Company, Inc., an affiliate of Canyon Bridge, have signed a definitive agreement under which Canyon Bridge will acquire all outstanding shares of Lattice for approximately $1.3 billion inclusive of Lattice’s net debt, or $8.30 per share in cash. This represents a 30% premium to Lattice’s last trade price on November 2, 2016, the last trading day prior to announcement.

Darin G. Billerbeck, President and Chief Executive Officer of Lattice, commented, “We are pleased to announce the transaction today with Canyon Bridge, which will unlock tremendous value for shareholders. This transaction is the culmination of an extensive review process with our Board, financial and legal advisers, and it delivers certain and immediate cash value to shareholders while reducing our execution risk. We are excited to leverage Canyon Bridge’s resources and market connections as we enhance our focus on executing our long-term strategic plan of continued innovation. Importantly, we will operate as a standalone subsidiary after the acquisition and do not expect any changes in our operations or our unwavering commitment to continued innovation for our customers.”

Ray Bingham, Founding Partner, Canyon Bridge, noted, “Lattice’s low-power FPGA franchise, along with its video connectivity and wireless solutions, make it a compelling, strategic investment. We expect the Company will continue to leverage its existing customer relationships with major OEMs globally, while further broadening the role of its technology solutions and accelerating its strategic plans.”

Benjamin Chow, Founding Partner, Canyon Bridge, added, “Equally critical in our decision to partner with Lattice is the Company’s world-class management team and its dedicated, highly experienced employee base. Our long-term interests are aligned with Lattice’s employees and customers. We plan to build upon Lattice’s achievements and are excited to provide the resources necessary to help the Company achieve significant growth and long-term success.”

The transaction has been unanimously approved by both companies’ boards of directors and is expected to close in early 2017 subject to customary closing conditions, regulatory approvals and approval by Lattice’s shareholders. Lattice and Canyon Bridge are committed to proactive engagement with regulators to facilitate the government review process.

Upon the completion of the transaction, Lattice will be a standalone subsidiary of Canyon Bridge and Lattice’s senior management team will continue to lead the business from its current headquarters in Portland, OR.

Morgan Stanley & Co. LLC is serving as the sole financial adviser to Lattice and Skadden, Arps, Slate, Meagher & Flom LLP is serving as legal adviser. Lazard is serving as the financial adviser to Canyon Bridge and Jones Day is serving as legal adviser.

Qualcomm’s proposed acquisition of NXP Semiconductors marks the latest deal in a wave of industry consolidation that includes increasingly expensive transactions with greater focus on expanding scope rather than economies of scale, according to Fitch Ratings. Fitch believes consolidation in the chip industry will continue through the intermediate term within the context of cheap financing and tepid demand in more mature semiconductor markets.

While the NXP deal is expensive (and the largest ever) at $47 billion, including nearly $8 billion of net debt at NXP, Qualcomm will be able to tax-efficiently use offshore cash to fund a material amount of the all-cash transaction, given NXP’s Dutch incorporation. Fitch estimates Qualcomm will use approximately $28 billion of its $31 billion of total available cash at June 26, 2016 (more than $28 billion is located outside the U.S.) of offshore cash as of June 26, 2016 (versus $31 billion of total cash) and $11 billion of new debt, resulting in a Fitch estimated total leverage (total debt to operating EBITDA) of roughly 3.2x at closing. Despite the high price tag, Fitch believes the 4.6x revenue purchase multiples is in line with averages paid in large transactions completed over the last year, which Fitch estimates was roughly 5x revenues.

The Qualcomm deal with NXP is the latest example of chip companies acquiring capabilities within growth markets, particularly automotive and internet of things (IoT), as traditional semiconductor PC and smartphone markets mature. Qualcomm expects the acquisition will increase its addressable market by 40%, driven by increasing semiconductor content per car in automotive markets, exponential growth of connected devices in IoT markets and growing adoption of credit card security technologies.

Avago Technologies’ Feb. 2, 2016 acquisition of Broadcom for $37 billion focused on leveraging Broadcom’s leading wi-fi technology for the IoT market. Qualcomm’s August 2016 $2.4 billion acquisition of CSR plc strengthened Qualcomm’s nascent automotive and IoT offerings with significant semiconductor and software capabilities. Intel’s December 2015 acquisition of Altera Inc. for $16.7 billion acquisition of Altera diversified Intel away from personal computers by combining Altera’s field-programmable gate arrays with Intel’s low power processors for IoT applications. Even NXP’s December 2015 $12 billion acquisition of Freescale Semiconductor focused on expanding already strong capabilities and share in automotive and IoT markets.

Qualcomm has been in strategic review mode over the past few years amid growth concerns reflecting intensifying competition in the maturing smart phone market from the likes of Intel and a less robust long-term outlook for licensing revenue in China, where most smartphone unit growth is expected. The acquisition of NXP meaningfully diversifies Qualcomm’s end market exposure, reducing wireless handset exposure to below 50% of mobile products sales from 61% currently, and provides a top line growth catalyst, as well as earnings growth beyond significant share repurchases.

Fitch believes deal integration may be complicated by NXP’s ongoing integration of Freescale, which was structured largely as a merger of equals, and lack of technology overlap, given Qualcomm’s system-on-a-chip for mobile devices and telecom equipment focus and NXP’s focus on mixed-signal semiconductors and microprocessors and microcontrollers.