Category Archives: Displays

Today, SEMI announced details about the SEMI Industry Strategy Symposium (ISS) on January 10-13 where semiconductor executives will discuss “Integrating for Growth: Markets, Technology, and Ecosystem” in Half Moon Bay, Calif.  Industry leaders present the current status of their major technological and economic challenges while economists and industry analysts discuss their views of global economic and industry forecasts. Attendees hear diverse perspectives from IC design, manufacturing, foundry, R&D, and consumer electronics.

Emerging applications are broadening the scope of the traditional semiconductor business, resulting in advanced capabilities and expanded ecosystems. Growing semiconductor complexity serves diverse markets, sophisticated technologies, and expanding ecosystems, while escalating costs related to innovation and investment requirements remain a concern. Still Moore’s Law continues to relentlessly push both silicon and the industry to new limits associated with physics and economics.  With an era of disruptive innovation on the horizon, the industry is focusing on creating value and achieving growth using an integrative platform approach. ISS will focus on a breakthrough approach that fosters greater sharing of resources and more effective strategies for accomplishing mutual goals, industry-wide.

Highlights of the conference include:

  • Keynotes: Mary J. Miller, U.S. Army; Haruyoshi Kumura, Nissan; and Ken Hansen, Semiconductor Research Corporation
  • ISS CxO Panel on “It’s 2050… Moore’s Law is Dead… What’s the New Business Model?” with panelists from Brewer Science, Intel, Synopsys, and more
  • Economic Trends: Keynote by Duncan Meldrum, Hilltop Economics; with presentations from Gartner, IC Insights, McKinsey & Company, Pacific Crest Securities, SEMI, and VLSI Research
  • Market Perspectives: Presentations from AnandTech, International Business Strategies, Jefferies, Robert Bosch LLC, and SanDisk
  • Technology and Manufacturing: Presentations from Amkor Technology, ASM International, GLOBALFOUNDRIES, IM Flash Technologies, Intel, Qualcomm, SMIC, and SUNY Poly/CNSE
  • Collaboration Towards Success: Presentations from ASML, Intel Capital, and Micron

For more information on the SEMI Industry Strategy Symposium, please visit: www.semi.org/iss.

BY PETER CONNOCK, Chairman of memsstar

The dramatic shift from the trend for increasingly advanced technology to a vast array and volume of application-based devices presents Europe with a huge opportunity. Europe is a world leader in several major market segments – think automotive and healthcare as two examples – and many more are developing and growing at a rapid rate. Europe has the technology and manufacturing skills to satisfy these new markets but they must be addressed cost effectively – and that’s where the use of secondary equipment and related services comes in.

While Moore’s Law continues to drive the production of advanced devices, the broadening of the “More than Moore” market is poised to explode. All indicators are pointing to a major expansion in applications to support a massive increase in data interchange through sensors and related devices. The devices used to support these applications will range from simple sensors to complex packages but most can, and will, be built by “lower” technology level manufacturing equipment.

This equipment will, in many cases, be required to be “remanufactured” and “repurposed” but will allow semiconductor suppliers to extend the use of their depreciated equipment and/or bring in additional equipment, matched to their process needs, at reduced cost. In many cases this older equipment will need to be supported by advanced manufacturing control techniques and new test and packaging capabilities.

SEMI market research shows that investment in “legacy” fabs is important in manufacturing semiconductor products, including the emerging Internet of Things (IoT) class of devices and sensors, and remains a sizeable portion of the industries manufacturing base:

  • 150mm and 200mm fab capacity represent approximately 40 percent of the total installed fab capacity
  • 200mm fab capacity is on the rise, led by foundries that are increasing 200mm capacity by about 7 percent through to 2016 compared to 2012 levels
  • New applications related to mobility, sensing, and IoT are expected to provide opportunities for manufacturers with 200mm fabs

Out of the total US$ 27 billion spent in 2013 on fab equipment and US$ 31 billion spent on fab equipment in 2014, secondary fab equipment represents approximately 5 percent of the total, or US$ 1.5 billion, annually, according to SEMI’s 2015 secondary fab equipment market report. For 2014, 200mm fab investments by leading foundries and IDMs resulted in a 45 percent increase in spending for secondary 200mm equipment.

Secondary equipment will form at least part of the strategy of almost anyone manufacturing or developing semiconductors in Europe. In many cases, it is an essential capability for competitive production. As the secondary equipment industry increases its strategic importance to semiconductor manufac- turers and researchers it is critical that the corresponding supply chain ensures a supply of quality equipment, support and services to meet rapidly developing consumer needs.

Common challenges across the supply chain include:

  • How to generate cooperation across Europe between secondary equipment users and suppliers and what sort of cooperation is needed?
  • How to ensure the availability of sufficient engineering resource to support the European secondary installed base?
  • Are there shortages of donor systems or critical compo- nents that are restricting the use of secondary equipment and, if so, how might this be resolved

Europe’s secondary industry will be in the spotlight during two sessions at SEMICON Europa 2015:

  • Secondary Equipment Session – Enabling the Internet of “Everything”?
  • SEA Europe ‘Round Table’ Meeting

The sessions are organised by the SEMI SEA Europe Group and are open to everyone associated with the secondary industry, be they device manufacturer or supplier, interested in the development of a vibrant industry providing critical support to cost effective manufacturing in Europe.

Today, SEMI announced additional details on the 29th annual SEMICON Korea, with more than 40,000 expected attendees, the largest semiconductor technology event in Korea.  The theme for the January 27 through 29 exhibition at Seoul’s COEX is “Connect to the Future – Markets, Technology, and People.”  SEMICON Korea will feature new innovations, technologies and present the future of semiconductor processing technology. The event will be co-located with LED Korea 2016, the leading exhibition for LED manufacturing.

SEMICON Korea 2016 will feature over 530 leading companies from 20 countries with expectation of a record 1,870 exhibition booths. With 97 presentations on diverse topics for 60 hours, the event offers exceptional opportunities to learn and network. In addition, four industry thought leader keynotes will provide insight into the future of global semiconductor industry (including a keynote that will be announced soon before SEMICON Korea):

  • Dr. Ahmad Bahai, CTO of Texas Instruments
  • Dr. Aart de Geus, chairman and co-CEO of Synopsys: “IoT: from Silicon to Software”
  • Berthold Hellenthal, head of the Audi Progressive Semiconductor Program at Audi: “Inventing the Automotive Future”

The keynotes will be followed by a broad offering of deep programs including the SEMI Technology Symposium where experts in semiconductor manufacturing processes will discuss the latest issues and new technologies. The event also covers advanced lithography, advanced process technology, device technology, plasma science and etching, contamination-free manufacturing and CMP, and advanced packaging technologies.

In addition, forums and seminars cover major issues in the semiconductor market, including System LSI, Metrology and Inspection (MI) and Test. The SEMI Standards Program, which develops the global standards indispensable in the strengthening of international competitiveness, will conduct a strong program. Two other programs are increasingly popular with their exclusive navigation of the semiconductor manufacturing supply chain:  Supplier Search – featuring the world’s leading materials manufacturers, and OEM Supplier Search – which facilitates business cooperation between global suppliers and Korea’s parts manufacturers.  The President Reception is a SEMICON Korea highlight where industry leaders network — bringing together suppliers, customers, and innovation leaders.

For a complete schedule of technical sessions and events, visit http://www.semiconkorea.org/en/attend/program-sessions.

SEMICON Korea 2016 registration (www.semiconkorea.org/en) opens November 16. Complimentary registration includes access to the exhibition area and attendance of the keynote speeches.

While conventional thin film transistor liquid crystal (TFT LCD) displays are rapidly trending towards commoditization and currently suffering from declining prices and margins, China is quickly adding capacity in all flat-panel display (FPD) manufacturing segments. Supported by financial incentives from local governments, Chinese TFT capacity is projected to grow 40 percent per year between 2010 and 2018. In 2010 China accounted for just 4 percent of total TFT capacity. However by 2018, China is forecast to become the largest FPD-producing region in the world, accounting for 35 percent of the global market, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight.

While Chinese capacity expands, Japan, South Korea and Taiwan have restricted investments to focus mainly on advanced technologies. TFT capacity for flat panel display (FPD) production in these countries is forecast to grow on average at less than 2 percent per year between 2010 and 2018.

Based on the latest IHS Display Supply Demand & Equipment Tracker, BOE Technology Group stands out as the leading producer of FPDs in China. With a capacity growth rate of 44 percent per year between 2010 and 2018, BOE will become the main driver for Chinese share gains. By 2018, the company will have ramped up more FPD capacity than any other producers, except for LG Display and Samsung Display.

“Despite growing concerns of oversupply for the next several years in most parts of the display industry, there is still little evidence that Chinese makers are reconsidering or scaling back their ambitious expansion plans,” said Charles Annis, senior director at IHS. “On the contrary, there continues to be a steady stream of announcements of new factory plans by various regional governments and panel makers.”

In China, the central government has generally encouraged investment in FPDs, in order to shift the economy to higher technology manufacturing, to increase domestic supply and to support gross domestic product (GDP) growth. Provincial governments have become the main enabler of capacity expansion through product and technology subsidies, joint ventures and other direct investments, by providing land and facilities and through tax incentives. In return, new FPD fabs increase tax revenue, support land value appreciation, increase employment and spur the local economy. The economic benefits generated from the feedback loop between local governments, panel makers and new FPD factories are still considered sufficiently positive in China to warrant application of significant public resources.

“China currently produces only about a third of the FPD panels it consumes. However, by rapidly expanding capacity, panel makers and government officials are expecting to double domestic production rates in the next few years and are also looking to export markets,” Annis said. “How excessive global supply, falling prices and lower profitability will affect these plans over time is not yet exactly clear. Even so, there is now so much new capacity in the pipeline that China will almost certainly become the top producer of FPDs by 2018.”

The IHS Display Supply Demand & Equipment Tracker covers metrics used to evaluate supply, demand, and capital spending for all major FPD technologies and applications.

Systematic – and predictive – cost reduction in semiconductor equipment manufacturing

BY TOM MARIANO, Foliage, Burlington, MA

After a period of double-digit growth, the semiconductor equipment industry has now stabilized to the point where recent market forecasts are predicting anemic single-digit growth rates. This is driven by total market demand from chipmakers. For example, despite strong growth of 12.9 percent in 2014, Gartner, Inc. projects worldwide semiconductor capital spending to only grow 0.8 percent in 2015, to $65.7 billion. [1] Additionally, this industry has always been subject to volatile demand cycles that are notoriously difficult to predict.

Translation: It’s extremely challenging for today’s semiconductor equipment manufacturers to improve their financial performance. There are fewer and fewer opportunities to grow topline revenue through innovation and new product development. And, after several years of cutting costs on existing products and not realizing enough cost reduction to improve margins, it’s difficult to know how to do it differently.

Yet a viable alternative to improve financial performance does exist: A disciplined, rigorous, and systematic approach to reducing costs that delivers more predictive results.

A systematic approach to cost reduction

Where cutting costs was once perceived as the end result of “desperate times, desperate measures,” many innovators are now using this approach much more proactively. By
meeting the idea of cost reduction head on – as an opportunity, not a last resort – many semiconductor equipment makers are uncovering wasteful, inefficient, and costly processes, often in areas they once overlooked. At this point, you may be thinking, “All of this sounds great, but what is a systematic approach to cost reduction, and how is it different from what I’m doing?”

Remember that many manufacturers (in all industries) tend to have a hard time driving costs down. They may set cost reduction goals and then attempt to achieve them using various ad hoc approaches. But they really need to understand exactly what their true costs are, where they exist, and which areas will improve their margins.

A systematic approach to cost reduction gives them this insight. With improved visibility into the entire organization, various processes, and how they execute, semiconductor equipment manufacturers can’t identify the right places to cut costs and hit their cost savings goals. This is a very detailed and planned approach in which organizations closely examine areas such as cost of goods sold, R&D, and service to make more informed decisions that will position their business for long-term success. This is the value of a systematic approach to cost reduction.

This approach also introduces the element of speed, helping equipment makers realize cost savings much faster than ad hoc cost-cutting initiatives and puts them on a path to achieve more predictive results. Beyond the positive (and more obvious) impact successful cost reduction has on a semiconductor equipment manufacturer’s bottom line, it also provides a number of significant benefits such as improving productivity, freeing up key personnel, and providing needed capital to fuel new growth.

The path to predictive results

Even if the concept of a more strategic approach to cutting costs sounds reasonable, many semiconductor equipment manufacturers struggle with how to begin and where to focus. All to often they resort to making reactive decisions regarding existing products without the necessary data, leading them to ask questions such as, “Should we have an obsolescence plan for this product?” “How much could we save?” and “Will this lead to bigger problems down the road?”

Without understanding where your best opportunities for cost cutting are, it’s a lot larder to predict when, and if, cost reduction goals will be met. A systematic approach to cost reduction includes establishing clear cost targets, communicating them to leadership, and measuring and reporting results along the way.

The first step is to engage with an outside firm that has a singular focus on cost reduction, and one that is clearly separated from day-to-day operations and current organizational dynamics. Such an engagement will yield an actionable list of improvements with specific cost targets, realistic timelines for achieving these goals, and future plans for reinvesting the cost savings.

More specifically, a systematic cost reduction approach will focus on three key areas: material costs, R&D costs, and service costs:

1. Material costs: The bill of materials is one of the most common ways to see all the components needed to produce the end product. But this goes well beyond the pure cost of materials. Research has shown that improving the way these components are managed can affect 80-90% of the product’s total costs.[2]

For semiconductor equipment manufacturers, the cost reduction process should start with the selection of the products or sub-assemblies that have the highest potential for savings. Focus on those products that are still generating significant revenue, but may not be receiving much attention in terms or engineering upgrades and enhancements. Thoroughly examine the bill of materials for these products by addressing materials, design, complexity reduction, the potential to create common assemblies, and more.

Value engineering efforts can simultaneously improve product functionality and performance while reducing bill of material costs. This effort should factor in ways to meet RoHS requirements and when to make end-of-life decisions for various electrical components to improve design efficiency and the effectiveness of the product.

A realistic cost reduction goal can then be created and a resulting value-engineering project can commence, often using low-cost offshore resources to best achieve those savings.

2. R&D costs: Making better decisions related to R&D processes and product development can shave considerable costs. Some areas to focus on include:

• When to officially end of life non-performing products
• When to consolidate products, or possibly even entire R&D departments
• When and how to move sustaining engineering efforts offshore, or to other lower-cost alternatives

The critical next step is to look at all products and all product variations to determine if an official end-of-life program should be employed. These decisions are notoriously hard to make and often require difficult conversations with key customers, but they are necessary nonetheless.

Many semiconductor equipment manufacturers have grown through acquisitions, creating redundant engineering groups that can be eliminated or downsized. Performing an organizational analysis of all R&D activities may uncover opportunities to consolidate and combine functions or create centers of excellence that focus on specific technical areas eliminating redundancies of technical specialty.

3. Service costs: Examine engineering and design processes to find ways to improve performance, reliability, and costs. For example, adding data collection technology or product diagnostics to enhance remote support efforts and predictive maintenance.

Improvement of product reliability is usually a large multiplier when it comes to service and spare parts costs. Collect and analyze field data to find the most significant issues driving service costs and then look to cut where possible.

For example, equipment in the field often does not have the capability to report enough information to effectively identify a problem. Adding increased data logging and communication can be used to clarify machine status and point services in the right direction. Connectivity can also help with remote diagnostics, all of which helps reduce costs, uptime, and customer satisfaction.

Cost Reduction as a Competitive Advantage

Short-term market forecasts will continue to make it challenging for semiconductor equipment manufacturers to deliver improved financial results. Yet the concept of a systematic approach to cost reduction is a proven way for them to proactively cut costs – in the right places – and also make better decisions related to existing products and other business systems and processes.

By taking a disciplined, rigorous, and objective look at any and all parts of their organization, semiconductor equipment makers can capitalize on new opportunities to free valuable resources, improve processes and future technology, and reinvest savings for future growth. For many equipment manufacturers the greatest obstacle to successfully exploiting these opportunities is insufficient experience and expertise with a disciplined and unconventional way of approaching cost reduction projects. A systematic approach to cost reduction will be the key to success for companies looking to improve their competitive advantage.

References

1. Gartner, Inc., “Gartner Says Worldwide Semiconductor Capital Spending to Increase 0.8 Percent in 2015: Conser- vative Investment Strategies Paving the Way to Slower Growth in 2015,” January 13, 2015. http://www.gartner. com/newsroom/id/2961017.

2. Forbes, “Product Lifecycle Management: A New Path to Shareholder Value?” August 5, 2011, http://www. forbes.com/sites/ciocentral/2011/08/05/product-lifecycle- management-a-new-path-to-shareholder-value/.

Sapphire is hard, strong, optically transparent and chemically inert.

BY WINTHROP E. BAYLIES and CHRISTOPHER JL MOORE, BayTech-Resor LLC, Maynard, MA

Have you ever wondered what blue gemstone earrings, an LED lightbulb and an Apple Watch have in common? The answer (at least for this article) is that all depend on sapphire as part of their manufacturing process. In part 1 of the following two part article, we will discuss how sapphire is becoming an important part of the mobile device food chain. Part 2 will concentrate on how sapphire is used in LED production.

Sapphire (chemical composition Al2O3) has a high melting point of 2040°C (3704°F) and is chemically resistant even at high temperatures. It is an anisotropic material meaning that its mechanical/thermal properties depend on the direction of the crystal plane that is cut and polished. An insulator with a 9.2 eV energy gap it is optically transparent. With a hardness of 9 on the Mhos scale, it is almost as hard and strong as diamond (10 Mhos).

To summarize, sapphire has some good points: hard, strong, optically transparent and chemically inert (there is a reason high end watches use sapphire crystals) and some bad points: hard, strong, and chemically inert (which is why sapphire crystals are more expensive than glass). That is, the very properties that make it ideal for applications needing mechanical strength and hardness mean that it is a difficult material to grow, machine and polish.

There are several places where sapphire can be (or is now) used in the manufacture of mobile devices. The most publicity in this area was generated in 2014 with significant speculation in both the trade magazines and newspapers (such as the Wall Street Journal) that the iPhone 6 would be released with a sapphire touch screen or at the very least a sapphire cover glass over the existing touchscreen. Part of this speculation was fueled by the large number (1700 to 2500 depending on source) of sapphire producing furnaces being installed at an Apple facility in Mesa Arizona. However, the sapphire iPhone 6 was not released due in part to the difficulties in growing and processing enough sapphire screens at a reasonable cost to supply the significant number of phones produced. There are now sapphire touch screen phones available from other suppliers and recently, the Apple Watch was released with a sapphire screen. In addition, many fingerprint sensors and camera cover glasses are now produced using sapphire as the cover material.

Requirements for sapphire material is clear (forgive the pun). For screens and cameras, it must be of good optical quality i.e. transmit light well and have low surface roughness. For fingerprint sensors, it needs consistent surface quality and electrical properties.

Production process

FIGURE 1 shows a schematic of the production process for sapphire used in a mobile device screen. The following paragraphs provide more detail on this process [1] as well as a few of problems encountered along the way.

Sapphire Fig 1

The sapphire production process starts when a seed crystal and a mixture of aluminum oxide and crackle (un-crystallized sapphire material) is heated using a specific temperature/time profile, then cooled (this process can take two weeks depending on the amount of sapphire being produced) using a carefully controlled set of time/temperature profiles. When done correctly, the cookie sized seed grows and produces a single-crystal sapphire boule. That at least is the theory. In reality, two weeks is a long time and any number of problems can go wrong during this process including gas bubbles, mechanical faults such as cracks and contamination. Each of these problems can affect the sapphire and its optical/electrical properties. There is a clear correlation between the time taken to grow a boule and the potential quality of the boule produced. Many of the problems encountered in the upscaling of the sapphire production process sprang from trying to grow large boules at high speeds.

It is at the next step in the process where boule size does matter. Typically, the boule will be drilled or cut to produce material near the size needed for the particular application. It makes a significant difference if the material is for a watch crystal (say 1.5 inch diameter ~ 1.7 square inches). Here you can “core-drill” a boule to produce a number of smaller cylinders. For a phone screen/cover plate (at 4 by 6 inch i.e. 24 square inches) a larger portion of the boule is needed for a box shape. The ability to grow large sized boules on a regular basis is not in question; most important is how much of that boule is bubble-, crack- and impurity-free. In some cases the boules are inspected with various metrology techniques to determine which sections of the boule can be used and which cannot. The section of the boules not used is recycled into the original growth process (unless contaminated).

Given the hardness of the sapphire, diamond wire saws or diamond core drills are used for cutting or coring the boules. The yield from any boule is a function of the original boule size, the size of the cores or slabs being produced and the volume of the boule free from imperfections. As was discussed earlier, and is typical of many processes, the larger the size of the piece the lower the yield.

The next step is to take the cylindrical cores (or rectangular slabs) and cut them into appropriate sized pieces. The thickness of the desired part and the amount the producer is willing to invest in high technology solutions determines what is done next. On one end of the technology scale, the parts are cut using a wire saw or an abrasive cutoff saw. On the other end of the scale, you can ion implant the surface to produce a damaged layer at a depth below the surface determined by the original ion energy. If the slab is heated after sufficient implantation is done, a thin sheet will separate from the surface. Both processes result in parts of the approximate size needed for the application; a discussion of the pros and cons of each approach is beyond the scope of this article.

The process after this point depends on the parts’ final application and their manufacturer. Given the difficulty of polishing a material this hard many of the bigger companies have developed proprietary process for grinding or mechanically polishing the sapphire parts to the desired shape and surface roughness/finish. From a mechanical strength standpoint, it is important that there be no significant scratching of the surface or chipping of the edges which could severely limit the mechanical strength of the final piece. From an optical standpoint, it is important to produce a uniform finish so as not to effect the overall appearance of the part. At this stage, the parts are then ground to their final size and any additional shaping of the part including holes/ profiles is done. FIGURE 2 shows a variety of sapphire parts at this stage of the process.

Sapphire Fig 2

In most sapphire part production these parts are next coated with a variety of optical and/or electrical and/ or chemical films again depending on their application. Because of its high index of refraction (1.76) a sapphire screen or watch crystal is highly reflective. For this application, the parts are typically coated with a series of films to produce an anti-reflection coating enhancing final screen readability. For parts that will be touched on a regular basis such as touchscreens or fingerprint sensors coatings, it is important that they be “self-cleaning.” In these cases, hydrophobic and oleophobic coatings are used to make sure your fingerprints are less likely to stay behind after the material has been touched. FIGURE 3 shows a series of parts after the coating and silk screening process. They are now ready for assembly into the mobile device.

Sapphire Fig 3

The use of sapphire in mobile devices is driven by two main concerns. One is that the final screen/sensor be mechanically stronger and harder than most glasses. There are a number of videos [2] available showing cement blocks being dragged over cell phones to show the sapphire screens’ scratchproof capabilities. The second (and not as well known) factor is the significant data showing that touch sensors made using sapphire have better performance characteristics due to its superior electrical properties and electrical uniformity. This allows the development of sensors which have improved performance in the field.

The downside of using sapphire remains its cost. Estimates [3] have reported sapphire costs 2 to 10 times the price of an equivalent glass part. Although these costs are coming down, in price sensitive applications glass continues to dominate at this time and it is expected that only higher end phones will use sapphire screens.

In the second part of this article, we will discuss the importance of sapphire in the LED industry and the difference in process needed for this material.

Additional reading/viewing material

1. http://www.businessinsider.com/how-sapphire- glass-screens-are-made-2014-9
2. Video Aero Gear’s Flight Glass SX Sapphire Crystal vs a Concrete
3. http://seekingalpha.com/article/2230553-ignore- the-sapphire-threat-corning-is-on-a-roll

By Dr. Harry Zervos, Principal Analyst, IDTechEx

Flexible electronic devices are starting to experience significant proliferation, with more and more devices with innovative form factors being brought to market, from small components such as disposable sensors that have been in the market for quite some time now, all the way to new flexible smart phones currently being demonstrated by consumer electronics giants like Samsung and LG.

While printing technologies enable lower manufacturing costs and superior performance in many applications, vacuum deposition still claims significant market share in flexible electronics, although sometimes a combination of both can be the ideal combination.

From test strips to OLEDs 

Glucose test strips are a great example of the prevalence of both printed and vacuum deposited devices. Over ten billion test strips are being manufactured worldwide, in order to cater for the needs of the ever-increasing number of people living with diabetes. Although each manufacturer/brand has its own technology and design, the following cross-section shows the key parts of a test strip.  Manufacturers follow both thick film (screen printing) and thin film (sputtering) techniques for depositing the circuit in test strips, each of the techniques with its own merits.

Screen printing technology involves printing patterns of conductors and insulators onto the surface of planar solid (plastic or ceramic) substrates based on pressing the corresponding inks through a patterned mask. Each strip contains printed working and reference electrodes with the working one coated with the necessary reagents and membranes, with the reagents commonly dispensed by ink jet printing technology and deposited in the dry form. With thin film deposited electrodes, sputtering or laser ablation is commonly utilized. Lifescan for instance, a Johnson & Johnson company, mostly prints electrodes whereas Roche utilizes laser ablation in its Indianapolis plant. Along with the very specialized organic materials utilized in assays in the actively sensing part of the test strips, advanced devices integrating thin film technology utilize gold nanoparticles and mesoporous Pt electrodes, and even the use of carbon nanotubes and graphene has been demonstrated in certain designs.

OLED displays are a good example where the advent of printing techniques is meant to bring about much larger displays, manufactured at lower costs but for the time being, the OLED industry makes displays that are almost exclusively vacuum evaporated. Optimized solution processed materials are also becoming available but for now, vacuum deposited options perform better. Sunic, Aixtron, Canon Tokki and ULVAC are some of the companies that actively design and market equipment and materials for industrial vacuum technology in OLED applications.

Most of these companies, along with others such as Applied Materials are active in making more than just the active OLED layers, providing equipment for TFT deposition, encapsulation, etc.

The opportunity here is significant: The OLED market is meant to reach over $50bn in the next decade, with flexible and rigid plastic OLED displays surpassing 16 billion by 2020.

Flexible encapsulation & thin film PV

Encapsulation of flexible versions of OLED displays is set to become an exciting market: flexible barrier films – whether utilizing CVD or PVD processes or even in cases when ALD is utilized to make high quality, defect free layers- are hugely benefiting from vacuum deposition techniques and have created encapsulation materials that can reach the water vapor transmission rates required to allow flexible OLED displays the necessary lifetimes required to become commercially viable. Encapsulation for flexible OLED devices is a market that is expected to reach almost $340m by 2022 according to IDTechEx Research in the report “Barrier Layers for Flexible Electronics 2016-2026: Technologies, Markets, Forecasts”.

Flexible versions of thin film photovoltaics also require stringent encapsulation, but thin films have had harsh competition from low cost crystalline silicon cells from China, that have significantly reduced their market share in recent years. Just over 7% of the overall market for PV this year is expected to be thin-film based, according to research from SPV Research.

It is interesting to point out that manufacturing of all thin films for solar cell applications is fully vacuum based: PECVD for amorphous silicon platforms, sputtering or co-evaporation tends to be the preferred deposition techniques for CIGS technologies while CdTe leader First Solar has developed and optimized its own unique vacuum deposition technique, High Rate Vapor Transport Deposition (HRVTD). In this process, co-developed with NREL in an effort that started back in the early 1990’s, the material to be deposited is carried on a gas stream in powder form, then heated and vaporized as it passes through a membrane before depositing on a glass substrate. The technology can deposit a thin uniform layer of CdTe (or CdS, a common material system used as a buffer layer in CdTe cells) on 8 square feet of glass in less than 40 seconds, a deposition rate much higher than other rival thin film solar technologies that proved to be key in First Solar’s success in improving yield and output and consequently lower production costs for its thin film solar cells.

Conclusions 

The conclusion is simple: commercializing flexible or printed electronics will invariably require a deeper understanding of vacuum deposition technologies. Printing techniques are not the only manufacturing option that can allow for the freedom in design that the advent of flexibility in form factor is ushering in. In fact, vacuum deposition technologies are currently enabling the proliferation of a wide range of components and devices, from encapsulation films to thin flexible batteries to transparent conductive films and backplane elements. In many cases, having reached economies of scale, vacuum deposited devices have reached attractive cost structures that make it harder for printed versions to compete, having to “dig deep” in order to bring forward additional selling points than just reductions in cost.

Printed Electronics USA 2015 taking place in Santa Clara, CA on the 18th and 19th of November this year is going to focus on the importance of vacuum deposition, with both the conference as well as the trade show featuring contributions from end users, device manufacturers and manufacturing equipment suppliers of vacuum deposition technologies.

Security by design


November 13, 2015

Chowdary_Yanamadala-150x150By Chowdary Yanamadala, Senior Vice President of Business Development, ChaoLogix

The advent of Internet-connected devices, the so-called Internet of Things (IoT), offers myriad opportunities and significant risks. The pervasive collection and sharing of data by IoT devices constitutes the core value proposition for most IoT applications. However, it is our collective responsibility, as an industry, to secure the transport and storage of the data. Failing to properly secure the data risks turning the digital threat into a physical threat.  

Properly securing IoT systems requires layering security solutions. Data must be secured at both the network and hardware level. As a hardware example, let’s concentrate, on the embedded security implemented by semiconductor chips.

Authentication and encryption are the two main crypto functions utilized to ensure data security. With the mathematical security of the standardized algorithms (such as AES, ECDSA, SHA512, etc.) is intact, hackers often exploit the implementation defects to compromise the inherent security provided by the algorithms.

One of the most dangerous and immediate threats to data security is a category of attacks called Side Chanel Analysis attacks (SCA). SCA attacks exploit the power consumption signature during the execution of the crypto algorithms. This type of attack is called Differential Power Analysis (DPA). Another potent attack form of SCA is exploiting the Electromagnetic emanations that are occurring during the execution of the crypto algorithm – or Differential Electromagnetic Analysis attacks (DEMA).

Both DPA and DEMA attacks rely on the fact that sensitive data, such as secret keys, leaks via the power signature (or EM signature) during execution of the crypto algorithm.

DPA and DEMA attacks are especially dangerous, not only because of their effectiveness in exploiting security vulnerabilities but also due the low cost of the equipment required for the attack. An attacker can carry out DPA attacks against most security chips using equipment costing less than $2,000.

There are two fundamental ways to solve the threat of DPA and DEMA. One approach is to address the symptoms of the problem. This involves adding significant noise to the power signature in order to obfuscate the sensitive data leakage. This is an effective technique.  However, it is an ad-hoc and temporary measure against a potent threat to data security. Chip manufacturers can also apply this technique as a security patch, or afterthought, once  and architecture work is completed.

Another way (and arguably a much better way) to solve the threat of DPA is to address the problem at the source. The source of the threat derives from the leakage of sensitive data the form of power signature variations. The power signature captured during the crypto execution is dependent on the secret key that is processed during the crypto execution. This makes the power signature indicative of the secret key.

What if we address the problem by minimizing the relation between the power signature and the secret key that is used for crypto computation? Wouldn’t this offer a superior security? Doesn’t addressing the problem at the source provide more fundamental security? And arguably a more permanent security solution?

Data security experts call this Security By Design. It is obvious that solving a problem at the source is a fundamentally better approach than providing symptomatic relief to the problems. This is true in the case of data security as well. In order to achieve the solution (against the threat of DPA and DEMA) at the source, chip designers and architects need to build the security into the architecture.

Security needs to be a deliberate design specification and needs to be worked into the fabric of the design. Encouragingly, more and more chip designers are moving away from addressing security as an afterthought and embracing security by design.

As an industry, we design chips for performance, power, yield and testability. Now it is time to start designing for security. This is especially true for chips used in IoT applications. These chips tend to be small, have limited computational power and under tight cost constraints. It is, therefore, difficult, and in some cases impossible, to apply security patches as an afterthought. The sound approach is to start weaving security into the building blocks of these chips.

In sum, designing security into a chip is as much about methodology as it is about acquiring various technology and tools. As IoT applications expand and the corresponding demand for inherently secure chips grows, getting this methodology right will be a key to successful deployment of secure IoT systems.

Related data security articles: 

Security should not be hard to implement

ChaoLogix introduces ChaoSecure technology to boost semiconductor chip security

From laptops and televisions to smartphones and tablets, semiconductors have made advanced electronics possible. These types of devices are so pervasive, in fact, that Northwestern Engineering’s Matthew Grayson says we are living in the “Semiconductor Age.”

“You have all these great applications like computer chips, lasers, and camera imagers,” said Grayson, associate professor of electrical engineering and computer science in Northwestern’s McCormick School of Engineering. “There are so many applications for semiconductor materials, so it’s important that we can characterize these materials carefully and accurately. Non-uniform semiconductors lead to computer chips that fail, lasers that burn out, and imagers with dark spots.”

Grayson’s research team has created a new mathematical method that has made semiconductor characterization more efficient, more precise, and simpler. By flipping the magnetic field and repeating one measurement, the method can quantify whether or not electrical conductivity is uniform across the entire material – a quality required for high-performance semiconductors.

“Up until now, everyone would take separate pieces of the material, measure each piece, and compare differences to quantify non-uniformity,” Grayson said. “That means you need more time to make several different measurements and extra material dedicated for diagnostics. We have figured out how to measure a single piece of material in a magnetic field while flipping the polarity to deduce the average variation in the density of electrons across the sample.”

Remarkably, the contacts at the edge of the sample reveal information about the variations happening throughout the body of the sample.

Supported by funding from the Air Force’s Office of Scientific Research, Grayson’s research was published on October 28 online in the journal Physical Review Letters. Graduate student Wang Zhou is first author of the paper.

One reason semiconductors have so many applications is because researchers and manufacturers can control their properties. By adding impurities to the material, researchers can modulate the semiconductor’s electrical properties. The trick is making sure that the material is uniformly modulated so that every part of the material performs equally well. Grayson’s technique allows researchers and manufacturers to directly quantify such non-uniformities.

“When people see non-uniform behavior, sometimes they just throw out the material to find a better piece,” Grayson said. “With our information, you can find a piece of the material that’s more uniform and can still be used. Or you can use the information to figure out how to balance out the next sample.”

Grayson’s method can be applied to samples as large as a 12-inch wafer or as small as an exfoliated 10-micron flake, allowing researchers to profile the subtleties in a wide range of semiconductor samples. The method is especially useful for 2-D materials, such as graphene, which are too small for researchers to make several measurements across the surface.

Grayson has filed a patent on the method, and he hopes the new technique will find use in academic laboratories and industry.

“There are companies that mass produce semiconductors and need to know if the material is uniform before they start making individual computer chips,” Grayson said. “Our method will give them better feedback during sample preparation. We believe this is a fundamental breakthrough with broad impact.”

Baltimore, MD — November 11, 2015 — Pixelligent, a leader in high-index advanced materials, today launched a new family of PixClear® materials for display and optical components and films. The PixClear product line is now available in a new solvent system — a low boiling ethyl acetate (ETA) — that delivers the same high performance while easing integration with customer manufacturing processes. Now leading manufacturing companies will have the choice of a standard, high boiling propylene glycol methyl ether acetate (PGMEA) or the low boiling ETA for their testing. These materials are available in both 20 percent and 50 percent loadings for PixClear PG and PixClear PB.

“The launch of our new PixClear ETA materials is a response to customer demand. These low boiling ETA dispersions will result in brighter, clearer devices produced at a lower cost, which directly supports reducing time to innovation for our customers in the display and adhesives space,” said Craig Bandes, President and CEO of Pixelligent. “At Pixelligent, we continue to expand our matrix of high quality, high-index nanomaterials in order to support the growth of our customers.” Matt Healy, Vice President of Product Management adds, “In August, we launched a full OLED materials family, which includes four products for testing internal light extraction structures for OLED lighting. All totaled, we have introduced 12 new products for customer testing in the past three months.”

PixClear zirconia dispersions are now available for order in two solvents, and at two different loadings, to complement the processes used for the production of displays and optical components.