Category Archives: Displays

CEA-Leti today announced that it has demonstrated a path to fabricating high-density micro-LED arrays for the next generation of wearable and nomadic systems in a process that is scalable to the IC manufacturing process.

The high-brightness, enhanced-vision systems such as head-up and head-mounted displays can improve safety and performance in fields such as aeronautics and automotive, where the displays allow pilots and drivers to receive key navigation data and information in their line of sight. For consumers, smart glasses or nomadic projection devices with augmented reality provide directions, safety updates, advertisements and other information across the viewing field. LED microdisplays are ideally suited for such wearable systems because of their low footprint, low power consumption, high-contrast ratio and ultra-high brightness.

Leti researchers have developed gallium-nitride (GaN) and indium gallium-nitride (InGaN) LED technology for producing high-brightness, emissive microdisplays for these uses, which are expected to grow dramatically in the next three to five years. For example, the global research firm MarketsandMarkets forecasts the market for head-up displays alone to grow from $1.37 billion in 2012 to $8.36 billion in 2020.

“Currently available microdisplays for both head-mounted and compact head-up applications suffer from fundamental technology limitations that prevent the design of very low-weight, compact and low-energy-use products,” said Ludovic Poupinet, head of Leti’s Optics and Photonics Department. “Leti’s technology breakthrough is the first demonstration of a high-brightness, high-density micro-LED array that overcomes these limitations and is scalable to a standard microelectronic large-scale process. This technology provides a low-cost, leading-edge solution to companies that want to target the fast-growth markets for wearable vision systems.”

Announced during Display Week 2015 in San Jose, Calif., Leti’s technology innovation is based on micro-LED arrays that are hybridized on a silicon backplane. Key innovations include epitaxial growth of LED layers on sapphire or other substrates, micro-structuration of LED arrays (10μm pitches or smaller), and 3D heterogeneous integration of such LED arrays on CMOS active-matrices.

These innovations make it possible to produce a brightness of 1 million cd/m² for monochrome devices and 100 kcd/m² for full-color devices with a device size below one inch and 2.5 million pixels. This is a 100- to 1,000-times improvement compared to existing self-emissive microdisplays, with very good power efficiency. The technology also will allow fabrication of very compact products that significantly reduce system-integration constraints.

The high-density micro-LED array process was developed in collaboration with III-V Lab.

IC Insights will release its Update to the 2015 IC Market Drivers report in June. The Update includes revisions to IC market conditions and forecasts for the 2015 2018 automotive, smartphone, personal computer and tablet markets, as well as an update to the market for the Internet of Things. This bulletin reviews IC Insights’ 2015 unit shipment forecast for total personal computing unit shipments.

Five years ago, touchscreen tablets began pouring into the personal computing marketplace, stealing growth from standard personal computers and signaling the start of what has been widely described as the “post-PC” era. Led by Apple’s iPad systems, tablet shipments overtook notebook PCs in 2013, and it appeared as if they would surpass total personal computer units (counting both desktop and portable systems) by 2016. However, that scenario no longer seems possible after tablet growth lost significant momentum in 2014 and then nearly stalled out in the first half of 2015 due to the rise in popularity of large-screen smartphones and the lack of interest in new tablets that do not add enough features or capabilities to convince existing users to buy replacements. Consequently, IC Insights has downgraded its forecast for the overall personal computing market, including much lower growth in tablets and continued weakness in standard PCs (Figure 1).

The updated forecast shows total personal computing unit shipments (desktop PCs, notebook PCs, tablets, and Internet/cloud-computing “thin-client” systems) dropping 1 percent in 2015 to 545 million. In the original forecast of the 2015 IC Market Drivers report (MD15), total personal computing system shipments were projected to rise 8 percent in 2015 to 609 million units, followed by a 10 percent increase in 2016 to 670 million. The revised outlook cuts the compound annual growth rate (CAGR) of personal computing unit shipments to 2.1 percent between 2013 and 2018. Total personal computing system shipments are now projected to reach 578 million in 2018.

Worldwide shipments of keyboard-equipped standard PCs (desktops and notebooks) peaked in 2012 at 345 million, but they are expected to decline by a CAGR of -0.5 percent in the 2013-2018 timeperiod. In the updated outlook, tablets are projected to account for 45 percent of total systems sold in 2018 (259 million units) versus the MD15’s original forecast of 57 percent (423 million) that year. Further into the future, tablets are now expected to account for about half of personal computing system shipments with the remaining units being divided between standard PCs and Internet/cloud-centric platforms.

IC Insights June Report

Figure 1

 

Additional details on the IC market for medical and wearable electronic is included in the 2015 edition of IC Insights’ IC Market Drivers—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits.  This report examines the largest, existing system opportunities for ICs and evaluates the potential for new applications that are expected to help fuel the market for ICs.

By Paula Doe, SEMI

Ever growing volumes of data to be stored and accessed, and advancing process technologies for sophisticated control of deposition and etch in complex stacks of new materials, are creating a window of opportunity for an emerging variety of next-generation non-volatile memory technologies.  While flash memory goes vertical for  higher densities, resistive RAM and spin-transfer magnetic RAM  technologies are moving towards commercial manufacture for  initial applications in niches that demand a different mix of speed,  power and endurance than  flash or SRAM. This article delves into some of the topics that will be addressed at SEMICON West 2015.

Micron: Memory Needs to go Vertical

“Memory is going through a transformation, making it an exciting time to be in the sector, with both emerging opportunities and new challenges,” notes Naga Chandrasekaran, Micron Technology VP of process R&D, who will keynote the next-generation memory program at SEMICON West 2015.  As new applications in the connected world drive demand for increased storage, bandwidth, and smart memory, and as conventional planar memory scaling faces more challenges, memory suppliers across the industry face a transformation, requiring new emerging memory types and a transition from planar to vertical technology.

“Memory needs to go vertical to meet growing demands placed on performance, and that means a new set of process and equipment requirements,” says Chandrasekaran.  Scaling the vertical 3DNAND structures is no longer limited by the lithography, but instead is driven by the capability of the etch, film and characterization processes.  “Metrology and structure/defect characterization is a holdup for the entire sector, which is slowing down the cycle time for development,” he notes. “In addition, there are challenges in materials, structural scaling, equipment technology, and manufacturability on the new roadmap that need to be resolved.”

Everspin Targets ST-RAM on GLOBALFOUNDRIES’ 40nm 300mm Process in a Year

Everspin Technologies’ recently introduced 64Mb spin transfer torque MRAM makes a big jump in density over the company’s earlier 16Mb device, as switching the magnetization by a current of electrons of aligned spin allows much better selectivity than applying a magnetic field.  Manufacturing these spin-transfer devices has traditionally been a challenge, but the company claims it sees a clear roadmap to continue to increase the density. “We’re squeezing a 64Mb device on 90nm silicon out of the quarter-micron process equipment in our fab,” says VP of manufacturing Sanjeev Aggarwal, who will give an update on the technology at SEMICON West.  The company is in the process of transferring the technology to a 40nm process on 300mm wafers at partner GLOBALFOUNDRIES in the next year, to significantly reduce the cell size and spacing.

Aggarwal notes that the layers in the magnetic stack of the spin-transfer torque device (ST RAM) are similar in thickness to those of the earlier magnetic-field switched MRAM devices, which have already shipped some  50 million units. In the 28nm version of the ST-RAM, targeted for a couple of years out, the company plans to switch from an in-plane to a perpendicular structure, which will significantly improve efficiency to cut power consumption by an order of magnitude, though the material stack and processing will remain very similar.

Current deposition tools can provide the layer uniformity required for the many ultrathin layers of these magnetic stacks, and etching technology being developed with a vendor for cleanly removing these non-volatile magnetic material looks promising for 40nm, says Aggarwal. Key is the company’s IP for depositing the tunnel barrier MgO and for stopping the etch uniformly on the tunnel barrier when etching the magnetic stack. “These deposition and etch technologies should extend to 1Gb without much change, though at 16Gb we may need something new,” he adds. “In the next several years we will need help from vendors on better ways to clean up the etch residue, such as by ion milling after RIE, or encapsulating the stack to protect it before the next round of etching.”

Demand for the 64Mb ST-RAM is coming from buffer storage applications, such as high-end enterprise-class solid state drives, where an array of the fast-writing, non-volatile chips holds the data until it can be more permanently filed and stored, and where the high volumes of data require better endurance than flash,  reports Terry Hulett,  Evergreen VP Systems Engineering and GM Storage Solutions.  “As our products increase in density, we expect to serve the same function for bigger storage systems, like a whole rack of solid state drives,” he projects. The company also targets applications for potential power savings for the instant-on persistent memory, such as powering off the display buffer between every refresh cycles for mobile devices, or shutting down the server between operations.

Both Sanjeev Aggarwal (Everspin) and Naga Chandrasekaran (Micron Technology) will update SEMICON West attendees on the state of these emerging memory technologies in a TechXPOT.   In addition, Wei D. Lu (Crossbar), Robert Patti (Tezzaron), and Jim Handy (Objective Analysis) will provide analysis and updates at the July 14 event in San Francisco:

Crossbar Aims for Embedded ReRAM IP Blocks from Foundry by End of Year

ReRAM suppliers, meanwhile, argue that their technology potentially offers better prospects for scaling and lower costs than either flash or spin-based MRAM, although it is still a ways from a commercial volume process.   Crossbar Co-founder and chief scientist Wei Lu, who will also speak at SEMICON West, says the company plans to deliver its ReRAM technology to strategic partners as an IP block for embedded non-volatile memory on logic chips from a leading-edge manufacturing foundry by the end of the year.  The company’s approach stores data by changing the resistance by forming a conductive metallic bridge through a resistive layer of amorphous silicon sandwiched between two electrode layers.

Lu says the devices are being made with two-mask steps on top of the CMOS transistors in a leading foundry.  Key to improving performance to commercial levels and achieving very dense crossbar arrays, he notes, is the addition of a high speed selector device on top of the memory layer.  This layer blocks unwanted sneak currents at low voltages and turns on at the threshold level to enable formation of the conduction bridge. “It’s like a volatile RAM stacked on top of the ReRAM, with nanosecond recovery time,” he explains. “This brings the on/off selectivity up to 108.”

Initial target market is chip makers who want to embed nonvolatile memory directly in the logic fab, for low-power applications like the IoT, with faster speed and higher endurance than flash.  But ultimately the company targets the bigger market of stand-alone enterprise data storage with lower read and write latencies.  “We expect to offer Gigabit-level density at faster speed than NAND flash by around 2017,” claims Lu.  He figures ReRAM and STT RAM will both find their place in the more diverse memory market of the future, with SST RAM offering better endurance, and ReRAM offering higher density and lower cost.

Tezzaron Reports High ReRAM Yields from Repair and Remapping through Multilayer Stack

Tezzaron Semiconductor takes a different approach to ReRAM, storing data by moving oxygen vacancies instead of metal ions across the thin layers to change resistance.  CTO Robert Patti, another SEMICON West speaker, credits the Tezzaron fab’s ALD technology for the tight control of layer uniformity required to build its 16-tiers of ReRAM cells on top of a CMOS transistor tier from another foundry.  Controlling the chemistry of the layering and the reaction is a challenge, but the tiers allow dynamic repair and remapping of defective cells, which Patti claims can enable yields of up to 98%.  “The possibility to repair across the vertical structure makes defect density less of an issue, and lets us deal with materials and processes that are less mature,” he notes.

Patti says his company’s aerospace/military customers, who need a non-volatile option with better endurance than flash memory, will likely move to ReRAM within a couple of years.  Server makers are also starting to look at the potential for adding a new intermediate level of memory, between the solid state disk and the DRAM, which could potentially significantly improve server performance in analyzing big data by holding big chunks of data for faster access at lower power. It might also reduce system-level costs, although it will require changes in operating system architecture to use it effectively, and sophisticated programming algorithms to manage the memory to limit wear.  Demands on the intermediate storage memory should be limited enough that the ReRAM target endurance of 109 cycles should be sufficient, though it remains lower than DRAM’s 1015.  If ReRAM endurance reaches 1012 cycles, the nonvolatile, instant-on memory could become a viable replacement for mobile memory, Patti suggests.

“Vertical NAND is appealing because it’s more familiar, which has probably delayed interest in ReRAM.  But ReRAM has a smaller cell size so may ultimately be easier to scale and more cost effective,” argues Patti.

Costs Remain the Challenge

“The only thing that ultimately matters in memory is cost,” argues Objective Analysis analyst Jim Handy, another speaker, pointing out that the target aerospace and enterprise storage applications remain small markets, and volumes are not high enough yet to build up deep understanding of the new materials used, so there will be bumps in the road to come.  But as costs come down as MRAM and ReRAM scale to higher densities, he expects them to gradually take over more mainstream applications, starting with the highest cost memories, so first SRAM (especially SRAM with battery backup), then NOR flash, DRAM and finally NAND flash — perhaps by ~2023.  “We have been predicting that 2017 is the earliest we’ll see significant penetration of 3D NAND into the planar NAND market,” he notes. “And now that some suppliers are saying it will be 2017, it makes me think it may be longer.”

On July 14, all of these industry leaders will present at SEMICON West at the emerging memory technologies TechXPOT (www.semiconwest.org/node/13781). Register now and save $100 off registration.

Worldwide silicon wafer area shipments increased during the first quarter 2015 when compared to fourth quarter 2014 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,637 million square inches during the most recent quarter, a 3.4 percent increase from the 2,550 million square inches shipped during the previous quarter, resulting in a new quarterly volume shipment record. New quarterly total area shipments are 11.6 percent higher than first quarter 2014 shipments.

“Total silicon shipment volumes for the first quarter of this year surpassed the record high reached in the third quarter of last year,” said Ginji Yada, chairman of SEMI SMG and general manager, International Sales & Marketing Department of SUMCO Corporation. “Silicon shipments for the most recent quarter benefited from the strong market momentum the semiconductor market enjoyed last year.”

Quarterly Silicon Area Shipment Trends

Millions of Square Inches

Q1 2014

Q3 2014

Q4 2014

Q1 2015
Total

2,363

2,597

2,550

2,637

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers, epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C.   For more information, visit www.semi.org.

Applied Materials, Inc. today announced its Applied Endura Cirrus  HTX PVD system with breakthrough technology for patterning copper interconnects at 10nm and beyond. As chip features continue to shrink, innovations in hardmask are required to preserve the pattern integrity of tightly packed, tiny interconnect structures.With the introduction of this technology, Applied enables scaling of the TiN metal hardmask – the industry’s material of choice – to meet the patterning needs of copper interconnects in advanced microchips.

“Precision engineering of metal hardmask films is key to addressing the patterning challenges for advanced interconnects,” said Dr. Sundar Ramamurthy, vice president and general manager of Applied’s Metal Deposition Products business unit. “The Cirrus HTX TiN product represents Applied’s decades of expertise in applying PVD technology for engineering TiN film properties. Incorporating our unique VHF-based technology offers customers the flexibility of tuning stress in TiN films from compressive to tensile to overcome their specific integration challenges.”

Today’s advanced microchips can pack 20 kilometers of copper wiring in a 100 square millimeter area, stacked in 10 layers with up to 10 billion vias or vertical connections between layers. The role of the metal hardmask is to preserve the integrity of these patterned lines and vias in soft ULK dielectrics. However, with scaling, the compressive stress from conventional TiN hardmask layers can cause the narrow lines patterned in ULK films to deform or collapse. The tunable Cirrus HTX TiN hardmask with high etch selectivity delivers superior CD line width control and via overlay alignment resulting in yield improvement.

This breakthrough in TiN hardmask is made possible by precision materials engineering at the wafer level to produce a high density, low-stress film. Combining exceptional film thickness uniformity with low defectivity on a proven Endura platform, the Cirrus HTX system addresses the stringent high volume manufacturing needs of patterning multiple interconnect layers.

Applied Materials, Inc. is a developer precision materials engineering solutions for the semiconductor, flat panel display and solar photovoltaic industries.

Researchers at Lehigh University have identified for the first time that a performance gain in the electrical conductivity of random metal nanowire networks can be achieved by slightly restricting nanowire orientation. The most surprising result of the study is that heavily ordered configurations do not outperform configurations with some degree of randomness; randomness in the case of metal nanowire orientations acts to increase conductivity.

The study, Conductivity of Nanowire Arrays under Random and Ordered Orientation Configurations, is published in the current issue of Nature‘s journal Scientific Reports. The research was carried out by Nelson Tansu, Daniel E. ’39 and Patricia M. Smith Endowed Chair Professor in Lehigh’s Center for Photonics and Nanoelectronics and Department of Electrical and Computer Engineering, and lead author Milind Jagota, a Bethlehem-area high school student.

Transparent conductors are needed widely for flat screen displays, touch screens, solar cells, and light-emitting diodes, among many other technologies. Currently, Indium Tin Oxide (ITO) is the most widely used material for transparent conductors due to its high conductivity and high transparency. However, ITO-based technology has several issues. The material is scarce, expensive to manufacture and brittle, a particularly undesirable characteristic for anything being used in this modern age of flexible electronics.

Researchers searching for a replacement for ITO are increasingly employing random networks of metal nanowires to match ITO in both transparency and conductivity. Metal nanowire-based technologies display better flexibility and are more compatible with manufacturing processes than ITO films. The technology, however, is still in an early phase of development and performance must be improved. Current research is focused on the effect of rod orientation on conductivity of networks to improve performance.

In this work, Lehigh researchers developed a computational model for simulation of metal nanowire networks, which should speed the process towards idealizing the configuration of nanowires. The model predicts existing experimental results and previously published computational results.

The researchers then used this model to extract results for the first time on how conductivity of random metal nanowire networks is affected by different orientation restrictions of varying randomness. Two different orientation configurations are reported.

In the first, a uniform distribution of orientations over the range (?θ, θ) with respect to a horizontal line is used. In the second, a distribution of orientations over the range [?θ] _ [θ] is used, also with respect to a horizontal line. In each case θ is gradually decreased from 90° to 0°. Conductivity is measured both in directions parallel and perpendicular to alignment.

Researchers found that a significant improvement in conductivity parallel to direction of alignment can be obtained by slightly restricting orientation of the uniform distribution. This improvement, however, comes at the expense of a larger drop in perpendicular conductivity. The general form of these results matches that demonstrated by researchers experimenting with carbon nanotube films. Surprisingly, it was found that the highly ordered second case is unable to outperform isotropic networks for any value of θ; thus demonstrating that continuous orientation configurations with some degree of randomness are preferable to highly ordered configurations.

Prior research in this field has studied the effects of orientation on conductivity of 3D carbon nanotube composites, finding that a slight degree of alignment improves conductivity. Computational models have been used to study how percolation probability of 2D random rod dispersions is affected by rod orientation. Others have developed a more sophisticated computational model capable of calculating conductivity of 3D rod dispersions, again finding that a slight degree of axial alignment improves conductivity.

“Metal nanowire networks show great potential for application in various forms of technology,” said Jagota. “This computational model, which has proven itself accurate through its good fit with previously published data, has demonstrated quantitatively how different orientation configurations can impact conductivity of metal nanowire networks.”

“Restriction of orientation can improve conductivity in a single direction by significant amounts, which can be relevant in a variety of technologies where current flow is only required in one direction,” said Tansu. “Surprisingly, heavily controlled orientation configurations do not exhibit superior conductivity; some degree of randomness in orientation in fact acts to improve conductivity of the networks. This approach may have tremendous impacts on improving current spreading in optoelectronics devices, specifically on deep ultraviolet emitter with poor p-type contact layer.”

By Douglas G. Sutherland and David W. Price

Author’s Note: This is the sixth in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article in this series introduces one of the 10 fundamental truths and highlights their implications. Within this article we will use the term inspection to imply either defect inspection or a parametric measurement such as film thickness or critical dimension (CD).

In previous installments we discussed capability, sampling, missed excursions, risk management and variability. Although all of these topics involve an element of time, in this paper we will discuss the importance of timeliness in more detail.

The sixth fundamental truth of process control for the semiconductor IC industry is:

Time is the Enemy of Profitability

There are three main phases to semiconductor manufacturing: research and development (R&D), ramp, and high volume manufacturing (HVM). All of them are expensive and time is a critical element in all three phases.

From a cash-flow perspective, R&D is the most difficult phase: the fab is spending hundreds of thousands of dollars every day on man power and capital equipment with no revenue from the newly developed products to offset that expense. In the ramp phase the fab starts to generate some revenue early on, but the yield and volume are still too low to offset the production costs. Furthermore, this revenue doesn’t even begin to offset the cost of R&D. It is usually not until the early stages of HVM that the fab has sufficient wafer starts and sufficient yield to start recovering the costs of the first two phases and begin making a profit. Figure 1 below shows the cumulative cash flow for the entire process.

Figure 1. The cumulative cash-flow as a function of time. In the R&D phase the cash-flow is negative but the slope of the curve turns positive in the ramp phase as revenues begin to build. The total costs do not turn positive until the beginning of high-volume manufacturing.

Figure 1. The cumulative cash-flow as a function of time. In the R&D phase the cash-flow is negative but the slope of the curve turns positive in the ramp phase as revenues begin to build. The total costs do not turn positive until the beginning of high-volume manufacturing.

What makes all of this even more challenging is that all the while, the prices paid for these new devices are falling. The time required from initial design to when the first chips reach the market is a critical parameter in the fab’s profitability. Figure 2 shows the actual decay curve for the average selling price (ASP) of memory chips from inception to maturity.

Figure 2. Typical price decline curve for memory products in the first year after product introduction. Similar trends can be seen for other devices types.

Figure 2. Typical price decline curve for memory products in the first year after product introduction. Similar trends can be seen for other devices types.

Consequently, while the fab is bleeding money on R&D, their ability to recoup those expenses is dwindling as the ASP steadily declines. Anything that can shorten the R&D and ramp phases shortens the time-to-market and allows fabs to realize the higher ASP shown on the left hand side of Figure 2.

From Figures 1 and 2 it is clear that even small delays in completing the R&D or ramp phases can make the difference between a fab that is wildly profitable and one that struggles just to break even. Those organizations that are the first to bring the latest technology to market reap the majority of the reward. This gives them a huge head start—in terms of both time and money—in the development of the next technology node and the whole cycle then repeats itself.

Process control is like a window that allows you to see what is happening at various stages of the manufacturing cycle. Without this, the entire exercise from R&D to HVM would be like trying to build a watch while wearing a blindfold. This analogy is not as far-fetched as it may seem. The features of integrated circuits are far too small to be seen and even when inspections are made, they are usually only done on a small percentage of the total wafers produced. For parametric measurements (films, CD and overlay) measurements are performed only on an infinitesimal percentage of the total transistors on each of the selected wafers. For the vast majority of time, the fab manager truly is blind. Parametric measurements and defect inspection are brief moments when ‘the watch maker’ can take off the blindfold, see the fruits of their labor and make whatever corrections may be required.

As manufacturing processes become more complex with multiple patterning, pitch splitting and other advanced patterning techniques, the risk of not yielding in a timely fashion is higher than ever. Having more process control steps early in the R&D and ramp phases increases the number of windows through which you can see how the process is performing. Investing in the highest quality process control tools improves the quality of these windows. A window that distorts the view—an inspection tool with poor capture rate or a parametric tool with poor accuracy—may be worse than no window at all because it wastes time and may provide misleading data. An effective process control strategy, consisting of the right tools, the right recipes and the right sampling all at the right steps, can significantly reduce the R&D and ramp times.

On a per wafer basis, the amount of process control should be highest in the R&D phase when the yield is near zero and there are more problems to catch and correct. Resolving a single rate-limiting issue in this phase with two fewer cycles of learning—approximately one month—can pay for a significant portion of the total budget spent on process control.

After R&D, the ramp phase is the next most important stage requiring focused attention with very high sampling rates. It’s imperative that the yield be increased to profitable levels as quickly as possible and you can’t do this while blindfolded.

Finally, in the HVM phase an effective process control strategy minimizes risk by discovering yield limiting problems (excursions) in a timely manner.

It’s all about time, as time is money. 

References:

1)     Process Watch: You Can’t Fix What You Can’t Find, Solid State Technology, July 2014

2)     Process Watch: Sampling Matters, Semiconductor Manufacturing and Design, September 2014

3)     Process Watch: The Most Expensive Defect, Solid State Technology, December 2014

4)     Process Watch: Fab Managers Don’t Like Surprises, Solid State Technology, December 2014

5)     Process Watch: Know Your Enemy, Solid State Technology, March 2015 

About the authors:

Dr. David W. Price is a Senior Director at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 10 years, Dr. Price and Dr. Sutherland have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

 

The 61st annual IEEE International Electron Devices Meeting (IEDM) has issued a Call for Papers seeking the world’s best original work in all areas of microelectronics research and development. The paper submission deadline is Monday, June 22, 2015 at 23:59 p.m. Pacific Time.

Overall, the 2015 IEDM is seeking increased participation in the areas of ‘Beyond CMOS’ devices, flexible devices, neuromorphic computing, power devices, sensors for the Internet of Things (IoT) and variation/reliability.

In addition, Special Focus Sessions will be held on the following topics: neural-inspired architectures; 2D materials and applications; flexible electronics and applications; power devices and reliability on non-native substrates; and silicon-based nanodevices for detection of biomolecules.

The 2015 IEDM will take place at the Washington, DC Hilton Hotel from December 7-9, 2015, preceded by a collection of 90-minute afternoon Tutorial sessions on Saturday, Dec. 5, and a full day of Short Courses on Sunday, Dec. 6. On Wednesday the conference will continue the successful Entrepreneurs Luncheon sponsored by IEDM and EDS Women in Engineering.

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics from industry, academia and government gather to participate in a technical program of more than 220 presentations, along with a special Luncheon Presentation on Tuesday, Dec. 8 and a variety of panels, special sessions, Short Courses, IEEE/EDS award presentations and other events spotlighting more leading work in more areas of the field than any other conference.

Papers in the following areas are encouraged:
– Circuit and Device Interaction
– Characterization, Reliability and Yield
– Display and Imaging Systems
– Memory Technology
– Modeling and Simulation
– Nano Device Technology
– Power and Compound Semiconductor Devices
– Process and Manufacturing Technology
– Sensors, MEMS and BioMEMS

BY GREG SHUTTLEWORTH, Global Product Manager at LINDE ELECTRONICS

The market expectations of modern electronics technology are changing the landscape in terms of performance and, in particular, power consumption, and new innovations are putting unprecedented demands on semiconductor devices. Internet of Things devices, for example, largely depend on a range of different sensors, and will require new architectures to handle the unprecedented levels of data and operations running through their slight form factors.

The continued shrinkage of semiconductor dimensions and the matching decreases in microchip size have corresponded to the principles of Moore’s Law with an uncanny reliability since the idea’s coining in 1965. However, the curtain is now closing on the era of predictable / conventional size reduction due to physical and material limitations.

Thus, in order to continue to deliver increased performance at lower costs and with a smaller footprint, different approaches are being explored. Companies can already combine multiple functions on a single chip–memory and logic devices, for example–or an Internet of Things device running multiple types of sensor through a single chip.

We have always known that we’d reach a point where conventional shrinking of semiconductor dimensions would begin to lose its effect, but now we are starting to tackle it head on. A leading U.S. semiconductor manufacturer got the ball rolling with their FinFET (or tri–gate) design in 2012 with its 3D transistors allowing designs that minimize current leakage; other companies look set to bring their own 3D chips to market.

At the same time, there’s a great deal of experimentation with a range of other approaches to semiconductor redesign. Memory device manufacturers, for instance, are looking to stack memory cells vertically on top of each other in order to make the most of a microchip’s limited space. Others, meanwhile, are examining the materials in the hope of using new, more efficient silicon–like materials in their chips.

Regardless of the approach taken, however, this step change in microchip creation means new material demands from chip makers and new manufacturing techniques to go with them.

The semiconductor industry has traditionally had to add new materials and process techniques to enhance the performance of the basic silicon building blocks with tungsten plugs, copper wiring / CMP, high–k metal gates, for example. Now, however, it is beginning to become impossible to extend conventional materials to meet the performance requirements. Germanium is already added to Si to introduce strain, but its high electron mobility means Germanium is also likely to become the material of the Fin itself and will be complemented by a corresponding Fin made of III–V material, in effect integrating three semiconductor materials into a single device.

Further innovation is required in the areas of lithography and etch. This is due to the delay in production suitability of the EUV lithography system proposed to print the very fine structures required for future technology nodes. Complex multi-patterning schemes using conventional lithography are already underway to compensate for this technology delay, requiring the use of carbon hard masks and the introduction of gases such as acetylene, propylene and carbonyl sulphide to the semiconductor fab. Printing the features is only half of the challenge; the structures also need to be etched. The introduction of new materials always presents some etch challenges as all materials etch at slightly different rates and the move to 3D structures, where very deep and narrow features need to be defined through a stack of different materials, will be a particularly difficult challenge to meet.

The microchip industry has continuously evolved to deliver amazing technological advances, but we are now seeing the start of a revolution in microchip design and manufacturing. The revolution will be slow but steady. Such is the pattern of the microchip industry, but it will need a succession of new materials at the ready, and, at Linde, we’re prepared to make sure the innovators have everything they need.

Quantum dots are finally ready for prime time and will exceed traditional phosphor revenue by 2020 by allowing LCD to compete with OLED in the race for the next display generation.
Yole Développement (Yole), the “More than Moore” market research and strategy consulting company releases a LED downconverters technology & market report, entitled “Phosphors & Quantum Dots 2015: LED Downconverters for Lighting & Displays”. Under this new report, the company proposes a deep review of the industry, especially the impact of the quantum dots development on the display and traditional phosphors industry. Are the quantum dots a real competitor of OLEDs technology?

After the lukewarm reception of 3D and 4K, the display industry needs a new and disruptive experience improvement to bring consumers back to the store. Image quality perception increases significantly when color gamut and dynamic contrast ratio are improved. Leading movie studios, content providers, distributors and display makers gathered and formed the “UHD Alliance” to promote those features.

“OLED was believed to be the technology of choice for this next generation of displays. But production challenges have delayed the availability of affordable OLED TVs. LCD TVs with LED backlights based on quantum dots downconverters can deliver performance close to, or even better than OLED in some respects, and at a lower cost,” said Dr. Eric Virey, Senior Analyst, LEDs at Yole.

Until OLEDs are ready, QD-LCD have a unique window of opportunity to try to close enough of the performance gap that the majority of the consumers won’t perceive the difference between the two technologies and price would become the driving factor in the purchasing decision. Under this scenario, QD-LCD could establish itself as the dominant technology while OLED would be cornered into the high end of the market. OLED potentially offers more opportunities for differentiation but proponents need to invest massively and still have to resolve manufacturing yield issues. For tier-2 LCD panel makers who can’t invest in OLED, QDs offer an opportunity to boost LCD performance without additional CAPEX on their fabs. At the 2015 CES, 7 leading TV OEMs including Samsung and LG showed QD-LCD TVs.

With tunable and narrowband emissions, QDs offer unique design flexibility. But more is needed to enable massive adoption, including the development of further improved Cd-free compositions.

And traditional phosphors haven’t said their last word. If PFS could further improve in term of stability and decay time and a narrow-band green composition was to emerge, traditional phosphors could also be part of the battle against OLED.

“… LCD TVs with LED backlights based on quantum dots downconverters can deliver performance close to, or even better than OLED in some respects, and at a lower cost.” said Dr. E. Virey, Yole.

Yole’s analysis, “Phosphors & Quantum Dots 2015: LED Downconverters for Lighting & Displays”, presents an overview of the quantum dot LED market for display and lighting applications including quantum dot manufacturing, benefits and drawbacks, quantum dots LCD versus OLED and detailed market forecast.