Category Archives: Displays

Organic light emitting diodes (OLEDs), which are made from carbon-containing materials, have the potential to revolutionize future display technologies, making low-power displays so thin they’ll wrap or fold around other structures, for instance.

Conventional LCD displays must be backlit by either fluorescent light bulbs or conventional LEDs whereas OLEDs don’t require back lighting. An even greater technological breakthrough will be OLED-based laser diodes, and researchers have long dreamed of building organic lasers, but they have been hindered by the organic materials’ tendency to operate inefficiently at the high currents required for lasing.

Now a new study from a team of researchers in California and Japan shows that OLEDs made with finely patterned structures can produce bright, low-power light sources, a key step toward making organic lasers. The results are reported in a paper appearing this week on the cover of the journal Applied Physics Letters, from AIP Publishing.

The key finding, the researchers say, is to confine charge transport and recombination to nanoscale areas, which extends electroluminescent efficiency roll off the current density at which the efficiency of the OLEDs dramatically decreases — by almost two orders of magnitude. The new device structures do this by suppressing heating and preventing charge recombination.

“An important effect of suppressing roll-off is an increase in the efficiency of devices at high brightness,” said Chihaya Adachi of Kyushu University, who is a co-author of the paper. “This results in lower power to obtain the same brightness.”

“For years scientists working in organic semiconductors have dreamed of making electrically-driven organic lasers,” said Thuc-Quyen Nguyen of the University of California, Santa Barbara, another co-author. “Lasers operate in extreme conditions with electric currents that are significantly higher than those used in common displays and lighting. At these high currents, energy loss processes become stronger and make lasing difficult.

“We see this work, which reduces some loss processes, as one step on the road toward realizing organic lasers,” Nguyen added.

How OLEDs Work

OLEDs operate through the interaction of electrons and holes. “As a simple visualization,” Adachi said, “one can think of an organic semiconductor as a subway train with someone sitting in every seat. The seats represent molecules and the people represent energetic particles, i.e., electrons. When people board the train from one end, they have extra energy and want to go to the relaxed state of sitting. As people board, some of the seated people rise and exit the train at the other end leaving empty seats, or ‘holes,’ for the standing people to fill. When a standing person sits, the person goes to a relaxed state and releases energy. In the case of OLEDs, the person releases the energy as light.”

Production of OLED-based lasers requires current densities of thousands of amperes per square centimeter (kA/cm2), but until now, current densities have been limited by heating. “At high current densities, brightness is limited by annihilation processes,” Adachi said. “Think of large numbers of people on the train colliding into each other and losing energy in ways other than by sitting and releasing light.”

In previous work, Adachi and colleagues showed OLED performance at current densities over 1 kA/cm2 but without the necessary efficiency required for lasers and bright lighting. In their current paper, they show that the efficiency problem can be solved by using electron-beam lithography to produce finely-patterned OLED structures. The small device area supports charge density injection of 2.8 kA/cm2 while maintaining 100 times higher luminescent efficiency than previously observed. “In our device structure, we have effectively confined the entrance and exit to the middle of the train. People diffuse to the two less crowded ends of the train and reduce collisions and annihilation.”

Cypress Semiconductor Corp., in conjunction with its strategic partner IDEX ASA, today introduced a fingerprint reader solution designed to bring reliable, easy-to-use user authentication to smartphones, tablets, wearables and other mobile devices. The TrueTouch Fingerprint Reader uses proprietary sensing circuitry and a unique touch sensor design to provide best-in-class fingerprint image quality and pattern matching accuracy—improving security and delivering a superior user experience. The flexible solution enables designers to create custom home buttons with specialized shapes and sizes or to integrate the sensor into any mobile device’s industrial design or home button.

Consumers have increasingly embraced fingerprint readers as an alternative to keying in complex usernames, PINs and passwords. Mobile device OEMs and companies that sell via the Internet have gravitated toward the technology as the most secure way to validate a user’s identity. Demand for fingerprint readers in mobile devices is forecast to grow at a compound annual rate of 47 percent through 2019, reaching annual shipments of more than 700 million units.

Cypress will showcase its TrueTouch Fingerprint Reader, along with its extensive portfolio of capacitive touchscreen and touch-sensing solutions, at Mobile World Congress 2015 from March 2-5 in Hall 2, Stand 2C26MR at Fira Gran Via in Barcelona.

TrueTouch Fingerprint Reader block diagram

“The barriers to entry are considerable in the emerging market for fingerprint readers, in part because of the highly specialized IP and complete solution that is required to compete,” said T.J. Rodgers, President and CEO of Cypress. “Our relationship with IDEX will enable us to provide our top-tier mobile customers with a globally deployable fingerprint sensing solution, including a sensor, Android drivers and a software stack. With our industry-leading CapSense capacitive touch-sensing controllers, and our TrueTouch touchscreen solutions, Cypress will have an unmatched portfolio for mobile user interfaces.”

“We are extremely pleased with the performance of our new generation touch sensor developed in record time through our partnership with Cypress,” said Dr. Hemant Mardia, CEO of IDEX ASA. “The combination of IDEX’s breakthrough imaging performance, matching algorithm and patented sensor IP with Cypress’s award-winning programmable system-on-chip technology delivers best in class fingerprint matching. This product has been designed based on fundamentally new technology to meet our OEM customers’ demands for usability and security strength from small touch sensors.”

The annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2015) will be held May 3-6 in Saratoga Springs, New York. The conference will feature 37 hours of technical presentations and 90+ speakers covering all aspects of advanced semiconductor manufacturing. This year’s event features a panel discussion on “Semiconductor Manufacturing: Keeping the Silicon Magic Alive,” with panelists from DARPA, GE Global Research, Lam Research and Rochester Institute of Technology.  The event features a tutorial on graphene presented by Dr. Paul L. McEuen, professor of Physics, Cornell University, and a second tutorial, on memory, presented by Dr. Gurtej Sandhu, IEEE Fellow and director of Advanced Technology Development at Micron Technology, Inc.

ASMC 2015 offers keynote talks by Dr. Thomas Caulfield, senior VP and GM of GLOBALFOUNDRIES; Dr. Frances M. Ross of the Nanoscale Materials Analysis Department at T.J. Watson Research Center, IBM Corporation; and Robert Maire, president of Semiconductor Advisors LLC.

ASMC technology tracks and poster presenters will address numerous topics, including:

  • 3D/TSV
  • Advanced Equipment and Materials
  • Advanced Metrology
  • Advanced Patterning/Design for Manufacturing
  • Advanced Process Control (APC)
  • Contamination Free Manufacturing (CFM)
  • Data and Yield Management; Defect Inspection
  • Equipment Reliability and Productivity Enhancement
  • Factory Optimization
  • Yield and Reliability Enhancement

ASMC also holds an interactive poster session and reception, which provides an ideal opportunity for networking between authors and conference attendees. During this session, participants can engage authors in in-depth discussions of a wide range of issues.

ASMC 2015 corporate sponsors include Applied Materials, ChemTrace, CNW, Edwards, KLA-Tencor, NY Loves Nanotech, and MSP.  Technical and supporting sponsors include: Institute of Electrical & Electronics Engineers (IEEE); IEEE Electron Devices Society (EDS); and IEEE Components, Packaging and Manufacturing Technology Society (CPMT); Saratoga Convention & Tourism Board; and Saratoga Economic Development Corporation (SEDC).

Registration for ASMC 2015 is available at www.semi.org/asmc2015.

SmartKem, supplier of the market-leading tru-FLEX semiconductor platform, has announced an extensive collaboration programme with the Centre for Process Innovation (CPI) for the development of pre-production prototypes featuring the SmartKem unique range of semiconductor inks for the manufacture of ultra flexible thin-film transistors (TFT). The three year agreement will see a scaling-up of SmartKem activities; driving customer development programs for the manufacture of unbreakable and foldable displays and electronics.

Headquartered in Wales, SmartKem is a provider of semiconductor inks for the manufacture of truly flexible transistors for flexible displays and electronics. The SmartKem tru-FLEX inks offer, for the first time, transistors with outstanding electrical performance, unparalleled physical flexibility and the chance to manufacture at room temperature onto any surface type.  As such, electronic TFT arrays can be printed at low cost with extremely high throughput, making tru-FLEX technology the leading candidate for the manufacture of new form factor consumer devices such as bendy smartwatch displays and foldable mobile phones.

“This collaboration supports our on-going activity of delivering tru-FLEX to meet market demand,” said Steve Kelly, CEO of SmartKem Ltd. “We have established the potential of the technology and proven its position as a total technology solution over competing TFT materials. Now in conjunction with our customers, we’re moving towards manufacturing pre-production demonstrators. We have a long established track record of development work with CPI since SmartKem was founded in 2009. It has proven invaluable to have access to such a well equipped facility that offers us the ability to validate our technology in a confidential environment. We are very excited to have secured a long term agreement with such a high profile industry partner.”

Nigel Perry, CEO of CPI commented, “at CPI we are committed to providing leaders in the field of flexible electronics, like SmartKem, with a means to develop their technology safe in the knowledge that we are an independent development partner. Having a centralised facility offers customers the ability to develop and test prototypes at our labs and focus on what they do best. Having created such a significant uptake in the market, we are excited to be able to support SmartKem in transferring its landmark tru-FLEX technology platform into their pre-production pipeline; ultimately enabling ultra-flexible display technology.”

In August 2014, SmartKem also announced the receipt of Series A funding from an investment syndicate including BASF Venture Capital, Finance Wales, Octopus Investments and Entrepreneurs Fund. This new industrial partnership with CPI will directly support SmartKem in fast-tracking its customers’ pre-production development with the tru-FLEX technology platform.

The Centre for Process Innovation, based in the UK, is an independent technology innovation centre which forms part of the High Value Manufacturing Catapult. It provides innovators with the tools and manufacturing facilities to develop and prove their technologies and to build prototypes and refine processes with minimal financial risk and complete confidentiality. By testing products and manufacturing processes in the CPI labs and manufacturing pilot lines, companies can validate their technology prior to transfer to customer pilot lines and full scale production.

North America-based manufacturers of semiconductor equipment posted $1.31 billion in orders worldwide in January 2015 (three-month average basis) and a book-to-bill ratio of 1.03, according to the January EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.03 means that $103 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in January 2015 was $1.31 billion. The bookings figure is 4.9 percent lower than the final December 2014 level of $1.38 billion, and is 2.6 percent higher than the January 2014 order level of $1.28 billion.

The three-month average of worldwide billings in January 2015 was $1.28 billion. The billings figure is 8.6 percent lower than the final December 2014 level of $1.40 billion, and is 3.5 percent higher than the January 2014 billings level of $1.23 billion.

“2014 was a strong growth year for the semiconductor equipment industry, and both bookings and billings at the start of this year are comparable to the early 2014 figures,” said SEMI president and CEO Denny McGuirk. “Given the positive outlook for the semiconductor industry in 2015 and based on current capex announcements, we expect the equipment market to continue to grow this year.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill

August 2014 

$1,293.4

$1,346.1

1.04

September 2014 

$1,256.5

$1,186.2

0.94

October 2014 

$1,184.2

$1,102.3

0.93

November 2014 

$1,189.4

$1,216.8

1.02

December 2014 (final)

$1,395.9

$1,381.5

0.99

January 2015 (prelim)

$1,276.3

$1,313.6

1.03

Source: SEMI, February 2015

Even as smartphone panel resolution continues to rise, and as display sizes continue to grow, panel manufacturers are facing pressure to reduce prices. According to the Quarterly Mobile Phone Display Shipment and Forecast Report from IHS, a global source of critical information and insight, total mobile phone display shipments are estimated to reach a new record high of 2 billion units in 2014. Average smartphone display prices declined nearly 14 percent year-over-year (YoY) from $22 per module in 2013 to $19 in 2014. IHS Technology forecasts another double-digit fall for smartphone display prices in 2015, resulting in a blended ASP of about $17.

“While smartphone display resolution and sizes reach new milestones, panel makers are still being challenged to reduce display module prices,” said Terry Yu, analyst for small and medium displays and display technologies for IHS Technology, formerly with DisplaySearch. “Shipment and manufacturing of panels using various display technologies like a-Si, Oxide, LTPS and AMOLED continues to rise, while pricing continues to decline. The sharpest smartphone average panel price declines occurred in 2014, and this trend of double-digit declines is expected to continue in 2015.”

Panel makers (like Tianma, BOE, InfoVision, and Japan Display Inc. (JDI) via their subsidiary TDI) are all promoting their products to Chinese smartphone makers with aggressive pricing strategies. Chinese smartphone makers are agile enough to use economies of scale and their strong market position to better negotiate display prices. On the supply side, LTPS LCD manufacturing capacity is increasing in all regions. Taiwanese panel suppliers are aggressively shifting production of smartphone panels to Gen 5 fabs, as well. These factors are adding pressure to reduce prices.

According to the Monthly Smartphone and Tablet PC FPD Pricing Report, 5-inch LTPS TFT LCD FHD (1920×1080) smartphone panels with IPS/FFS LCD technology, experienced a decline of 30 percent YoY, from $30 in December 2013 to $21 in December 2014. “Smartphone ASPs will continue to drop substantially in the first quarter of 2015, which is a traditionally slow season for smartphone display panel purchasing,” Yu said.

ihs smartphone displays

The 5-inch 720 HD (1280×720 pixels) module is the most popular smartphone display size in China, helping the format to gain over 40 percent market share in the market global 5.x-inch space during 2014. “Most brands are promoting low-priced, high-specification models with these displays, especially on e-commerce platforms,” Yu said. “China is the major battlefield for 5-inch smartphone displays. Demand for these displays is very strong, but they face strong competitive price pressure in the set market.”

In China’s open market, prices for 5-inch 720HD panels declined significantly to just under $12 in December 2014. Business agreements aside, market pricing for low-specification 5.x-inch panels is expected to decline to about $11 by March 2015. Prices of some low-grade specifications panels (lower brightness requirement) could decline to below $10 by the same period.

Due to the booming demand for LTPS LCD in China, panel makers are expected to continue expanding their LTPS manufacturing capacities & shipment.

“By the end of 2016, new fab investments by AUO, BOE, China Star, Tianma, and Foxconn will result in at least five Gen 6 LTPS fabs running in China and Taiwan, which may induce more pressure to reduce smartphone ASPs in the future,” Yu said.

Another price-reduction pressure in the smartphone display market comes from aggressive smartphone end-market pricing by Chinese smartphone brands. According to the Monthly Smartphone and Tablet PC FPD Pricing Report, after the introduction of the iPhone 6 Plus with its 5.5-inch FHD display, more Android-based premium models are expected to come equipped with wide-quad high-definition (WQHD) (2560×1440) displays driving FHD models down into the mid-range segment with lower pricing.

On December 23, 2014, Meizu, a rising brand in China, introduced its new “No Blue Note” smartphone, which was equipped with a 5.5-inch FHD display from Taiwan, which sells for just CNY 999 ($161). This model and pricing has been cited by many in the industry as a warning for upcoming price competition in 2015. “Facing ASP pressures, display cost reduction will be the top priority for the panel makers, especially through more effective production yield rate management and improvements in component performance,” Yu said.

Pulsed measurements are defined in Part 1, and common pulsed measurement challenges are discussed in Part 2.

By DAVID WYBAN, Keithley Instruments, a Tektronix Company, Solon, Ohio

Performing a DC measurement starts with applying the test signal (typically a DC voltage), then waiting long enough for all the transients in the DUT and the test system to settle out. The measurements themselves are typically performed using a sigma-delta or integrating-type analog-to-digital converter (ADC). The conversion takes place over one or more power line cycles to eliminate noise in the measurements due to ambient power line noise in the test environment. Multiple measurements are often averaged to increase accuracy. It can take 100ms or longer to acquire a single reading using DC measurement techniques.

In contrast, pulsed measurements are fast. The test signal is applied only briefly before the signal is returned to some base level. To fit measurements into these short windows, sigma-delta ADCs are run at sub-power-line interval integration times; sometimes, the even faster successive approximation register (SAR) type ADCs are used. Because of these high speeds, readings from pulsed measurements are noisier than readings returned by DC measurements. However, in on-wafer semiconductor testing, pulse testing techniques are essential to prevent device damage or destruction. Wafers have no heat sinking to pull away heat generated by current flow; if DC currents were used, the heat would increase rapidly until the device was destroyed. Pulse testing allows applying test signals for very short periods, avoiding this heat buildup and damage.

Why use pulsed measurements?

The most common reason for using pulsed measurements is to reduce joule heating (i.e., device self-heating). When a test signal is applied to a DUT, the device consumes power and turns it into heat, increasing the device’s temperature. The longer that power is applied, the hotter the device becomes, which affects its electrical characteristics. If a DUT’s temperature can’t be kept constant, it can’t be characterized accurately. However, with pulsed testing, power is only applied to the DUT briefly, minimizing self-heating. Duty cycles of 1 percent or less are recommended to reduce the average power dissipated by the device over time. Pulsed measurements are designed to minimize the power applied to the device so much that its internal temperature rise is nearly zero, so heating will have little or no effect on the measurements.

Because they minimize joule heating, pulsed measurements are widely used in nanotechnology research, such as when characterizing delicate materials and structures like CNT FETs, semiconductor nanowires, graphene-based devices, molecular- based electronics and MEMs structures. The heat produced with traditional DC measurement techniques could easily alter or destroy them.

To survive high levels of continuous DC power, devices like MOSFETs and IGBTs require packaging with a solid metal backing and even heat-sinking. However, during the early stages of device development, packaging these experimental devices would be much too costly and time consuming, so early testing is performed at the wafer level. Because pulsed testing minimizes the power applied to a device, it allows for complete characterization of these devices on the probe station, reducing the cost of test.

The reduction in joule heating that pulsed testing allows also simplifies the process of characterizing devices at varying temperatures. Semiconductor devices are typically so small that it is impossible
to measure their temperature directly with a probe. With pulsed measurements, however, the self- heating of the device can be made so insignificant that its internal temperature can be assumed to be equal to the surrounding ambient temperature. To characterize the device at a specific temperature, simply change the surrounding ambient temperature with a thermal chamber or temperature-controlled heat sink. Once the device has reached thermal equilibrium at the new ambient temperature, repeat the pulsed measurements to characterize the device at the new temperature.

Pulsed measurements are also useful for extending instruments’ operating boundaries. A growing number of power semiconductor devices are capable of operating at 100A or higher, but building an instrument capable of sourcing this much DC current would be prohibitive. However, when delivering pulse mode power, these high power outputs are only for very short intervals, which can be done by storing the required energy from a smaller power supply within capacitors and delivering it all in one short burst. This allows instruments like the Model 2651A High Power SourceMeter SMU instrument to combine sourcing up to 50A with precision current and voltage measurements.

Pulsed I-V vs. transient measurements

Pulsed measurements come in two forms, pulsed I-V and transient. Pulsed I-V (FIGURE 1) is a technique for gathering DC-like current vs. voltage curves using pulses rather than DC signals. In the pulsed I-V technique, the current and voltage is measured near the end of the flat top of the pulse, before the falling edge. In this technique, the shape of the pulse is extremely important because it determines the quality of the measurement. If the top of the pulse has not settled before this measurement is taken, the resulting reading will be noisy and or incorrect. Sigma-delta or integrating ADCs should be configured to perform their conversion over as much of this flat top as possible to maximize accuracy and reduce measurement noise.

FIGURE 1. Pulse I-V technique.

FIGURE 1. Pulse I-V technique.

Two techniques can improve the accuracy of pulsed I-V measurements. If the width of the pulse and measurement speed permit, multiple measurements made during the flat portion of the pulse can be averaged together to create a “spot mean” measurement. This technique is commonly employed with instruments that use high speed Summation Approximation Register (SAR) ADCs, which perform conversions quickly, often at rates of 1μs per sample or faster, thereby sacrificing resolution for speed. At these high speeds, many samples can be made during the flat portion of the pulse. Averaging as many samples as possible enhances the resolution of the measurements and reduces noise. Many instruments have averaging filters that can be used to produce a single reading. If even greater accuracy is required, the measurement can be repeated over several pulses and the readings averaged to get a single reading. To obtain valid results using this method, the individual pulsed measurements should be made in quick succession to avoid variations in the readings due to changes in temperature or humidity.

Transient pulsed measurements (FIGURE 2) are performed by sampling the signal at high speed to create a signal vs. time waveform. An oscilloscope is often used for these measurements but they can also be made with traditional DC instruments by running the ADCs at high speed. Some DC instruments even include high-speed SAR type ADCs for performing transient pulsed measurements. Transient measurements are useful for investigating device behaviors like self-heating and charge trapping.

FIGURE 2. Transient pulse measurements.

FIGURE 2. Transient pulse measurements.

Instrumentation options

The simplest pulse measurement instrumentation option is a pulse generator to source the pulse combined with an oscilloscope to measure the pulse (FIGURE 3). Voltage measurements can be made by connecting a probe from the scope directly to the DUT; current measurements can be made by connecting a current probe around one of the DUT test leads. If a current probe is unavailable, a precision shunt resistor can be placed in series with the device and the voltage across the shunt measured with a standard probe, then converted to current using a math function in the scope. This simple setup offers a variety of advantages. Pulse generators provide full control over pulse width, pulse period, rise time and fall time. They are capable of pulse widths as narrow as 10 nanoseconds and rise and fall times as short as 2-3 nanoseconds. Oscilloscopes are ideal for transient pulse measurements because of their ability to sample the signal at very high speeds.

FIGURE 3. Pulse measurement using a pulse generator and an oscilloscope. Voltage is measured across the device with a voltage probe and current through the device is measured with a current probe.

FIGURE 3. Pulse measurement using a pulse generator and an oscilloscope. Voltage is measured across the device with a voltage probe and current through the device is measured with a current probe.

Although a simple pulse generator/oscilloscope combination is good for fast transient pulse measurements, it’s not appropriate for all pulse measurement applications. A scope’s measurement resolution is relatively low (8–12 bits). Because scopes are designed to capture waveforms, they’re not well suited for making pulse I-V measurements. Although the built-in pulse measure functions can help with measuring the level of a pulse, this represents only a single point on the I-V curve. Generating a complete curve with this setup would be time consuming, requiring either manual data collection or a lot of programming. Pulse generators are typically limited to outputting 10-20V max with a current delivery capability of only a couple hundred milliamps, which would limit this setup to lower power devices and/or lower power tests. Test setup can also be complex. Getting the desired voltage at the device requires impedance matching with the pulse generator. If a shunt resistor is used to measure current, then the voltage drop across this resistor must be taken into account as well.

Curve tracers were all-in-one instruments designed specifically for I-V characterization of 2- and 3-terminal power semiconductor devices. They featured high current and high voltage supplies for stimulating the device and a configurable voltage/ current source for stimulating the device’s control terminal, a built-in test fixture for making connections, a scope like display for real-time feedback, and a knob for controlling the magnitude of the output. However, Source measure unit (SMU) instruments (FIGURE 4) have now largely taken up the functions they once performed.

FIGURE 4. Model 2620B System SourceMeter SMU instrument.

FIGURE 4. Model 2620B System SourceMeter SMU instrument.

SMU instruments combine the source capabilities of a precision power supply with the measurement capabilities of a high accuracy DMM. Although originally designed for making extremely accurate DC measurements, SMU instruments have been enhanced to include pulse measurement capabilities as well. These instruments can source much higher currents in pulse mode than in DC mode. For example, the Keithley Model 2602B SourceMeter SMU instrument can output up to 3A DC and up to 10A pulsed. For applications that require even high currents, the Model 2651A SourceMeter SMU instrument can output up 20A DC or 50A pulsed. If two Model 2651As are configured in parallel, pulse current outputs up to 100A are possible.

SMU instruments can source both voltage and current with high accuracy thanks to an active feedback loop that monitors the output and adjusts it as necessary to achieve the programmed output value. They can even sense voltage remotely, directly at the DUT, using a second set of test leads, ensuring the correct voltage at the device. These instruments measure with high precision as well, with dual 28-bit delta-sigma or integrating-type ADCs. Using these ADCs along with their flexible sourcing engines, SMUs can perform very accurate pulse I-V measurement sweeps to characterize devices. Some, including the Model 2651A, also include two SAR-type ADCs that can sample at 1 mega-sample per second with 18-bit resolution, making them excellent for transient pulse measurements as well.

In addition, some SMU instruments offer excellent low current capability, with ranges as low as 100pA with 100aA resolution. Their wide dynamic range makes SMU instruments an excellent choice for both ON- and OFF-state device characterization. Also, because they combine sourcing and measurement in a single instrument, SMU instruments reduce the number of instruments involved, which not only simplifies triggering and programming but reduces the overall cost of test.

Although SMU instruments are often used for pulse measurements, they don’t operate in the same way as a typical pulse generator. For example, an SMU instrument’s rise and fall times cannot be controlled by the user; they depend on the instrument’s gain and bandwidth of the feedback loop. Because these loops are designed to generate little or no overshoot when stepping the source, the minimum width of the pulses they produce are not as short as those possible from a pulse generator. However, an SMU instrument can produce pulse widths as short as 50–100μs, which minimizes device self-heating.

The terminology used to describe a pulse when using SMU instruments differs slightly from that used with pulse generators. Rather than referring to the output levels in the pulse as amplitude and base or the high level and the low level, with SMU instruments, the high level is referred to as the pulse level and the low level as the bias level. The term bias level originates from the SMU’s roots in DC testing where one terminal of a device might be biased with a fixed level. Pulse width is still used with SMU instruments, but its definition is slightly different. Given that rise and fall times cannot be set directly and vary with the range in use and the load connected to the output, pulse width can’t be accurately defined by Full Width at Half Maximum (FWHM). (refer to the sidebar for more information on FWHM). Instead, for most SMU instruments, pulse width is defined as the time from the start of the rising edge to the start of the falling edge, points chosen because they are under the user’s control.

In other words, the user can set the pulse width by setting the time between when the source is told to go to the pulse level and then told to go back to the bias level.

FIGURE 5. A pulse measure unit card combines the capabilities of a pulse generator and a high resolution oscilloscope.

FIGURE 5. A pulse measure unit card combines the capabilities of a pulse generator and a high resolution oscilloscope.

Pulse measure units (PMUs) combine the capabilities of a pulse generator and a high-resolution oscilloscope, which are sometimes implemented as card-based solutions designed to plug into a test mainframe. Keithley’s Model 4225-PMU, designed for use with the Model 4200 Semiconductor Charac- terization System (FIGURE 5), is one example. It has two independent channels capable of sourcing up to 40V at up to 800mA. Like a standard pulse generator, users can define all parameters of the pulse shape. Pulse widths as narrow as 60ns and rise and fall times as short as 20ns make it well suited for characterizing devices with fast transients. A Segment Arb mode allows outputting multi-level pulse waveforms in separately defined segments, with separate voltage levels and durations for each. Each PMU channel is capable of measuring both current and voltage using two 14-bit 200MS/s ADCs per channel for a total of four ADCs per card. Additionally, all four ADCs are capable of sampling together synchronously at full speed. By combining a pulse generator with scope- like measurement capability in one instrument, a PMU can not only make high-resolution transient pulse measurements but also perform pulse I-V measurement sweeps easily using a spot mean method for enhanced resolution.

EGBERT WOELK, PH.D., is director of marketing at Dow Electronic Materials, North Andover, MA. ROGER LOO, PH.D., is a principal scientist at imec, Leuven, Belgium.

SEMI today announced the “Call for Papers” for technical sessions and presentations for SEMICON Europa 2015 which takes place October 6-8 in Dresden, Germany. Technical presentation abstracts are due April 30.

SEMICON Europa 2015 will feature more than 100 hours of technical sessions and presentations focused on critical industry topics that are shaping the design and manufacturing of semiconductors, MEMS, printed and flexible electronics, and other related technologies.

Abstracts for presentations are now being accepted for:

  • 17th European Manufacturing Test Conference (EMTC): “Zero defect in shortest time to market and lowest cost –  is it possible?”
  • Advanced Packaging Conference:  “Interconnects in Miniaturized Systems”
  • Semiconductor Technology Conference: “Productivity Enhancements for future Technology Nodes”
  • Plastic Electronics Conference: Business Cases; Manufacturing; Technology/Materials

The SEMICON Europa abstract submission deadline is April 30.  Prospective presenters are invited to submit abstracts (1,000-2,000 characters). Material must be original, non-commercial and non-published. Abstracts must clearly detail the nature, scope, content, organization, key points and significance of the proposed presentation.  More information on how to submit your abstract is available on the “Call for Papers” homepage. Visit www.semiconeuropa.org or contact Christina Fritsch, SEMI Europe, at Tel. +49 30 3030 8077 18 or email [email protected].

Co-located with SEMICON Europa 2015, the Plastic Electronics Conference will also take place in Dresden from October 6-8.  From technology breakthrough to Innovative manufacturing in large area electronics and heterogeneous integrated smart systems to reports about the key manufacturing challenges and selected business cases across the sector, abstracts for presentations are now being accepted (until April 30) for: Technology and Materials; Manufacturing; and Business Cases. Visit www.plastic-electronics.org for more information.

China’s new industry investment and government promotion policies outlined in the recent “National Guidelines for Development and Promotion of the IC Industry” represents major opportunities for China and global semiconductor companies. The details of the policy and its implementation are being closely watched by the global industry for the resources China’s government has dedicated and potential impact to the global semiconductor manufacturing supply chain. During SEMICON China 2015, to be held March 17-19 in Shanghai, SEMI organized Market and Investment forums where key government decision makers, IC fund managers, and global industry analysts will share their insights on the policy and impact to the industry. SEMI expects record numbers of global industry executives to attend the world’s largest microelectronics manufacturing exposition to learn about these semiconductor and emerging/adjacent markets opportunities.

The China “National Guidelines for the Development and Promotion of the IC Industry” sets ambitious targets and sizable support for a China National IC industry investment fund. The combined investment in fabless, IDMs, foundries, and OSATs aims to spur industry at annualized growth rates above 20 percent through 2020. China’s ambitious targets cover: IC manufacturing, IC design, IC packaging and test, materials, and equipment. SEMI estimates the implemented investment plan could reach US$100 billion with the total government and associated local industry funding.

“The rapid development of the semiconductor industry in China has already formed an industry base of domestic enterprises. The unprecedented scale of new industry investment signaled by government plans is likely to further impact the global industry landscape,” said Allen Lu, president of SEMI China. “We are pleased to see significant interest in SEMICON China 2015 as an international gathering — with comprehensive attendance from our industry — to identity the latest business intelligence, global trade prospects, and collaboration opportunities.”

Global companies looking to understand the opportunities, challenges, and risks of China’s investment plans will be participating in events and key forums, including the Semiconductor Market and China Opportunity Forum, Tech Investment Forum-China 2015, Build China’s IC Ecosystem Forum, and China Equipment and Materials Forum. SEMICON China is co-located with FPD China and the LED China Conference, leveraging synergies with these emerging and adjacent markets. Featuring more than 900 exhibitors occupying more than 2,600 booths, SEMICON China is the largest exposition of its kind in China with over 50,000 people expected to attend.

The event will present a comprehensive set of topics through its exhibition, keynote addresses, executive panels, technical and business forums and full-day technology conferences. Grand Opening keynote presenters include: Lisa Su, president and CEO of AMD; Tzu-Yin Chiu, CEO and executive director of SMIC; Xinchao Wang, chairman and CEO of JCET; Simon Yang, president and CEO of XMC; and Michael Hurlston, EVP at Broadcom; and Lei Shi, president of Nantong Fujitsu Microelectronics.

Semiconductor Market and China Opportunity” forum speakers include:

  • Zixue Zhou, chief economist, Ministry of Industry and Information Technology (MIIT); vice chairman and secretary-general, China Information Technology Industry Federation (Zhou is a vice minister-level MIIT official and the chief architect of the new China IC initiatives with setting up of the National IC Fund)
  • Professor Shaojun Wei, director, Institute of Microelectronics, Tsinghua University (Wei is also the leader of the expert group overseeing China’s National Project 01 responsible for growing China’s core competencies in computing and communication). Plus Handel Jones, founder and CEO of IBS; Jim Feldhan, president, Semico Research; and Dan Tracy, senior director, Industry Research and Statistics, SEMI

Tech Investment Forum—China 2015” forum speakers include: Mr. Wenwu Ding, the CEO of the newly formed China National IC Fund (Ding has been a director-general of MIIT in charge of Semiconductor industry); Yongzhi Jiang, managing director of Goldman Sachs Securities in charge of M&A; Lip-Bu Tan, founder and chairman of Walden International and CEO of Cadence; and fund managers from CGP Investment, GM E-town Capital, Summitview Capital and Shenzhen Capital.

Build China’s IC Ecosystem” forum is chaired by Professor Shaojun Wei, with speakers from the complete supply chain from IC design, device makers, to equipment manufacturers. Presenters include executives from Verisilicon, SMIC, XMC, ASMC, JCET, Northern Micro Electronics, and Applied Materials.

China Equipment and Materials Forum” includes speakers from China and global companies: Sevenstar, TEL, ACM Research, and Shanghai Sinyang with a panel discussion moderated by Mr. Tianchun Ye, director of the Institute of Microelectronics, China Academy of Sciences (Mr. Ye is also the leader of expert group of National Project 02 overseeing developing China’s semiconductor manufacturing core-competencies).

This year’s event features six technical conferences: Mobile Technology Enabled by Semiconductors, China Equipment and Materials Forum, Building China’s IC Ecosystem, Advanced Packaging, LED China Conference, and Intelligent Wearable Industry Seminar.  Business programs include: Tech Investment Forum and Semiconductor Market and China Opportunity. Keynote speakers from Intel, IBM, ITRI, University of California, and SMIC will present. ­ FPD China 2015 features special programs on OLED displays, LCD displays, Oxide and LTPS Displays, and Printing Displays and Touch Screens.

China Semiconductor Technology International Conference (CSTIC) is also co-located at SEMICON China. Organized by SEMI and  IEEE-EDS , co-organized by China’s High-Tech Expert Committee (CHTEC), and co-sponsored by ECS, MRS and the China Electronics Materials Industry Association, CSTIC 2015 will cover all aspects of semiconductor technology and manufacturing (more than 300 papers), including devices, design, lithography, integration, materials, processes, and manufacturing, as well as emerging semiconductor technologies and silicon material applications. Hot topics, such as 3D integration, III-V semiconductors, carbon nano-electronics, LEDs, MEMS and Photovoltaic Technology will also be addressed in the conference. (CPTIC 2015 has joined CSTIC 2015 as Symposium XII).

Sponsors of SEMICON China 2015 include: Tokyo Electron, Laytec, SMIC, Huahong Group, JCET, Disco, Edwards, Advantest, Vastity, Shanghai Sinyang, Spirox, and many others.

By CHOWDARY YANAMADALA, Senior Vice President of Business Development, ChaoLogix, Gainesville, FL 

Data is ubiquitous today. It is generated, exchanged and consumed at unprecedented rates.

According to Gartner, Internet of Things connected devices (excluding PCs, tablets and smart phones) will grow to 26 billion devices worldwide by 2020—a 30-fold increase from 2009. Sales of these devices will add $1.9 trillion in economic value globally.

Indeed, one of the major benefits of the Internet of Things movement is the connectivity and accessibility of data; however, this also raises concerns about securely managing that data.

Managing data security in hardware

Data security involves essential steps of authentication and encryption. We need to authenticate data generation and data collection sources, and we need to preserve the privacy of the data.

The Internet of Things comprises a variety of components: hardware, embedded software and services associated with the “things.” Data security is needed at each level.

Hardware security is generally implemented in the chips that make up the “things.” The mathematical security of authentication and encryption algorithms is less of a concern because this is not new. The industry has addressed these concerns for several years.

Nonetheless, hackers can exploit implementation flaws in these chips. Side channel attacks (SCAs) are a major threat to data security within integrated circuits (ICs) that are used to hold sensitive data, such as identifying information and secret keys needed for authentication or encryption algorithms. Specific SCAs include differential power analysis (DPA) and differential electro magnetic analysis (DEMA).

There are many published and unpublished attacks on the security of chips deployed in the market, and SCA threats are rapidly evolving, increasing in potency and the ease of mounting the attacks.

These emerging threats render defensive techniques adopted by the IC manufacturers less potent over time, igniting a race between defensive and offensive (threat) techniques. For example, chips that deploy defensive techniques deemed sufficient in 2012 may be less effective in 2014 due to emerging threats. Once these devices are deployed, they become vulnerable to new threats.

Another challenge IC manufacturers face is the complexity of defensive techniques. Often times, defensive techniques that are algorithm or protocol specific are layered to address multiple targeted threats.

This “Band-Aid” approach is tedious and becomes unwieldy to manage. The industry must remember that leaving hardware vulnerable to SCA threats can significantly weaken data security. This vulnerability may manifest itself in the form of revenue loss (counterfeits of consumables), loss of privacy (compromised identification information), breach of authentication (rogue devices in the closed network) and more.

How to increase the permanence of security

A simplified way to look at the SCA problem is as a signal to noise issue. In this case, signal means sensitive data leaked through power signature. Noise is the ambient or manufactured noise added to the system to obfuscate the signal from being extracted from power signature.

Many defensive measures today concentrate on increasing noise in the system to obfuscate the signal. The challenge with this approach is that emerging statis- tical techniques are becoming adept at separating the signal from the noise, thereby decreasing the potency of the deployed defensive techniques.

One way to effectively deal with this problem is to ”weave security into the fabric of design.” SCA threats can be addressed at the source rather than addressing the symptoms. What if we can make the power signature agnostic of the data processed? What if we can build security into the building blocks of design? That would make the security more permanent and simplify its implementation.

A simplified approach of weaving security into the fabric of design involves leveraging a secure standard cell library that is hardened against SCA. Such a library would use analog design techniques to tackle the problem of SCA at the source, diminishing the SCA signal to make it difficult to extract from the power signature.

Leveraging standard cells should be simple since they are the basic building blocks of digital design. As an industry, we cannot afford to bypass these critical steps to defend our data.