Category Archives: Displays

SEMI today announced a “Call for Papers” for SEMICON West, North America’s premier microelectronics event, to be held July 14-16 at the Moscone Center in San Francisco, Calif. The “Call for Papers” includes the Semiconductor Technology Symposium and the popular TechXPOT programs. Presentation abstracts are due March 20, 2015.

SEMICON West 2015 will be attended by nearly 27,000 semiconductor and related microelectronics industry professionals and feature more than 60 hours of technical sessions, led by the most informed and influential experts in the world. For 2015, SEMICON West will feature two “Generation Next” Pavilions — a new concept in topic-based engagement, which will connect exhibits, technical sessions, and networking events to current, critical industry topics, engaging exhibitors and visitors in an immersive exhibition experience.  In addition, the “standing-room only” success of the SEMICON West TechXPOT programs prompted the creation of the Semiconductor Technology Symposium (STS) at the 2014 event.

In 2015, the STS program continues with programs on leading-edge chip manufacturing held in a classroom setting with reserved seating adjacent to the show floor in the North Hall of Moscone Center. STS will offer technology trends, developments and new technology information in the areas of advanced materials and processing, lithography, metrology, 450mm, advanced packaging, and 3D-IC.  Test Vision 2020, the leading semiconductor test conference focusing on ATE and high-volume manufacturing, is part of the STS program in Moscone Center.

TechXPOT programs in the Moscone Center North and South Halls will continue focusing on special topics in semiconductor manufacturing, and adjacent and related microelectronics technologies.

For the Semiconductor Technology Symposium and for TechXPOT sessions, SEMI is soliciting technical presentations in the following areas:

  • Advanced lithography/Advanced films
  • Advanced materials and processes
  • Contamination control for advanced materials
  • New and advanced metrology solutions
  • Interconnect challenges at sub-10nm
  • Substrates: Materials research beyond Silicon
  • Other process implications for manufacturing next-generation transistors
  • Accelerating and improving yield
  • Silicon Photonics
  • Disruptive compound semiconductor technologies
  • Manufacturing advanced power semiconductors
  • Improving Yield on Non-Planar ICs
  • Failure analysis
  • Advanced packaging
  • Design for packaging
  • Semiconductor test
  • Design for test
  • Application Level Testing
  • Technologies for Emerging Markets & Applications
  • What’s next in MEMS?
  • How manufacturing of IoT devices will impact IC fabrication
  • How IoT and 3D printing will be used in IC manufacturing in the future
  • Printed and flexible electronics
  • Packaging of MEMS and Sensors
  • SiP for Power and RF
  • Heterogeneous Integration for SiP and Modules

“There are many exciting challenges facing the industry today,” said Karen Savala, President of SEMI Americas. “We are pleased that SEMICON West continues to serve as the premier forum where industry leaders share their insight on these issues.”

SEMICON West 2015 “Call for Participants”:  Prospective presenters are invited to submit abstracts (maximum 500 words) on key industry issues and topics in the areas listed above for consideration. Presentations should focus on the latest developments and innovations in these technology areas, inclusive of supporting data. Submissions may be made online from the “Call for Participants” website at: www.semiconwest.org/Participate/SPCFP. The deadline is March 20.

“Generation Next” Pavilions (Advanced Substrate Engineering; Packaging): These two new Generation Next Pavilions will be held in conjunction with technical sessions (STS and TechXPOTs) at SEMICON West — addressing critical issues, challenges, and opportunities. For more information about exhibiting opportunities within these new Pavilions, contact Nick Antonopoulos at [email protected] or +1.408.943.6986.

Silicon Innovation Forum (SIF) “Call for Startups”:  SEMI will host its 3rd Annual Silicon Innovation Forum at SEMICON West 2015 and is now accepting early applications to participate. The Silicon Innovation Forum (SIF) provides a stage for new and emerging innovators, industry leaders, strategic investors, and venture capitalists to discuss the needs and requirements of the industry’s innovation engine. Participants will gain insights into technology, capital, partnership, and collaboration strategies necessary for mutual success. For more information, please email Ray Morgan, director of Outreach at [email protected].  SIF application: 2015 SIF Showcase Request for Participation. The deadline is March 20.

About SEMICON West

SEMICON West is the flagship annual event for the global microelectronics industry, showcasing the people, products, and technologies driving the design and manufacture of advanced microelectronics. SEMICON West attracts the world’s leading technology companies serving the microelectronics supply chain and the largest audience of influential buyers, industry leaders, decision-makers, technologists, analysts, and media of any industry event in North America. SEMICON West 2015 is projected to bring together more than 27,000 international attendees, more than 700 global companies, and feature more than 60 hours of technical, business, and networking programs. For more information, visit www.semiconwest.org.

UCT announces new CEO


January 5, 2015

Ultra Clean Holdings, Inc. today announced that Mr. James Scholhamer has accepted an offer to become UCT’s Chief Executive Officer, effective Monday, January 19, 2015. Mr. Scholhamer will also join UCT’s Board of Directors effective as of his first day of employment.  UCT’s current Chairman and Chief Executive Officer, Clarence Granger, has decided to retire as an officer of the company, effective Monday, January 19th.  Mr. Granger will remain UCT’s non-executive Chairman of the Board of Directors.

Mr. Scholhamer has had an eight-year tenure at Applied Materials, Inc., and has most recently been Corporate Vice President and General Manager, leading the Equipment Products Group and Display Services Group of Applied Materials’ Global Service Division.  Prior to joining Applied Materials, Mr. Scholhamer was Chief Operating Officer, Chief Technology Officer and Executive Vice President of Applied Films Corporation, which was acquired by Applied Materials in 2006.  Mr. Scholhamer holds a bachelor degree in Materials Science and Engineering from the University of Michigan, Ann Arbor.

“After almost two decades with the company and twelve years as CEO, it is time for me to transfer the company’s helm to a new generation of leadership. I am very excited that we have found someone of Jim’s caliber to take on this role,” said Mr. Granger.  “I am confident that we are well positioned for the next phase of the company’s growth, and I look forward to supporting Jim and the company in my role as Chairman.”

“I am very excited to lead UCT as we write the next chapter of the company’s history,” said Scholhamer.  “I want to thank Clarence, the Board, the management team, and all the employees who have worked so hard and so long to nurture and grow a world class organization.  I’m looking forward to building on that foundation by working with the team to take advantage of our potential, create growth opportunities for those employees, and generate attractive returns for our shareholders.”

“Our Board of Directors is confident that Jim will make significant, long-term positive contributions to the Company,” said UCT Director David ibnAle, Chairman of the Nominating and Governance Committee. “We are extremely grateful for Clarence Granger’s contributions to UCT during his tenure as CEO.  Clarence has been the company’s only CEO during its twelve years as an independent company, and he has grown the company successfully across some very challenging cycles and market environments.”

Ultra Clean Holdings, Inc. is a developer and supplier of critical systems and subsystems for the semiconductor capital equipment, flat panel display, medical, energy and research industries.

Worldwide semiconductor market revenue is on track to achieve a 9.4 percent expansion this year, with broad-based growth across multiple chip segments driving the best industry performance since 2010.

Global revenue in 2014 is expected to total $353.2 billion, up from $322.8 billion in 2013, according to a preliminary estimate from IHS Technology (NYSE: IHS). The nearly double-digit-percentage increase follows respectable growth of 6.4 percent in 2013, a decline of more than 2.0 percent in 2012 and a marginal increase of 1.0 percent in 2011. The performance in 2014 represents the highest rate of annual growth since the 33 percent boom of 2010.

“This is the healthiest the semiconductor business has been in many years, not only in light of the overall growth, but also because of the broad-based nature of the market expansion,” said Dale Ford, vice president and chief analyst at IHS Technology. “While the upswing in 2013 was almost entirely driven by growth in a few specific memory segments, the rise in 2014 is built on a widespread increase in demand for a variety of different types of chips. Because of this, nearly all semiconductor suppliers can enjoy good cheer as they enter the 2014 holiday season.”

More information on this topic can be found in the latest release of the Competitive Landscaping Tool from the Semiconductors & Components service at IHS.

Widespread growth

Of the 28 key sub-segments of the semiconductor market tracked by IHS, 22 are expected to expand in 2014. In contrast, only 12 sub-segments of the semiconductor industry grew in 2013.

Last year, the key drivers of the growth of the semiconductor market were dynamic random access memory (DRAM) and data flash memory. These two memory segments together grew by more than 30 percent while the rest of the market only expanded by 1.5 percent.

This year, the combined revenue for DRAM and data flash memory is projected to rise about 20 percent. However, growth in the rest of the market will swell by 6.7 percent to support the overall market increase of 9.4 percent.

In 2013, only eight semiconductor sub-segments grew by 5 percent or more and only three achieved double-digit growth. In 2014, over half of all the sub-segments—i.e., 15—will grow by more than 5 percent and eight markets will grow by double-digit percentages.

This pervasive growth is delivering general benefits to semiconductor suppliers, with 70 percent of chipmakers expected to enjoy revenue growth this year, up from 53 percent in 2013.

The figure below presents the growth of the DRAM and data flash segments compared to the rest of the semiconductor market in 2013 and 2014.

2014-12-18_Semi_Sectors_Growth

Semiconductor successes

The two market segments enjoying the strongest and most consistent growth in the last two years are DRAM and light-emitting diodes (LEDs). DRAM revenue will climb 33 percent for two years in a row in 2013 and 2014. This follows often strong declines in DRAM revenue in five of the last six years.

The LED market is expected to grow by more than 11 percent in 2014. This continues an unbroken period of growth for LED revenues stretching back at least 13 years.

Major turnarounds are occurring in the analog, discrete and microprocessor markets as they will swing from declines to strong growth in every sub-segment. Most segments will see their growth improve by more than 10 percent, compared to the declines experienced in 2013.

Furthermore, programmable logic device (PLD) and digital signal processor (DSP) application-specific integrated circuits (ASICs) will experience dramatic improvements in growth. PLD revenue in 2014 will grow by 10.2 percent compared to 2.1 percent in 2013, and DSP ASICs will rise by 3.8 percent compared to a 31.9 percent collapse in 2013.

Moving on up

Among the top 20 semiconductor suppliers, MediaTek and Avago Technologies attained the largest revenue growth and rise in the rankings in 2014. Both companies benefited from significant acquisitions.

MediaTek is expected to jump up five places to the 10th rank and become the first semiconductor company headquartered in Taiwan to break into the Top 10. Avago Technologies is projected to jump up eight positions in the rankings to No. 15.

The strongest growth by a semiconductor company based purely on organic revenue increase is expected to be achieved by SK Hynix, with projected growth of nearly 23 percent.

No. 13-ranked Infineon has announced its plan to acquire International Rectifier. If that acquisition is finalized in 2014 the combined companies would jump to No. 10 in the overall rankings and enjoy 16 percent combined growth.

The table below presents the preliminary IHS ranking of the world’s top 20 semiconductor suppliers in 2013 and 2014 based on revenue.

2014-12-18_Semi_Ranking_Final

Troubles for consumer electronics and Japan

Semiconductor revenue in 2014 will grow in five of the six major semiconductor application end markets, i.e. data processing, wired communications, wireless communications, automotive electronics and industrial electronics. The only market segment experiencing a decline will be consumer electronics. Revenue will expand by double-digit percentages in four of the six markets.

Japan continues to struggle, and is the only worldwide region that will see a decline in semiconductor revenues this year. The other three geographies—Asia-Pacific, the Americas and the Europe, Middle East and Africa (EMEA) region—will see healthy growth. The world will be led by led by Asia-Pacific which will post an expected revenue increase of 12.5 percent.

In a sub-basement deep below the Laboratory for Integrated Science and Engineering at Harvard University, Mikhail Kats gets dressed. Mesh shoe covers, a face mask, a hair net, a pale gray jumpsuit, knee-high fabric boots, vinyl gloves, safety goggles, and a hood with clasps at the collar–these are not to protect him, Kats explains, but to protect the delicate equipment and materials inside the cleanroom.

While earning his Ph.D. in applied physics at the Harvard School of Engineering and Applied Sciences, Kats has spent countless hours in this cutting-edge facility. With his adviser, Federico Capasso, the Robert L. Wallace Professor of Applied Physics and Vinton Hayes Senior Research Fellow in Electrical Engineering, Kats has contributed to some stunning advances.

One is a metamaterial that absorbs 99.75 percent of infrared light–very useful for thermal imaging devices. Another is an ultrathin, flat lens that focuses light without imparting the distortions of conventional lenses. And the team has produced vortex beams, light beams that resemble a corkscrew, that could help communications companies transmit more data over limited bandwidth.

Certainly the most colorful advance to emerge from the Capasso lab, however, is a technique that coats a metallic object with an extremely thin layer of semiconductor, just a few nanometers thick. Although the semiconductor is a steely gray color, the object ends up shining in vibrant hues. That’s because the coating exploits interference effects in the thin films; Kats compares it to the iridescent rainbows that are visible when oil floats on water. Carefully tuned in the laboratory, these coatings can produce a bright, solid pink–or, say, a vivid blue–using the same two metals, applied with only a few atoms’ difference in thickness.

Capasso’s research group announced the finding in 2012, but at that time, they had only demonstrated the coating on relatively smooth, flat surfaces like silicon. This fall, the group published a second paper, in the journal Applied Physics Letters, taking the work much further.

“I cut a piece of paper out of my notebook and deposited gold and germanium on it,” Kats says, “and it worked just the same.”

That finding, deceptively simple given the physics involved, now suggests that the ultrathin coatings could be applied to essentially any rough or flexible material, from wearable fabrics to stretchable electronics.

“This can be viewed as a way of coloring almost any object while using just a tiny amount of material,” Capasso says.

It was not obvious that the same color effects would be visible on rough substrates, because interference effects are usually highly sensitive to the angle of light. And on a sheet of paper, Kats explains, “There are hills and valleys and fibers and little things sticking out–that’s why you can’t see your reflection in it. The light scatters.”

On the other hand, the applied films are so extremely thin that they interact with light almost instantaneously, so looking at the coating straight on or from the side–or, as it turns out, looking at those rough imperfections in the paper–doesn’t make much difference to the color. And the paper remains flexible, as usual.

Demonstrating the technique in the cleanroom at the Center for Nanoscale Systems, a National Science Foundation-supported research facility at Harvard, Kats uses a machine called an electron beam evaporator to apply the gold and germanium coating. He seals the paper sample inside the machine’s chamber, and a pump sucks out the air until the pressure drops to a staggering 10^-6 Torr (a billionth of an atmosphere). A stream of electrons strikes a piece of gold held in a carbon crucible, and the metal vaporizes, traveling upward through the vacuum until it hits the paper. Repeating the process, Kats adds the second layer. A little more or a little less germanium makes the difference between indigo and crimson.

This particular lab technique, Kats points out, is unidirectional, so to the naked eye very subtle differences in the color are visible at different angles, where slightly less of the metal has landed on the sides of the paper’s ridges and valleys. “You can imagine decorative applications where you might want something that has a little bit of this pearlescent look, where you look from different angles and see a different shade,” he notes. “But if we were to go next door and use a reactive sputterer instead of this e-beam evaporator, we could easily get a coating that conforms to the surface, and you wouldn’t see any differences.”

Many different pairings of metal are possible, too. “Germanium’s cheap. Gold is more expensive, of course, but in practice we’re not using much of it,” Kats explains. Capasso’s team has also demonstrated the technique using aluminum.

“This is a way of coloring something with a very thin layer of material, so in principle, if it’s a metal to begin with, you can just use 10 nanometers to color it, and if it’s not, you can deposit a metal that’s 30 nm thick and then another 10nm. That’s a lot thinner than a conventional paint coating that might be between a micron and 10 microns thick.”

In those occasional situations where the weight of the paint matters, this could be very significant. Capasso remembers, for example, that the external fuel tank of NASA’s space shuttle used to be painted white. After the first two missions, engineers stopped painting it and saved 600 pounds of weight.

Because the metal coatings absorb a lot of light, reflecting only a narrow set of wavelengths, Capasso suggests that they could also be incorporated into optoelectronic devices like photodetectors and solar cells.

“The fact that these can be deposited on flexible substrates has implications for flexible and maybe even stretchable optoelectronics that could be part of your clothing or could be rolled up or folded,” Capasso says.

Harvard’s Office of Technology Development continues to pursue commercial opportunities for the new color coating technology and welcomes contact from interested parties.

Kats, who concludes his year-long postdoctoral research position at SEAS this month, will become an assistant professor at the University of Wisconsin, Madison, in January. He credits those many hours spent in Harvard’s state-of-the-art laboratory facilities for much of his success in applied physics.

“You learn so much while you’re doing it,” Kats says. “You can be creative, discover something along the way, apply something new to your research. It’s marvelous that we have students and postdocs down here making things.”

By DAVE HEMKER, Senior Vice President and Chief Technology Officer, Lam Research Corp.

Given the current buzz around the Internet of Things (IoT), it is easy to lose sight of the challenges
– both economic and technical. On the economic side is the need to cost-effectively manufacture up to a trillion sensors used to gather data, while on the technical side, the challenge involves building out the infrastructure. This includes enabling the transmission, storage, and analysis of volumes of data far exceeding anything we see today. These divergent needs will drive the semiconductor equipment industry to provide very different types of manufacturing solutions to support the IoT.

In order to fulfill the promise of the IoT, sensor technology will need to become nearly ubiquitous in our businesses, homes, electronic products, cars, and even our clothing. Per-unit costs for sensors will need to be kept very low to ensure the technology is economically viable. To support this need, trailing-edge semiconductor manufacturing capabilities provide a viable option since fully depreciated wafer processing equipment can produce chips cost efficiently. For semiconductor equipment suppliers, this translates into additional sales of refurbished and productivity-focused equipment and upgrades that improve yield, throughput, and running costs. In addition to being produced inexpensively, sensors intended for use in the IoT will need to meet several criteria. First, they need to operate on very low amounts of power. In fact, some may even be self-powered via MEMS (microelectromechanical systems)-based oscillators or the collection of environmental radio frequency energy, also known as energy harvesting/scavenging. Second, they will involve specialized functions, for example, the ability to monitor pH or humidity. Third, to enable the transmission of data collected to the supporting infrastructure, good wireless communications capabilities will be important. Finally, sensors will need to be small, easily integrated into other structures – such as a pane of glass, and available in new form factors – like flexible substrates for clothing. Together, these new requirements will drive innovation in chip technology across the semiconductor industry’s ecosystem.

The infrastructure needed to support the IoT, in contrast, will require semiconductor performance to continue its historical advancement of doubling every 18-24 months. Here, the challenges are a result of the need for vast amounts of networking, storage in the Cloud, and big data analysis. Additionally, many uses for the IoT will involve risks far greater than those that exist in today’s internet. With potential medical and transportation applications, for example, the results of data analysis performed in real time can literally be a matter of life or death. Likewise, managing the security and privacy of the data being generated will be paramount. The real-world nature of things also adds an enormous level of complexity in terms of predictive analysis.

Implementing these capabilities and infrastructure on the scale imagined in the IoT will require far more powerful memory and logic devices than are currently available. This need will drive the continued extension of Moore’s Law and demand for advanced semiconductor manufacturing capability, such as atomic-scale wafer processing. Controlling manufacturing process variability will also become increasingly important to ensure that every device in the new, interconnected world operates as expected.

With development of the IoT, semiconductor equipment companies can look forward to opportunities beyond communications and computing, though the timing of its emergence is uncertain. For wafer processing equipment suppliers in particular, new markets for leading-edge systems used in the IoT infrastructure and productivity-focused upgrades for sensor manufacturing are expected to develop.

The most expensive defect


December 18, 2014

Defects that aren’t detected inline cost fabs the most. 

By DAVID W. PRICE and DOUGLAS G. SUTHERLAND, KLA-Tencor, Milpitas, CA

Defect inspection tools can be expensive. But regardless of the cost of the inspection tool needed to find a defect, the fab is almost always better off financially if it can find and fix that defect inline versus at the end of line (e.g., electrical test and failure analysis). Here, we are referring to the term defect in a general sense—the same concepts also apply to metrology measurements.

The third fundamental truth of process control for the semiconductor IC industry is:

The most expensive defect is the one that wasn’t detected inline.

FIGURE 1A (top) shows an imaginary SPC chart for a factory experiencing a baseline shift in defectivity (an excursion) beginning at Lot #300. FIGURE 1B (bottom) shows the same scenario except the fab has an effective inline monitor at the point of the excursion. In this case, the excursion is quickly identified and the offending process tool is taken offline for process tuning or maintenance. The excursion is contained and relatively few lots are impacted by the resulting yield loss.

Defects 1a

FIGURE 1. It is always better to find and fix problems inline versus at the end of line. 1a. Problem identification and correction does not occur until bad wafers reach end-of-line test. 1b. Problem identification and correction occurs immediately.

FIGURE 1. It is always better to find and fix problems inline versus at the end of line. 1a. Problem identification and correction does not occur until bad wafers reach end-of-line test. 1b. Problem identification and correction occurs immediately.

The difference between these two scenarios is that in the top chart, the fab is unable to detect the excursion inline so the baseline shift continues unabated until the first affected lots hit end of line test. For a foundry process with a 60-day cycle time, this delay could easily exceed 20 days.

In our experience working with IC manufacturers, the majority of financial impact does not come from large excursions that cause significant yield loss to every affected wafer—those problems are usually identified and rectified very early on. Rather, the largest losses usually come from small excursions that are difficult to detect. They cause relatively low levels of yield loss but persist for prolonged periods of time. It is not uncommon to see thousands or even tens of thousands of wafers exposed to these low level excursions.

The culprit is nearly always a process control capability issue that can be traced back to one or more possible problems. The following list is not meant to be exhaustive, but is instead, representative of the most common causes:

Defects 2

FIGURE 2. Cost vs. mean time to detection (MTTD) of finding a defect inline. The curves are drawn for 4 different wafer costs in a fab with 100k WSPM. It is assumed that the excursion takes place at a single step in the process and happens once per year to each of the process tools at that step. The yield loss is assumed to be 20% during the excursion.

  • Insufficient number of inspection points to allow effective isolation of the defect source.
  • Failing to use a sensitive enough inspection tool or recipe (pixel size is too large, wrong wavelength,
  • etc.)
  • Inspection area of wafer is too low.
  • Review sample size is too small.

Often, the original inspection strategy was carefully designed, but as time passed, changes were made to reduce costs. As new sources of noise are introduced in the SPC chart, the fab becomes less sensitive to small excursions.

FIGURE 2 shows the economic impact to the fab for the two scenarios shown by the SPC chart in FIGURE 1. Imagine an excursion which results in a net 25 percent yield loss (e.g., one out of four wafers must be scrapped). Finding that excursion at end-of-line (+30 days) versus inline (greater than one day) would amount to a staggering $21 million loss per occurrence for an average size run rate of 25k wafer starts per month. Given that this value only repre- sents the cost of re-manufacturing the scrapped wafers it could actually be a conservative estimate. The true cost could easily be double that amount for a fab that is running at the limit of their capacity since it would directly impact revenue.

Even if the situation requires the use of a relatively expensive inspection tool to find, monitor and resolve the problem, it is nearly always in the factory’s best interest to do so. One of the implications of this truth is that if an important defect type can only be detected by a certain inspection tool, then that inspection tool is almost always the most cost-effective solution for that layer. Rather than modifying process control strategies to save costs, it is nearly always in the factory’s best interest to maintain capable, inline process control strategies that prevent the financial impact of ‘the most expensive defect.’

Author’s Note: This is the third in a series of 10 installments that explore fundamental truths about process control—defect inspection and metrology—for the semiconductor industry. Each article introduces one of the 10 fundamental truths and highlights their implications.

Read more Process Watch:

Process Watch: Fab managers don’t like surprises

Process Watch: The 10 fundamental truths of process control for the semiconductor IC industry

Process Watch: Exploring the dark side

The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

 

Cross section sample preparation is demonstrated using a workflow that combines High Accuracy Cleaving I(HAC) and Broad Ion Beam (BIB) milling.

By TESHIMA, LatticeGear, Beaverton, OR and JAMIL J. CLARKE, Hitachi High Technologies America, Inc., Clarksburg, MD 

In order to develop and manufacture new materials and processes, the cross section is essential (FIGURE 1). Cross sections allow one to visualize, measure, and characterize the chemistry of the film stack or device structures. This allows engineers to verify the integrity of devices and to make critical decisions about the process. To be able to provide this data, manufacturers and equipment suppliers invest close to a billion dollars annually [1] to purchase equipment for off-line use and out- of-fab support labs.

FIGURE 1. Cross section of a fully processed microprocessor prepared by high accuracy cleaving and flat milling

FIGURE 1. Cross section of a fully processed microprocessor prepared by high accuracy cleaving and flat milling

Because such labs are not considered a “make wafer” function, lab managers are under constant pressure to reduce costs, both per sample and for lab operations. This paper demonstrates cross section sample preparation using a workflow that combines High Accuracy Cleaving (HAC) and Broad Ion Beam (BIB) milling. Coupling these techniques, which are relatively low in cost when compared to Focused Ion Beam (FIB) or automated polishing or cleaving [2], reduces sample preparation time, complexity, and cost without sacrificing cross-section quality. The LatticeAxTM HAC and the Hitachi IM4000 BIB milling tools were used to demonstrate this process and are also described.

Preparing cross sections for SEM analysis

Characterization of semiconductor structures and material properties commonly begins with sample preparation. Semiconductor samples are inspected either as a cross section or “top down.” Cross-section samples are needed to inspect layers of subsurface features. As shown in FIGURE 2, if a cross-section view is required and the original sample is a wafer or a die, cleaving is typically the first step in the sample preparation procedure.

FIGURE 2. Wafers and wafer pieces enter a cross- section workflow that starts with cleaving and then follows a single- or multi-tool sample preparation process.

FIGURE 2. Wafers and wafer pieces enter a cross- section workflow that starts with cleaving and then follows a single- or multi-tool sample preparation process.

In many cases, the sample can proceed directly to the Scanning Electron Microscope (SEM) as shown in the Single-Tool workflow. For fully processed devices and those with large metal structures, improving surface quality with another method enhances the results (see Multi-Tool workflow).

Advanced techniques used in the multi-tool workflow, such as FIB and automated polishing, have benefits in terms of submicron—or in the case of FIB, nanometer—targeting accuracy, but the tradeoff is high cost, long cycle time, and the need for skilled operators.

Methods

The following sections describe the techniques used to perform multi-tool, cross-section sample prepa- ration workflow using HAC and BIB milling.

High Accuracy Cleaving An accurate and high quality cleave is critical to preparing a cross section for SEM imaging regardless of whether it follows the single- or multi-tool workflow. Manual cleaving, in which you scribe a line and then break the sample along the fracture over a raised edge or pin, has inherent problems with accuracy and repeatability. In addition, because the user handles the sample with fingers that are often gloved, great skill is required to achieve good results. FIGURE 3a shows traditional scribing hand tools used in manual cleaving. Cleaving results using these tools are obviously dependent on the hand-eye coordination of the operator.

FIGURE 3a. Hand tools commonly used for cleaving semiconductor materials

FIGURE 3a. Hand tools commonly used for cleaving semiconductor materials

Figure 3b

Figure 3b

The LatticeAx process overcomes these disadvantages by controlling the indent location and depth, as well as the cleaving operation, with fine-positioning knobs on the LatticeAx high magnification digital microscope. This new machine-assisted Indent and Cleave[3] approach bridges both manual scribing and fully automated cleaving or polishing, and increases success rates while keeping costs down.

The accurate, repeatable indent and slow, controlled cleaving that results from this hybrid tool (FIGURE 3b) speeds preparation time and produces high accuracy, quality results—regardless of user experience—and with greater flexibility of sample size and dimensions.

Broad Ion Beam Milling The BIB milling system is a specimen preparation device (FIGURE 3c) for SEM and surface analysis (EDX[4], EBSP[5], etc.). The device uses a defocused beam of argon ions that sputter material from the target specimen at a rate up to 2-500μm/hour, depending on the mode used. The BIB milling system uses a simple, repeatable process to remove surface layers of a specimen and for final finish of specimens in cross section. It is advantageous compared to mechanical polishing methods, which require well-trained operators to polish the specimen to a flat and mirror-like surface and hit a specific target. In addition, complex material composites that contain materials varying in hardness pose challenges when mechanically prepared using polishing wheels and compounds. This mechanical approach can lead to cracks, stress, relief (pull-out effects), and smearing. These adverse effects are minimized when using the low voltage (0-6kV) argon beam to remove material.

FIGURE 3c. Hitachi IM4000Plus broad ion beam milling system

FIGURE 3c. Hitachi IM4000Plus broad ion beam milling system

Flat Milling Mode Using the BIB’s “Flat Milling” mode yields a high quality cross section in a short amount of time. It requires the initial high accuracy cleave to be through or within a few 100nms of the area of interest and the face of the cross section to be at 90 degrees to the sample surface. With a high quality cleave, the BIB’s Flat Milling mode quickly polishes the cross-section face. Material is removed at a rate of 2μm/hr. Using the flat milling holder, the milling process can uniformly sputter an area approximately ~5mm across around the center of rotation of the specimen (FIGURE 3d). Typical operating parameters for the Hitachi IM4000Plus are 3kV accelerating voltage and a tilt of 70 degrees, with sample stage oscillation set to ±90 degrees and 10rpm. The best quality surface is achieved with a minimum mill time, thus the importance of cleaving through, or very close to, the region of interest. Otherwise, variations in the milling rates of different materials produce artifacts, often called “curtaining.”

Figure 3d

Figure 3d

Cross-section Mode When more than a few microns of material need to be removed, the BIB system is operated in “Cross-section” mode. This is commonly used when exposing a sub-surface target structure. Mechanical grinding causes mechanical artifacts and deformation from stress, making it difficult to obtain a smooth surface for SEM analysis. When using the cross-section milling holder, the BIB IM4000Plus shields part of the argon ion beam with the mask arranged on the specimen, and produces a cross section along the trailing edge of the mask into the sample. For Cross-section mode, targeting accuracy is approximately +/- 15μm.

Backside Milling Backside (as opposed to topside) milling mode can be used in both flat milling and cross-section modes. Backside milling is effective and necessary to alleviate curtaining effects[6] that can occur when traditional top-down ion milling induces striations. These striations are caused by the milling differential from neigh- boring materials that are atomically denser than the surrounding area. FIGURE 4 shows the direction of the ion beam during backside milling and the trench milled by the ion beam.

FIGURE 4. Copper bump after backside milling shows both the milling direction and the trench created by the ion beam

FIGURE 4. Copper bump after backside milling shows both the milling direction and the trench created by the ion beam

Case Study 1. Quick 5-minute HAC and Flat Milling for Cross Section Final Polish

In this example, a cross section was prepared of an Intel microprocessor removed from its package. The size of the sample available after deprocessing was 8 x 8mm. To prepare the cross section, the sample was cleaved parallel to 15μm contacts visible on the sample surface. The Hitachi IM4000 was then used to prepare the final surface using flat milling mode. Approximately 100nm of material was removed in 10 minutes to achieve the polished surface of the final cross section.

The cross-section process included:

1. Indenting the 15μm area of interest (AOI) with the LatticeAx (FIGURE 5a) (3 min)
2. Cleaving through the AOI using the small sample cleaving accessory[7] (2 min) (FIG 5b-c)
3. Mounting the sample for the IM4000Plus and backside milling using flat milling mode (15 min)

FIGURE 5a. Case Study 1 –HAC and flat milling processes for cross section final polish

FIGURE 5a. Case Study 1 –HAC and flat milling processes for cross section final polish

FIGURE 5b. View of sample after cleaving with the small sample cleaver

FIGURE 5b. View of sample after cleaving with the small sample cleaver

 

FIGURE 5c. Optical view of the cross section after cleaving

FIGURE 5c. Optical view of the cross section after cleaving

Results

This demonstrates a rapid (15-minute) method to obtain a damage-free cross section from a fully processed microprocessor over a very large area (5mm in diameter). A comparison of the results before and after milling shows the clear improvement in surface quality and SEM imaging results (FIGURE 5d and e). Using other methods such as mechanical polishing or FIB can take several hours to achieve a comparable size produced by the large flat-milled region. The best results were obtained when removing a minimum of material (nms), demonstrating the importance of an accurate, high quality cleave prior to BIB milling. FIGURE 5f shows a high-magnification view of the resulting cross section after flat milling that is high quality and without curtaining.

FIGURE 5d. SEM image of the microprocessor after cleaving

FIGURE 5d. SEM image of the microprocessor after cleaving

FIGURE 5e. SEM image of the microprocessor after 10 minutes of BIB milling using flat milling mode

FIGURE 5e. SEM image of the microprocessor after 10 minutes of BIB milling using flat milling mode

 

FIGURE 5f. SEM image showing planar cross section after flat milling

FIGURE 5f. SEM image showing planar cross section after flat milling

Case Study 2. Using HAC and BIB Milling in Cross-section Mode to Prepare Cross Sections of Solder Bumps

Cross sections are required to inspect solder bump reliability for interconnect problems during development and production, or for electromigration failure after aging. Creating these cross sections in a targeted location is critical for effective fault isolation and SEM analysis. With the advent of large Through Silicon-Via (TSV) and solder bump structures—often 100μm in depth or width—high throughput methods are necessary to make cross sections efficiently and effectively.[8]

In this case study, the solder bumps were prepared for SEM in a two-step process. In step 1, the LatticeAx cleaver was used to cleanly cross-section close to, and parallel to, a specific row of copper bumps. The copper bumps had a diameter of 85μm and were cleaved 30 μm from the center of a bump. Time to cleave was 5 minutes and yielded the results shown in FIGURE 6a and FIGURE 6b.

FIGURE 6a. SEM image of the microprocessor after cleaving

FIGURE 6a. SEM image of the microprocessor after cleaving

FIGURE 6b. SEM image of the microprocessor after cleaving

FIGURE 6b. SEM image of the microprocessor after cleaving

In step 2, a broad argon ion beam instrument, the Hitachi IM4000, was used to prepare the final imaging surface within the copper bump. The backside milling method was used; no further preparation was performed.

Results

FIGURES 6c and 6d, taken after ion milling, plainly show the improved surface quality and copper grain structures, as well as fine details at the interface between the bump and adjacent structures. By cleaving close to the center of the copper bumps, the milling time on the BIB was reduced to less than 2 hours versus tens of hours for large cross-section areas (multiple bumps).

This two-step sample preparation process described has been implemented in production by a large semiconductor manufacturer. The technique described reduces turn-around time and repeatedly results in artifact-free cross sections of copper solder bumps.

FIGURE 6c. SEM image of the microprocessor after cleaving

FIGURE 6c. SEM image of the microprocessor after cleaving

FIGURE 6d. SEM image of the microprocessor after cleaving

FIGURE 6d. SEM image of the microprocessor after cleaving

Conclusion

For “off-line” laboratories, using HAC and BIB together for creating high quality cross sections is a compelling, low-cost alternative to investments in FIBs or automated polishing or cleaving equipment. High accuracy cleaving reduces sample preparation time, complexity, and cost without sacrificing cross- section quality. Combining this with a broad argon ion beam instrument for quick removal of minimal amounts of material or for milling of large flat areas, HAC presents effective, accurate results critical to product or failure analysis, while keeping both equipment and per-sample costs low.

Whether for final polish or in sample preparation of solder bumps, the results from the machine-assisted high accuracy Indent and Cleave approach combined with broad ion beam milling rival those of fully automated cleaving or polishing systems

References

1. Per industry sources
2. Approximate costs: FIB/SEM at $1-2 million; Automated HAC at $300,000; HAC+BIB milling tool at $160,000.
3. Cleaving Breakthrough: A New Method Removes Old Limitations, E. Moyal, E. Brandstädt, EDFAAO (2014) 3:26-31
4. Energy-dispersive X-ray spectroscopy
5. Electron backscatter pattern
6. CAVolkert and AM Minor, MRS Bull 32(5) (2007) 389–99.
7. The small sample cleaving accessory is used to clamp samples as small as 4mm wide for indenting with the LatticeAx and cleaving using a separate cleaving base. 8. Sample Preparation of Semiconductor Materials with a New Site-specific Cleaving Technology, Microscopy Today, September 2013, Teshima et al., 56-59.

J. TESHIMA is with LatticeGear, LLC., 1500 NW Bethany Blvd., Suite 200, Beaverton, OR 97006, USA. JAMIL J. CLARKE is with Hitachi High Technologies America, Inc., Nanotechnology Systems Division, 22610 Gateway Center, Dr. Clarksburg, MD 20871, USA

North America-based manufacturers of semiconductor equipment posted $1.22 billion in orders worldwide in November 2014 (three-month average basis) and a book-to-bill ratio of 1.02, according to the November EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.02 means that $102 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in November 2014 was $1.22 billion. The bookings figure is 10.4 percent higher than the final October 2014 level of $1.10 billion, and is 1.7 percent lower than the November 2013 order level of $1.24 billion.

The three-month average of worldwide billings in November 2014 was $1.19 billion. The billings figure is 0.5 percent higher than the final October 2014 level of $1.18 billion, and is 6.8 percent higher than the November 2013 billings level of $1.11 billion.

“”With the rise in bookings, the book-to-bill ratio climbed above parity in November,”” said SEMI president and CEO Denny McGuirk. “”2014 has been a solid growth year for the semiconductor equipment market, and we expect the foundry and memory sector to continue leading investments in 2015.””

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill

June 2014 

$1,327.5

$1,455.0

1.10

July 2014 

$1,319.1

$1,417.1

1.07

August 2014 

$1,293.4

$1,346.1

1.04

September 2014 

$1,256.5

$1,186.2

0.94

October 2014 (final)

$1,184.2

$1,102.3

0.93

November 2014 (prelim)

$1,189.8

$1,217.1

1.02

Source: SEMI, December 2014

Global desktop monitor sell-in revenue rose 7 percent in the third quarter (Q3) of 2014, as average selling prices (ASPs) rose just over 10 percent. According to a new report from DisplaySearch, now part of IHS, worldwide desktop PC monitor shipments declined just over 3 percent, to reach 34 million units.

“Sales margins for desktop displays have declined over time, and manufacturers are now trying to reverse that trend with bigger sizes and improved features, to justify higher prices,” said Hidetoshi Himuro, director of PC/IT market research for DisplaySearch. “In the face of tablets and notebook computers with integrated displays, demand for desktop monitors is shifting toward higher display quality and resolution, with improved performance for professional operation and computer gaming.”

Table: Monitor Set Shipment Attribute Comparison 

Item

Q3’13

Q3’14

Y/Y change

Average Sales Price

$155

$171

10%

Size share  – 20″ and above

60%

64%

7%

Resolution share  – 1920×1080 and above

48%

55%

14%

Wide Viewing Angle Share (IPS/FFS+VA)

17%

19%

13%

Source: DisplaySearch Quarterly Desktop Monitor Shipment and Forecast Report, Q3 2014.

In order to improve PC display penetration rates, average screen sizes have been steadily increasing. For example, market share for 20-inch-and-larger desktop monitor screens rose from 60 percent in Q3 2013 to 64 percent in Q3 of this year. Displays with full-high-definition (FHD) and higher resolutions have grown from 48 percent in Q3 2013 to 55 percent in Q3 of this year. Desktop PC displays shipped with wide viewing angle technology have also increased from 17 percent to 19 percent, year over year.

A team of researchers led by North Carolina State University has found that  stacking materials that are only one atom thick can create semiconductor junctions that transfer charge efficiently, regardless of whether the crystalline structure of the materials is mismatched – lowering the manufacturing cost for a wide variety of semiconductor devices such as solar cells, lasers and LEDs.

“This work demonstrates that by stacking multiple two-dimensional (2-D) materials in random ways we can create semiconductor junctions that are as functional as those with perfect alignment” says Dr. Linyou Cao, senior author of a paper on the work and an assistant professor of materials science and engineering at NC State.

“This could make the manufacture of semiconductor devices an order of magnitude less expensive.”

Schematic illustration of monolayer MoS2 and WS2 stacked vertically. Image: Linyou Cao.

Schematic illustration of monolayer MoS2 and WS2 stacked vertically. Image: Linyou Cao.

For most semiconductor electronic or photonic devices to work, they need to have a junction, which is where two semiconductor materials are bound together. For example, in photonic devices like solar cells, lasers and LEDs, the junction is where photons are converted into electrons, or vice versa.

All semiconductor junctions rely on efficient charge transfer between materials, to ensure that current flows smoothly and that a minimum of energy is lost during the transfer. To do that in conventional semiconductor junctions, the crystalline structures of both materials need to match. However, that limits the materials that can be used, because you need to make sure the crystalline structures are compatible. And that limited number of material matches restricts the complexity and range of possible functions for semiconductor junctions.

“But we found that the crystalline structure doesn’t matter if you use atomically thin, 2-D materials,” Cao says. “We used molybdenum sulfide and tungsten sulfide for this experiment, but this is a fundamental discovery that we think applies to any 2-D semiconductor material. That means you can use any combination of two or more semiconductor materials, and you can stack them randomly but still get efficient charge transfer between the materials.”

Currently, creating semiconductor junctions means perfectly matching crystalline structures between materials – which requires expensive equipment, sophisticated processing methods and user expertise. This manufacturing cost is a major reason why semiconductor devices such as solar cells, lasers and LEDs remain very expensive. But stacking 2-D materials doesn’t require the crystalline structures to match.

“It’s as simple as stacking pieces of paper on top of each other – it doesn’t even matter if the edges of the paper line up,” Cao says.

The paper, “Equally Efficient Interlayer Exciton Relaxation and Improved Absorption in Epitaxial and Non-epitaxial MoS2/WS2 Heterostructures,” was published as a “just-accepted” manuscript in Nano Letters Dec. 3.

Lead authors of the paper are Yifei Yu, a Ph.D. student at NC State; Dr. Shi Hu, a former postdoctoral researcher at NC State; and Liqin Su, a Ph.D. student at the University of North Carolina at Charlotte. The paper was co-authored by Lujun Huang, Yi Liu, Zhenghe Jin, and Dr. Ki Wook Kim of NC State; Drs. Alexander Puretzky and David Geohegan of Oak Ridge National Laboratory; and Dr. Yong Zhang of UNC Charlotte. The research was funded by the U.S. Army Research Office under grant number W911NF-13-1-0201 and the National Science Foundation under grant number DMR-1352028.