Category Archives: Displays

Anyone who’s stuffed a smart phone in their back pocket would appreciate the convenience of electronic devices that could bend. Flexible electronics could spawn new products: clothing wired to cool or heat, reading tablets that could fold like newspaper, and so on.

The yellow electric charge races through a "speed-lane" in this stylized view of a polymer semiconductor, but pauses before leaping to the next fast path. Stanford engineers are studying why this occurs with an eye toward building flexible electronics.

The yellow electric charge races through a “speed-lane” in this stylized view of a polymer semiconductor, but pauses before leaping to the next fast path. Stanford engineers are studying why this occurs with an eye toward building flexible electronics.

Alas, electronic components such as chips, displays and wires are generally made from metals and inorganic semiconductors — materials with physical properties that make them fairly stiff and brittle.

In the quest for flexibility many researchers have been experimenting with semiconductors made from plastics or, more accurately polymers, which bend and stretch readily enough.

“But at the molecular level polymers look like a bowl of spaghetti,” says Stanford chemical engineering professor Andrew Spakowitz, adding: “Those non-uniform structures have important implications for the conductive properties of polymeric semiconductors.”

Spakowitz and two colleagues, Rodrigo Noriega, a postdoctoral researcher at UC Berkeley, and Alberto Salleo, a Stanford professor of Materials Science and Engineering, have created the first theoretical framework that includes this molecular-level structural inhomogeneity, seeking to understand, predict and improve the conductivity of semiconducting polymers.

Their theory, published Monday, Sep. 23, 2013 in the Proceedings of the National Academy of Sciences, deals with the observed tendency of polymeric semiconductors to conduct electricity at differing rates in different parts of the material – a variability that, as the Stanford paper explains, turns out to depend on whether the polymer strands are coiled up like a bowl of spaghetti or run relatively true, even if curved, like lanes on a highway.

In other words, the entangled structure that allows plastics and other polymers to bend also impedes their ability to conduct electricity, whereas the regular structure that makes silicon semiconductors such great electrical switches tends to make it a bad fit for our back pockets.

The Stanford paper in PNAS gives experimental researchers a model that allows them to understand the tradeoff between the flexibility and conductivity of polymeric semiconductors.

Grasping how they created their model requires a basic understanding of polymers. The word “polymer” is derived from the Greek for “many parts” which aptly describes their simple molecular structure, which consists of identical units, called monomers, that string together, end to end, like so many sausages. Humans have long used natural polymers such as silk and wool, while newer industrial processes have adapted this same technique to turn end-to-end chains of hydrocarbon molecules, ultimately derived from petroleum byproducts, into plastics.

But it was only in the late 1970s that a trio of scientists discovered that plastics which, until then were considered non-conductive materials suitable to wrap around wires for insulation could, under certain circumstances, be induced to conduct electricity.

The three scientists, Alan Heeger, Alan MacDiarmid and Hideki Shirakawa, shared the Nobel Prize in Chemistry in 2000 for their co-discovery of polymeric semiconductors. In recent years, with increasing urgency, researchers have been trying to harness the finicky electrical properties of plastics with an eye toward fashioning electronics that will bend without breaking.

In the process of experimenting with polymeric semiconductors, however, researchers discovered that these flexible materials exhibited “anomalous transport behavior” or, simply put, variability in the speed at which electrons flowed through the system.

One of the fundamental insights of the Stanford paper is that electron flow through polymers is affected by their spaghetti-like structure – a structure that is far less uniform than that of the various forms of silicon and other inorganic semiconductors whose electrical properties are much better understood.

“Prior theories of electrical flow in polymeric semiconductors are largely extrapolated from our understanding of metals and inorganic semiconductors like silicon,” Spakowitz said, adding that he and his collaborators began by taking a molecular-level view of the electron transport issue.

In essence, the variability of electron flow through polymeric semiconductors owes to the way the structure of these molecular chains creates fast paths and congestion points (refer to diagram). In a stylized sense imagine that a polymer chain runs relatively straight before coming to a hairpin turn to form a U-shape. An electric field moves electrons rapidly up to the hairpin, only to stall.

Meanwhile imagine a similar U-shape polymer separated from the first by a tiny gap. Eventually, the electrons will jump that gap to go from the first fast path to the opposing fast path. One way to think about this is a traffic analogy, in which the electrons must wait for a traffic light to cross from one street, though the gap, before proceeding down the next.

Most importantly, perhaps, in terms of putting this knowledge to use, the Stanford theory includes a simple algorithm that begins to suggest how to control the process for making polymers – and devices out of the resulting materials – with an eye toward improving their electronic properties.

“There are many, many types of monomers and many variables in the process,” Spakowitz said. The model presented by the Stanford team simplifies this problem greatly by reducing it to a small number of variables describing the structural and electronic properties of semiconducting polymers. This simplicity does not preclude its predictive value; in fact, it makes it possible to evaluate the main aspects describing the physics of charge transport in these systems.

“A simple theory that works is a good start,” said Spakowitz, who envisions much work ahead to bring bending smart phones and folding e-readers to reality.

Gary Dickerson (L), president and CEO of Applied Materials and Tetsuro Higashi, chairman, president and CEO of Tokyo Electron.

Gary Dickerson (L), president and CEO of Applied Materials and Tetsuro Higashi (R), chairman, president and CEO of Tokyo Electron.

Applied Materials Inc. and Tokyo Electron Limited today announced Applied Materials agreed to merge with Tokyo Electron in a deal valuing the Japanese semiconductor production equipment maker at $9.3 billion, creating a giant in the chip and display manufacturing-tools sector. An all-stock combination values the new combined company at approximately $29 billion. The companies expect the transaction to close in mid to second half of 2014.

“Today, we are launching a new company and taking a bold step forward for our industry,” said Tetsuro Higashi, chairman, president and CEO of Tokyo Electron.

Under the terms of the agreement, Tokyo Electron shareholders will receive 3.25 shares of the new company for every Tokyo Electron share held. Applied Materials shareholders will receive 1 share of the new company for every Applied Materials share held. After the close, Applied Materials shareholders will own approximately 68 percent of the new company and Tokyo Electron shareholders approximately 32 percent.

Gary Dickerson, president and CEO of Applied Materials, said he believes they are creating a global innovator in precision materials engineering and patterning.

“We believe the combination will accelerate our momentum for profitable growth, increase the value we deliver to shareholders and create great opportunities for our employees,” said Dickerson.

The new company will have a shared leadership team. Tetsuro Higashi will serve as chairman, and Gary Dickerson will serve as chief executive officer.  The board will be made up of eleven directors with five directors appointed by each company and one additional director to be mutually agreed upon. Seven of the eleven directors will be independent. Bob Halliday of Applied Materials will serve as chief financial officer. The company will also have a new name, dual headquarters in Tokyo and Santa Clara, a dual listing on the Tokyo Stock Exchange and the NASDAQ, and will be incorporated in The Netherlands.

This merger could give the new company control of as much as a quarter of the entire market. Other top Applied Materials rivals include Veeco Instruments, KLA-Tencor, Lam Research Corp and ASM International.

In its official release, Applied Materials said the combined organization is intended to accelerate the existing strategic visions of Applied Materials and Tokyo Electron and increase the new company’s opportunity to enable major, future technology inflections and advance customers’ roadmaps in both semiconductor and display, citing the market growth in personal mobile electronics, such as smartphones and tablets, as a driver in the company’s strategic plans.

“We are building this new company in the spirit of a merger of equals,” said Dickerson. “For five decades, we have each made significant contributions to the semiconductor industry and we have deep respect for the capabilities that the other brings to this combination. Both companies have a strong heritage of customer service and an enduring commitment to push the boundaries of technology and engineering.  We share many common values and are confident we will execute together to achieve our strategic and financial goals.”

The companies expect to achieve $250 million in annualized run-rate operating synergies by the end of the first full fiscal year and $500 million in run-rate operating synergies realized in the third full fiscal year.  In addition, the new company expects to realize meaningful savings as a result of the new corporate structure. The new company intends to commence a $3.0 billion stock repurchase program targeted to be executed within 12 months following the close of the transaction. On a non-GAAP basis, taking into account the buyback, the transaction is expected to be EPS accretive at the end of the first full fiscal year after transaction close.

Goldman, Sachs & Co. acted as Applied Materials’ exclusive financial advisor, and Weil, Gotshal & Manges LLP, Mori, Hamada & Matsumoto, and De Brauw Blackstone Westbroek acted as legal counsel to Applied Materials.  Mitsubishi UFJ Morgan Stanley Securities Co., Ltd. acted as Tokyo Electron’s exclusive financial advisor, and Jones Day, and Nishimura & Asahi acted as legal counsel to Tokyo Electron.

It’s apparent that the world’s appetite for electronics has never been greater. That has increasingly taken the form of mobile electronics, including smartphones, tablets and tablets and the new “phablets.” People want to watch movies and live sports on their phones. They want their mobile devices to be “situationally aware” and even capable of monitoring their health through sensors. That drives higher bandwidth (6G is on the drawing board), faster data rates and a demand for reduced power consumption to conserve battery life. At the same time, “big data” and the internet of things (IoT) are here, which drives the demand for server networks and high performance semiconductors, as well as integrated sensors and inventive gadgets such as flexible displays and human biosensor networks.

All of this is pushing the semiconductor manufacturing industry and related industry (MEMS, displays, packaging and integration, batteries, etc.) in new directions. The tradeoffs that chipmakers must manager between power, performance, area and cost/complexity (PPAC) are now driven not by PCs, but by mobile devices.

In a keynote address at Semicon West 2013, Ajit Monacha, CEO of Global Foundries, expanded on his Foundry 2.0 concept, talking about how the requirements of mobile devices were, in fact, changing the entire semiconductor industry. He noted that the mobile business is forecast to be double the size of the PC market in 2016. The mobile business drives many new requirements, said Manocha, including power, performance and features, higher data rates, high resolution multicore processors and thinner form factors.

Manocha presented the audience with what he sees as today’s Big Five Challenges: cost, device architectures, lithography and EUV, packaging and the 450mm wafer transition. I don’t recall when cost wasn’t an issue, but an audience poll revealed that most people believe economic challenges will be the main factor limiting industry growth, not technical challenges. I agree, but I’m also thinking new applications will emerge particularly in the health field that could push the industry in yet another new direction.

Peter Singer, Editor-in-Chief

Following Samsung’s introduction of the first flexible organic light-emitting diode (OLED) products this year, demand for these elastic displays is expected to grow by more than a factor of four next year, with sales reaching nearly $100 million in 2014.
 
Global market revenue for flexible OLEDs will rise to $94.8 million in 2014, up from $21.9 million in 2013, according to a new report entitled “In-depth analysis for Technical Trends of Flexible OLED” from IHS Inc., a global source of critical information and insight.

The projected growth next year will equate to a 334 percent expansion from this year, as presented in the figure below, paving the way for much larger sales in the future.

Click image to see full screen.

Click image to see full screen.

OLEDs represent a major segment of the larger flexible display market, which in the coming years will also include liquid-crystal display (LCD) and electronic paper (e-paper) technology.

“The buzz about flexible displays has been growing louder, ever since Samsung Display demonstrated its Youm line of bendable OLED products at the Consumer Electronics Show in January,” said Vinita Jakhanwal, director of mobile and emerging displays and technology at IHS. “Samsung is expected to begin shipping its first flexible OLED display—a 5-inch screen—in the second half of this year.”

Samsung’s initial product is likely to be a first-generation flexible display, employing a non-glass substrate that yields superior thinness and unbreakable ruggedness. However, such displays are flat and cannot be bent or rolled. Flexible displays are expected to eventually evolve into rollable and foldable OLED screens that are likely to be introduced after 2016.

Even so, it is too early for flexible OLED panels to fully replace conventional OLED screens. This is because the plastic substrate, thin-film encapsulation and other related technologies for flexible OLED remain immature for immediate application. Moreover, manufacturing processes are still being tested.

“A wide range of complementary technologies are under development to accelerate the advancement of flexible displays,” Jakhanwal said. “The success of the flexible OLED market will ultimately be determined by the maturity of the materials and manufacturing processes that will enable large-volume production at reasonable costs.”

Electronic devices with touchscreens are ubiquitous, and one key piece of technology makes them possible: transparent conductors. However, the cost and the physical limitations of the material these conductors are usually made of are hampering progress toward flexible touchscreen devices.

Fortunately, a research collaboration between the University of Pennsylvania and Duke University has shown a new a way to design transparent conductors using metal nanowires that could enable less expensive — and flexible — touchscreens.

The research was conducted by graduate student Rose Mutiso, undergraduate Michelle Sherrott and professor Karen Winey, all of the Department of Materials Science and Engineering in Penn’s School of Engineering and Applied Science. They collaborated with graduate student Aaron Rathmell, and professor Benjamin Wiley of Duke’s Department of Chemistry.

Their study was published in the journal ACS Nano.

The current industry-standard material for making transparent conductors is indium tin oxide, or ITO, which is deposited as two thin layers on either side of a separator film. Contact, in the form of a fingertip or a stylus, changes the electrical resistance between the two ITO layers enough so that the device can register where the user is touching. While this material performs well, its drawbacks have led industrial and academic researchers to look for alternatives.

“There are two problems with ITO; indium is relatively rare, so its cost and availability are erratic, and, more importantly for flexible devices, it’s brittle,” Winey said. “We’d like to make touchscreens that use a network of thin, flexible nanowires, but predicting and optimizing the properties of these nanoscale networks has been a challenge.”

Metal nanowires are increasingly inexpensive to make and deposit; they are suspended in a liquid and can easily be painted or sprayed onto a flexible or rigid substrate, rather than grown in vacuum as is the case for ITO. The challenge stems from the fact that this process forms a random network, rather than a uniform layer like ITO.

A uniform sheet’s overall quality in this context depends on only two parameters, both of which can be reliably derived from the bulk material’s properties: its transparency, which should be high, and its overall electrical resistance, which should be low. To determine the electrical properties for a network of nanowires, however, one needs to know the nanowires’ length and diameter, the area they cover and a property known as contact resistance, which is the amount of resistance that results from electrons traveling from one wire to another. The details of how these four independent parameters impact the electrical and optical properties of nanowire networks have been unclear.

“What this means is that people will synthesize nanowires, deposit them in a network, measure the network’s overall electrical resistance and optical properties and then claim victory when they get a good one,“ Winey said. “The problem is that they don’t know why the good ones are good, and, worse, they don’t necessarily know why the bad ones are bad.”

For example, low overall resistance could be the result of a particular synthesis method that produced a few unexpectedly long nanowires, or a processing method that reduced the contact resistance between nanowires. Without a way of isolating these factors, researchers can’t determine which combination of parameters will be most successful.

Winey’s group has previously worked on simulating nanowire networks in three-dimensional nanocomposites, particularly the number of nanowires it takes to ensure there is a connected path from one end of the system to the other. Duke’s Wiley took note of this work and contacted Winey, asking her if she would be interested in developing two-dimensional simulations that could be applied to data from silver nanowire networks his group had fabricated.

With Wiley’s group able to provide the nanowire length, diameter and area fraction of their networks, Winey’s team was able to use the simulation to work backward from the network’s overall electrical resistance to uncover the elusive contact resistance. Alternative methods for finding the contact resistance are laborious and incompatible with typical network processing methods.

“Once we have reliable and relevant contact resistances, we can start asking how we can improve the overall sheet resistance by changing the other variables,” Mutiso said. “In playing with this simulation, we can see how much better our networks get when we increase the length of the nanowires, for example.”

The Penn team’s simulation provides further evidence for each variable’s role in the overall network’s performance, helping the researchers home in on the right balance of traits for specific applications. Increasing the coverage area of nanowires, for example, always decreases the overall electrical resistance, but it also decreases optical transparency; as more and more nanowires are piled on the networks appear gray, rather than transparent.

“For specific applications and different types of nanowires, the optimal area fraction is going to be different,” Winey said. “This simulation shows us how many nanowires we need to apply to reach the Goldilocks zone where you get the best mix of transparency and resistance.”

Future collaborations between Winey’s team at Penn and the Wiley group at Duke will use this simulation to test the effect of different processing techniques on nanowires, pinpointing the effect various post-deposition processing methods has on contact resistance and ultimately on overall sheet resistance.

“We can now make rational comparisons between different wires, as well as different processing methods for different wires, to find the lowest contact resistance independent of nanowire length, diameter and area fraction,” Winey said. “Now that we know where all the levers are, we can start adjusting them one at a time.”

In the next generation of modeling studies, the Penn team will consider several additional parameters that factor into the performance of nanowire networks for transparent conductors, including nanowire orientation, to mimic nanowire networks produced by various continuous deposition methods, as well as the degree to which individual nanowires vary in length or diameter.

The research was supported by the National Science Foundation and Penn’s Materials Science Research and Engineering Center.

Michelle Sherrott is now a doctoral student in materials science at the California Institute of Technology.

From data centers to ultra-mobile devices such as tablets, phones and wearables, computing segments are undergoing exciting and even game-changing transitions, said new Intel CEO Brian Krzanich during today’s opening session of the Intel Developer Forum. Krzanich laid out Intel’s vision and described how Intel is addressing each dynamic market segment – such as accelerating Intel’s progress in ultra-mobile devices – with new products over the next year and beyond, including a new, lower-power product family.

Krzanich said Intel plans to leave no segment untapped. “Innovation and industry transformation are happening more rapidly than ever before, which play to Intel’s strengths. We have the manufacturing technology leadership and architectural tools in place to push further into lower power regimes. We plan to shape and lead in all areas of computing.”

This year’s Intel Developer Forum marked the first keynote addresses by Krzanich and Intel President Renée James since assuming their new roles in May.

In her presentation, James envisioned a new era in which every device and every object computes, meaning that integrated computing solutions must be smaller, faster, more versatile and produced in higher volume.

“Semiconductor-based technology will continue to address the world’s most pressing problems and exciting opportunities, changing how we live our lives, run our cities and care for our health,” said James. “Intel has played a pivotal role in every previous technology transition and will continue to enable breakthroughs in the future.”

Accelerating progress in ultra-mobile devices

Krzanich said that Intel this week will introduce “Bay Trail,” Intel’s first 22nm system-on-a-chip (SoC) for mobile devices. “Bay Trail” is based on the company’s new low-power, high-performance Silvermont microarchitecture, which will power a range of innovative Android and Windows designs, most notably tablets and 2 in 1 devices.

Defining the expanding ultra-mobile segment as smartphones, tablets, 2-in-1 tablets that take on PC functions with add-on keyboards, and other devices beyond traditional mobile computers, he said that ultra-mobiles are a more dynamic segment than is often recognized.

“Smartphones and tablets are not the end-state,” he said. “The next wave of computing is still being defined. Wearable computers and sophisticated sensors and robotics are only some of the initial applications.”

As an example of how Intel will continue to use its manufacturing and architectural leadership to push further into lower power regimes, Krzanich announced the Intel Quark processor family. The new lower-power products will extend Intel’s reach to growing segments from the industrial Internet-of-Things to wearable computing. It is designed for applications where lower power and size take priority over higher performance.

Intel will sample form-factor reference boards based on the first product in this family during the fourth quarter of this year to help partners accelerate development of tailored, optimized solutions initially aimed at the industrial, energy and transportation segments.

As the next era of computing grows even more personal, wearables are a hotbed for innovation. Krzanich highlighted a bracelet as an example of a concept with reference designs under development, and said the company is actively pursuing opportunities with partners in this area.

In high-speed 4G wireless data communications, Krzanich said Intel’s new LTE solution provides a compelling alternative for multimode, multiband 4G connectivity, removing a critical barrier to Intel’s progress in the smartphone market segment. Intel is now shipping a multimode chip, the Intel XMM 7160 modem, which is one of the world’s smallest and lowest-power multimode-multiband solutions for global LTE roaming.

As an example of the accelerating development pace under Intel’s new management team, Krzanich said that the company’s next-generation LTE product, the Intel XMM 7260 modem, is now under development. Expected to ship in 2014, the Intel XMM 7260 modem will deliver LTE-Advanced features, such as carrier aggregation, timed with future advanced 4G network deployments. Krzanich showed the carrier aggregation feature of the Intel XMM 7260 modem successfully doubling throughput speeds during his keynote presentation.

He also demonstrated a smartphone platform featuring both the Intel XMM 7160 LTE solution and Intel’s next-generation Intel Atom SoC for 2014 smartphones and tablets codenamed “Merrifield.” Based on the Silvermont microarchitecture, “Merrifield” will deliver increased performance, power-efficiency and battery life over Intel’s current-generation offering.

Intel manufacturing leadership

Citing continued, rapid innovation for PCs of the future, Krzanich demonstrated a 14nm-based “Broadwell” system. “Broadwell,” set to begin production by the end of this year, will be the lead product made using Intel’s 14nm manufacturing process. The first “Broadwell” products will deliver higher performance, longer battery life and low platform power points for 2-in-1 and fanless devices, Ultrabooks and various PC designs.

Saying that Intel will bring the full weight of its manufacturing process and architectural leadership to the Intel Atom processor family, he confirmed Intel intends to bring its Intel Atom processor and other products based on the next-generation “Airmont” microarchitecture to market on Intel’s leading-edge 14nm process technology beginning next year. Timing will vary by product segment.

As the only company offering 3-D Tri-gate transistors and the only semiconductor manufacturer in production at 22nm, Intel leads the industry in transistor technology by about three years. With its coming 14nm process, Intel’s second process generation with 3-D Tri-gate transistors, the company will further extend this lead. Advanced 3-D Tri-gate transistors enable the improved performance and energy efficiency demanded by today’s spectrum of computing that ranges from ultra-mobiles to servers.

Re-architecting the datacenter

Intel’s datacenter business, which generates more than $10 billion in revenues annually, develops solutions that help businesses keep pace with the increasing demands for cloud services and for managing data generated from billions of users and connected devices worldwide. Intel’s goal is to re-architect the datacenter to enable a common, software-defined foundation for both datacenters and cloud service providers that spans servers, networking, storage and security.

Intel’s newest Intel Xeon processor family for datacenters will launch later today; last week Intel introduced a portfolio of datacenter products and technologies, including the second generation 64-bit Intel Atom C2000 product family of SoC designs for microservers and cold storage platforms (codenamed “Avoton”) as well as for entry networking platforms (codenamed “Rangeley”).

Computing to solve the world’s problems

In her comments, James highlighted smart cities and customized healthcare as examples of potential applications for technology that can turn computing theories into life-changing realities.

By 2050, 70 percent of the world’s population is expected to live in megacities, according to James. Developments in semiconductor technology will further advance machine-to-machine data management in smart cities. Intel is partnering with the cities of Dublin and London to build a reference solution that could revolutionize urban management, providing citizens with better cities and improved municipal services with lower costs.

“It’s one thing to install computing power in billions of smart objects,” said James. “What we’re doing is harder — making powerful computing solutions that turn data to wisdom and search for answers to the world’s most complex problems like cancer care. What we’ve seen so far is just a glimpse of how Intel technology could be used to help heal, educate, empower and sustain the planet.”

James also highlighted Intel’s supercomputing work as one of many examples where computational ability can transform healthcare, the largest sector of the global economy. Intel is working with the Knight Cancer Institute at Oregon Health and Science University on a project aimed at shrinking the cost and time to analyze human genetic profiles and create searchable maps of DNA in multiple dimensions.

“For the first time in modern medicine, the computing and technology side of health care is as important as the biological side,” James said. “The more computing power we can deliver at a feasible price point, the more lives are saved.”

OLED, a self-light-emitting diode, has been touted as the next big thing in display technology for its exceptional properties including no need for a backlight, wide viewing angle, quick responding speed and low current consumption. In particular, LG unveiled the world’s first 55-inch flat OLED TV in early 2013 followed by 55-inch curved OLED TV in April. With Samsung joining the fray with its latest 55-inch curved OLED TV, a fierce competition is expected in the OLED TV industry.

In anticipation of the OLED TV market coming into full bloom next year and encroaching the LCD TV market, developing mass production technology for OLED panels will soon emerge as a major issue. Extensive R&D efforts are under way to refine the OLED manufacturing process, namely, TFT backplane, color patterning, encapsulation and driving circuit. Especially, a lot of research has centered on the development of compensation circuit, as threshold voltage and IR-drop reduce the luminance of a driving TFT for an AMOLED display.

Read more: AMOLED panel shipments get boost from premium smartphones

OLED is a current driving circuit whose luminance properties are extremely sensitive to current changes. Driving TFTs for each pixel circuit of an AMOLED display can have different threshold voltages, which undermines the consistency of luminance of the panel.

In addition, when a VDD line passes each pixel circuit, it creates an IR-drop, resulting in a gradual decrease in pixel luminance towards the bottom of the panel that requires compensation.

Displaybank now offers a report examining a number of selected U.S. patents, analyzes patent application trends and patents filed by major companies and pinpoints key patents and new technology patents, offering a wide array of in-depth analyses. These analyses are expected to help keep pace with development trends for an AMOLED pixel driving circuit technology that compensates the threshold voltage and IR-drop as well as key patented technologies.

amoled shipments

Patent Application Trends
The number of U.S. patent applications for AMOLED pixel driving circuit (Vth and IR-drop compensation) technology is generally on the rise, with threshold voltage (Vth) compensation taking the biggest share. Top assignees are Samsung Display, Global OLED Technology, LG Display, Chimei Innolux, and Sharp, in the order of the number of applications.

amoled patent analysis

Key Patent Analysis
Out of 244 U.S. patents, those listed in the top 50 issued patents in terms of the number of forward citations were selected as key patents and subjected to an in-depth analysis: technology development trends, overview of key patents and case analysis.

PC outlook lowered again


August 30, 2013

Worldwide PC shipments are now expected to fall by -9.7 percent in 2013, further deepening what is already the longest market contraction on record, according to the International Data Corporation (IDC) Worldwide Quarterly PC Tracker. The new forecast reflects not only a continued expansion of mobile device options at the expense of PCs, but also marked the cessation of emerging market growth that the industry had come to rely on in recent years. The market as a whole is expected to decline through at least 2014, with only single-digit modest growth from 2015 onward, and never regain the peak volumes last seen in 2011.

While the results of the second quarter were in line with forecast, a number of issues led IDC to further downgrade its PC outlook. Aside from stubbornly depressed consumer interest, 2013 also marks the first year where emerging regions are expected to contract at a steeper rate than mature regions. Leading this trend is China’s revised forecast, which calls for a double-digit decline in shipments this year compared to 2012, as channel sources report high levels of stagnant inventory and continued enthusiasm for tablets and smartphones. The repercussions of a slowing China, anxiety over the possible tapering of the U.S. quantitative easing program, and weak intrinsic PC demand are among a litany of factors that have rippled across portions of other formerly strong-growth areas, leading emerging markets as a whole to see declines through at least 2014.

“The days where one can assume tablet disruptions are purely a First World problem are over,” said Jay Chou, senior research analyst, Worldwide Quarterly PC Trackers at IDC. “Advances in PC hardware, such as improvements in the power efficiency of x86 processors remain encouraging, and Windows 8.1 is also expected to address a number of well-documented concerns. However, the current PC usage experience falls short of meeting changing usage patterns that are spreading through all regions, especially as tablet price and performance become ever more attractive.”

Looking beyond 2014, IDC expects a slow rebound, driven in part by modest consumer refresh of systems whose lifecycle have dramatically lengthened in recent years, as well as businesses taking a first serious look beyond Windows 7. However, without an adequate mass of compelling applications, the PC market is poised to subsist primarily on lukewarm replacements in the future.

“The second quarter of 2013 was the third consecutive quarter where the U.S. market came through stronger than the worldwide market. This was largely due to some recovery in the overall economy and channel inventory replenishment,” said Rajani Singh, research analyst, Client Computing. “Following the stronger than expected 2Q13, we expect the second half of 2013 to restore some volume momentum driven largely by better channel involvement of top vendors and industry restructuring/alignment. We also anticipate operating system migration (Window XP to 7) will drive some volume in the commercial segment. Entry-level ultraslim systems and lower-priced convertibles will also be bright spots in an otherwise still troubled consumer market.”

Villemain-2083Michel Villemain, CEO, Presto Engineering, Inc.

The semiconductor industry is moving from a PC-centric, digital era to a communication and mobile world. This, combined with integration, is driving chips to interact more with the real world and to become increasingly analog. It has a profound impact on test and automated test equipment (ATE). Test equipment used to be rated by speed and timing accuracy, and priced by pins, but those are no longer defining features. The ability to support a wide range of analog and RF measurements is now the critical specification of a modern test solution.

Not so long ago the critical elements were the timing chip and the pin electronic IC. Both were advanced ASICs and defined the price of the equipment. Today, FPGAs support most speed and timing test requirements of current system on chip (SOC) devices, while bench instruments support most analog and RF demands. Bench systems are expensive and do not scale cost-effectively—especially for parallel test. The challenge is therefore to package instrumentation into application-specific test hardware that offers a cost-effective, per-channel solution that can be scaled into multi-site test solutions. The successful test solutions of tomorrow will be those that can offer a portfolio of dedicated analog and RF options, and provide variations as quickly as the market itself evolves.

The second major back-end transformation, driven by communication and mobility, is packaging. More analog circuitry means not only new, multidimensional packages (including 2.5D and 3D), but also more bare die that are directly integrated into modules. As traditional test flows include wafer sort (primarily for fab yield control) and final test (quality insurance), bare die require a known-good die flow implemented by wafer-level test (WLT).  New standards (802.11ad, 100/400G) and new RF bands will require probe technologies that can support up to 90GHz, combining reliable ohmic contact (signal integrity) with a gentle mechanical touch–especially on aluminum pads used by SiGe and CMOS processes.

Addressing these two challenges, for quickly deployed, dedicated analog/RF test solutions and reliable probing technologies, will allow cost-effective semiconductor solutions, then, in turn, deployment in volume of high-speed, high-bandwidth electronics solutions for communication and mobility.

<<Previous   1   2   3   4   5   6   7   8   9   10    Home>>

RichGoldmanRich Goldman, Vice President, Corporate Marketing and Strategic Alliances, Synopsys

Keeping up with Moore’s Law has always required significant investment and ingenuity, and this era brings additional challenges in device structures, materials and methodologies. As costs rise, a dwindling number of semiconductor companies can afford to build fabs at the leading edge. Those thriving include foundries, which spread capital expenses over revenue from many customers, and fabless companies, which leverage foundries’ capital investment rather than risking their own. Thriving, leading-edge IDMs are now the exception. From a market perspective, companies focused on segments such as mobile, automotive, mil-aero and medical are prospering.

With this environment as a backdrop, we see five trends dominating the year ahead and expect companies leading in or well positioned to address these areas to do well.

FinFETs. Chipmakers will no doubt keep us well informed as they progress through FinFET tapeouts and deliver production FinFET processes, touting their power and speed advantages for customers. Those early to market will press their advantage by pursuing aggressive FinFET roadmaps.

IP & subsystems. As devices grow more complex, integrating third-party IP has become mainstream. The trend for reuse of integrated, tested IP is beginning to expand upwards to systems, so that designers no longer need to redesign well-understood systems, such as memory, audio and sensor systems.

Internet of Things/sensors. The Internet of Things is poised to ignite huge growth in 2014. Sensors will emerge as a key enabler, connecting our physical world to computation in products that allow us to remotely control our surrounding environment. Meanwhile, a wide variety of sensor types will enable the mobile phone to continue subsuming and disrupting markets from cameras, satellite navigation systems and fitness devices, to flashlights and other applications.

Systems companies bringing IC design in house. Large companies successful in system-level design and development, such as Google, Microsoft and others, are bringing IC specification and/or design in house in the belief that that they can do the best job of IC design for their specific needs.

Advanced designs at both emerging and established process nodes. While leading-edge semiconductor makers drive forward on emerging process nodes, others are finding success by focusing on established nodes (28nm and above) that deliver required performance at reduced risk. Thus, challenging designs will emerge at both ends of the spectrum.

<<Previous   1   2   3   4   5   6   7   8   9   10    Next>>