Ludo Deferm, Executive Vice President, imec, Leuven, Belgium

For almost five decades, performance improvements and cost reduction of ICs have been cornerstones of the growth of the semiconductor industry. All these years, the semiconductor industry continued to scale down transistor dimensions, and, at the same time, maintained its historical 30 percent cost saving per logic gate, node after node.

Today, the question we are all concerned about is: can the industry keep up this trend? I fully expect that the technical roadmap for scaling, backed up by the ITRS roadmap, will continue for at least one decade. At the same time, the costs associated with such a further node progression will increase significantly. Equipment and R&D costs keep rising node after node, and continuous investments in fabs and equipment remain crucial if the industry wants to stay at the forefront of innovation. This may push the industry towards a new round of consolidation. Just as was the case with IC companies in the past, a consolidation of equipment suppliers could be a necessity to cope with the rising costs.

So the real question is: can the industry upgrade the IC performance and maintain its 30 percent cost saving for integrated circuits at the same time? The answer is not straightforward. It will depend, among others, on the complexity of the technologies and equipment we’ll need. One notable example, is of course, EUV. As EUV relaxes the need of multiple patterning, it would significantly reduce the processing cost per wafer. On the other hand, additional investment costs will come along with introducing EUV tools in the fab. Another worry is wafer size. Historically, the semiconductor industry used wafer scale-up as an additional means to maintain the cost reduction per transistor. But will it be advantageous this time to scale up towards 450mm wafers? In the coming years, industry leaders must make smart choices on breakthrough technologies and wafer size. More than ever, these decisions will be driven by economics.

The same trends that dominate the semiconductor industry can be witnessed at the R&D level as well. At imec, we perform CMOS R&D two generations ahead of industrial needs. 30 years ago, our initial focus was on the 1.25µm node. In 2014 our workhorse is the 7nm node and beyond. To print these extremely small features at an affordable price, we need the accuracy and “simplicity” of EUV lithography. Also, in answer to rising equipment costs, we need to further strengthen our collaboration with leading equipment and material suppliers of the IC industry, which more than ever will play a key role in our innovation hub. We believe this will reinforce the interaction between IC manufacturers and suppliers, and is essential for implementing the next steps in innovation and scaling.

2014 and 2015 will be crucial years. The industry will introduce and ramp up the 14nm technology node and use advanced FinFETs in an industrial processing technology. We will witness shortly the real cost of this advanced technology node, allowing us to learn for the future. At first, EUV will be part of a future technology. If its throughput can be improved and the tool becomes mature, it will gradually be introduced in the years to come and will create additional operational cost benefits compared to immersion lithography. For sure, 2014 will be an exciting year.

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Joe Cestari, President, Total Facility Solutions

As far as the outlook goes for 2014-2015, investments coming from the semiconductor and microelectronics industries are going to be pretty robust. However, it will likely remain a consolidated group effort, with a majority of the investments coming from the few major players in the industry. The latest semiconductor industry forecast suggests a 21% increase in semiconductor equipment sales in 2014 to almost $44 billion.

The key drivers are flash fab investments in China and Japan, as well as processor and foundry fab investments in Ireland and the U.S. Strong demand for smartphones and tablet devices and pent-up need for capacity will lead the industry to one of the highest levels ever for equipment investment. Although equipment spending will see strong growth, new fab investments are expected to drop in 2014, as fabs under construction in 2013 will be installing tools in 2014.

We continue to see a need for increased collaboration moving forward. Whether you are a believer in Moore’s Law or not, technology needs to continue to advance for the sake of cost and efficiency. However, this is not easily accomplished without some level of collaborative technology development. New efforts from the likes of the G450C and F450C should help drive the level of industry collaboration that will be necessary to advance technology in the years ahead.

The U.S. finds itself in a unique position; the market is still lingering with uncertainty as we deal with economic and political issues. However, US manufacturing costs are now on par with developing countries as land and labor continue to diminish as part of the overall capital and operating costs for a factory, so we should continue to see increased technology investments especially in the area of personal health and quality of life products.

In the coming years, we will need to find new ways to foster innovation. Gone are the days when start-ups were popping up left and right, but we need to continue to see this type of technological creativity and innovation to keep our industry alive. It’s our job now to help nurture a new generation of engineers that have that start-up mentality, so we can continue to grow this industry at the pace our consumers demand.

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Fastest Ge p-MOSFET: Germanium (Ge) is of interest as a potential material for the channels of future ultrafast CMOS devices because it offers high hole mobility that enables fast switching. However, because Ge is unstable in the air, it is typically covered, or passivated, with a silicon layer. Unfortunately, that increases the effective oxide thickness (EOT) on the Ge layer – a limiting factor for future devices which must be extremely dense with ultra-thin oxide layer. A research team led by the University of Tokyo will describe how they eliminated the Si passivation layer, and instead used a plasma post-oxidation technique to process a Ge channel’s surface and to optimize its interface properties with NiGeSi source/drains and high-k HfO₂/Al₂O₃/GeO_x and Ta gate stacks. They also discovered that the electron mobility in the Ge channel can be enhanced to the highest value ever achieved by asymmetrically straining it along its <110> crystal facet. They used these techniques to build the fastest Ge p-MOSFET ever reported, with record peak hole mobility of 763 cm²/Vs, at a thin EOT of just 0.82nm.

• The image at left above shows the fabrication process and device structure of s-Ge p-MOSFETs with self-aligned NiGeSi metal source/drains.
• The middle image is a TEM electron microscope cross-section of the interfacial layer.
• The image at right is a graph showing the effective mobility of the s-Ge -pMOSFETs.

(Paper #26.1, “High Mobility Strained-Ge pMOSFETs with 0.7-nm Ultrathin EOT using Plasma Post Oxidation HfO₂/Al₂O₃/GeO_x Gate Stacks and Strain Modulation,” R. Zhang et al, Univ. Tokyo)

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Visualizing CBRAM Filaments: CBRAM (conductive bridging RAM) is a promising non-volatile memory technology offering low-power operation, fast switching, high endurance and scalability. CBRAM’s redox (reduction-oxidation)-based electrochemistry relies on the fact that some amorphous materials with relatively large amounts of metal can behave as solid electrolytes. Under a voltage bias, metal ions in such an insulating amorphous layer can be reduced to form a conductive filament, or pathway, through it. The process can be reversed as needed, thereby enabling the reading and writing of memory data. Device performance is directly related to the properties of the conductive filament, but because the filament is internal to the solid layer, it is difficult to see, which makes it difficult to optimize. IMEC researchers will describe a 3D imaging approach that enables them to “see” how and where the filament forms in the amorphous layer. Similar to medical CAT scans which take multiple X-ray “slices” of internal organs and combine them to create 3D images, the IMEC approach uses conductive atomic force microscopy to take many slices of the amorphous layer. Each slice maps where electrical conduction is occurring, and the slices are then combined to render 3D images of the entire conductive filament.

The left image is a model of the slices, with blue showing the area of conduction in each slice.  The middle image is a model with the slices combined to show the filament.  The right image shows measurements of the conductive filament superimposed onto the computer model of it.

(Paper #21.6, “Conductive-AFM Tomography for 3D Filament Observation in Resistive Switching Devices,” U/ Celano et al, IMEC)

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The integration scheme allows for a reduced, more uniform diffusion distance, affording a more abrupt junction.

Record Silicon Nanowire MOSFETs: IBM researchers will describe a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured an incredible 30nm SiNW pitch (the spacing between adjacent nanowires) with a gate pitch of 60nm. Devices with a 90nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100nm— peak/saturation current of 400/976µA/µm, respectively, at 1 V. Although this work focused on NFETs, the researchers say the same fabrication techniques can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology. (Paper #20.2, “Density Scaling with Gate-All-Around Silicon Nanowire MOSFETs for the 10nm Node and Beyond,” S. Bangsaruntip et al, IBM)

The TEM electron microscope images above show: a) a cross section of a completed device through a gate, illustrating the spacer, epitaxial source/drain and contacts; (b) the cross section of a silicon nanowire (SiNW) decorated with a high-Z film to better show the nanowire’s boundary. The effective SiNW diameter shown is 12.8 nm; (c) a close up of the region of interest indicated in a), showing that the source/drain is epitaxially regrown from the cut face of the nanowire. The lattice planes in the epi region are registered to that of the original SiNW channel (parallel red dashed lines).

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300mm wafer-scale Ge FinFET: One of the main challenges to the use of Ge in advanced devices is the need for a cost-effective and manufacturable method to integrate highly crystalline Ge on a silicon wafer. At last year’s IEDM, TSMC described the successful integration of p-channel Ge FinFETs on 300mm silicon wafers using an aspect ratio defect-trapping method. This year, they improved the performance of p-channel Ge FinFETs by implementing: 1) an optimized 8-angstrom capacitance-equivalent thickness gate stack fabricated with a replacement-gate process; 2) a scaled-down fin width; and 3) the <110> crystal direction in the channel. Compared to any other reported non-silicon pFET, the 20nm-channel-length FinFETs demonstrated 2.5 times better subthreshhold slope performance, twice the on/off current and record electrical conductance of 2.7mS/µm.

The figure above shows that the transconductance (transport properties) of the p-channel Ge FinFETs is better than any previously reported data at a given subthreshold slope (short channel effects).  The right side of the figure then adjusts the transconductance for the difference in gate oxide thickness, and makes the point that it still shows the advantage over the previous work.

(Paper #20.1, “Scaled P-Channel Ge FinFET With Optimized Gate Stack and Record Performance Integrated on 300mm Si Wafers,” B. Duriez et al, TSMC)

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