SEM electron microscope images of: a) the silicon nanowire (SiNW)/CMOS hybrid biosensor; b) a SiNW biosensor in the first stage; c) a magnified view of it; d) SiNW channel region, showing a 35-nm width

a) TEM electron microscope images of the SiNW; b) photo of the fabricated chip; c) view of the experimental setup

Hybrid Nanowire/CMOS Biosensor: In the burgeoning field of genetic research, one thorny problem is how to accurately and cost-effectively detect DNA molecules in electrolyte solutions such as bodily fluids. Because DNA molecules are so small and because the background electrical “noise” inherent in ionic solutions tends to mask the presence of DNA, the usual way to detect DNA molecules is to label, or tag, them, with a variety of substances that can be detected by specialized probes. This adds cost and complexity, which a label-free direct detection system would avoid. Until now, a sensor to make that possible has been lacking, but researchers from Kookmin University in South Korea will describe a hybrid biosensor which, for the first time, integrates silicon nanowires and CMOS devices for such an application. It combines the exquisite sensitivity of nanowire surfaces with the noise-reduction and readout capabilities of CMOS logic circuitry, and does away with the need for DNA labeling. It demonstrated extremely impressive and consistent sensitivity, expressed as a change in output voltage of 1.2 V per 0.4 change in pH level, and as a 1.2 V change per 200 fM of DNA. (fM is a unit of length; 1 femtometer is 10⁻¹⁵ meter).

(Paper #14.5, “A Novel SiNW/CMOS Hybrid Biosensor for High Sensitivity/Low Noise,” J. Lee et al, Kookmin University)

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Novel Nanopore Sensor for DNA Sequencing: Many label-free nanopore-based DNA sequencing methods have been proposed because of their potential for high throughput and possible large-scale integration with standard semiconductor technology. At the IEDM, Hitachi researchers will describe a way to identify the four nucleotides that make up the DNA molecule, using a novel side-gated ultrathin field-effect transistor (FET) containing a nanopore (4-9 nm diameter), through which DNA strands pass. The nanopore sits between the transistor’s control gate and channel, to which it is adjacent. When voltage is applied to the control gate, channel current is generated near the edge of the channel close to the nanopore. This current is then modulated by the electrical charges each DNA nucleotide produces as it passes through the nanopore. Spatial resolution is determined by channel thickness, and the 55nm-thick channel has an ultrathin conductive layer (2-4nm) for high sensitivity. The device operated successfully in air, water and a KCl solution.

The image above left shows a schematic of the device; the middle image is a TEM electron microscope view of it; and the image on the right is a magnified view of the nanopore.

(Paper 14.3, “A Novel Side-Gated Ultrathin-Channel Nanopore FET (SGNAFET) Sensor for Direct DNA Sequencing,” I. Yanagi et al, Hitachi)

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This image is a schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2. The silicon layers serve as sacrificial material.

Nanofluidic Channels for Lab-on-Chip: Nanofluidic channels are useful for many biological and chemical applications, such as DNA sequencing, drug delivery and molecular sensing and detection. But in the effort to build a versatile lab-on-a-chip, it has been challenging to develop a wafer-scale nanochannel fabrication process compatible with CMOS technology. At the IEDM, IBM researchers will report on a CMOS-compatible 200mm wafer-scale sub-20nm nanochannel fabrication method that enables stretching, translocation and real-time fluorescence microscopy imaging of single DNA molecules. Through the use of sacrificial XeF₂ etching and various UV and e-beam lithography methods, sub-20nm patterns in silicon were converted into macro-scale fluidic ports, micro-scale fluidic feed channels, and nano-scale channels for DNA imaging. Gradient nanopillars were located in the channels to stretch DNA molecules prior to imaging them. Fluid wasn’t pumped through the channels, but instead was transported by the force of gravity. The researchers say their techniques lead to highly manufacturable structures and can produce chips for a variety of biological applications. (Paper #14.1, “200mm Wafer-Scale Integration of Sub-20nm Sacrificial Nanofluidic Channels for Manipulating and Imaging Single DNA Molecules,” C. Wang, S. Nam et al, IBM)

The above image shows the etching sequence of the silicon layers: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

Left: SEM electron microscope photo of silicon nanochannels.  Right: Optical photos showing A,B) nanochannels with vent holes on 1-2µm SiO₂ capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Fluorescence microscope images of DNA movement.

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Monolithic 3D Chip: An alternative to scaling is to expand vertically. Although 3D circuits often are made by stacking separate chips and connecting them with through-silicon vias (TSVs), some TSVs also have major disadvantages, including relatively large dimensions, parasitic capacitances and thermal mismatch issues. Researchers from Taiwan’s National Nano Device Laboratories avoided the use of TSVs by fabricating a monolithic sub-50nm 3D chip, which integrates high-speed logic and nonvolatile and SRAM memories. They built it from ultrathin-body MOSFETs isolated by 300nm-thick interlayer dielectric layers. To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then used a novel low-temperature chemical mechanical planarization (CMP) technique to thin and planarize the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated high performance – 3ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, making it potentially suitable for compact, energy-efficient mobile products.

The image above left illustrates the process flow, while the image on the right is a TEM electron microscope view of the 3D chip.

(Paper #9.3, “Monolithic 3D Chip Integrated with 500ns NVM, 3ps Logic Circuits and SRAM,” C–H. Shen et al, National Nano Device Laboratories)

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TSMC’s Integrated 16nm FinFET Technology Platform: Gain in transistor performance traditionally have come from scaling the devices smaller, but with today’s nanoscale-sized features that has become difficult. New transistor architectures such as multiple-gate devices are an alternative. When more than one gate controls the flow of electrons and holes though a transistor’s channel, better on/off control can be achieved. This allows for higher drive currents or lower supply voltages than otherwise possible, and makes the devices potentially suitable for a range of applications. (Multiple-gate devices are often called FinFETs because they feature a long, thin channel that resembles a shark’s fin.) At the IEDM, TSMC researchers will describe a 16nm FinFET process that by many measures is one of the world’s most advanced semiconductor technologies. In size, it is the first integrated technology platform to be announced below the 20nm node, with key features including a 48nm fin  pitch and the smallest SRAM ever incorporated into an integrated process—a 128Mb SRAM measuring 0.07 µm² per bit. In performance, it demonstrated either a 35% speed gain or a 55% power reduction over TSMC’s existing 28nm high-k/metal gate planar process, itself a highly advanced technology, and had twice the transistor density.  Short-channel effects were well-controlled, with DIBL <30 mV/V, saturation current of 520/525 uA/um at 0.75V (NMOS and PMOS, respectively) and off-current of 30 pA/um. It incorporates seven levels of high-density copper/low k interconnect and high-density planar MIM devices for noise control.

The left image shows that the 16nm FinFET achieved either a >35% speed gain or >55% power reduction over TSMC’s planar process.  The right set of images show a cross-section of the device’s 7-level metal copper/low-k architecture, with low resistance.

(Paper #9.1, “A 16nm CMOS FinFET Technology for Mobile SoC and Computing Applications,”  S-Y. Wu et al, Taiwan Semiconductor Manufacturing Co.)

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Triangular MOSFETs with InGaAs Channels: InGaAs is a promising channel material for high-performance, ultra low-power n-MOSFETs because of its high electron mobility, but multiple-gate architectures are required to make the most of it, because multiple gates offer better control of electrostatics. In addition, it is difficult to integrate highly crystalline InGaAs with silicon, so having multiple gates offers the opportunity to take advantage of the optimum crystal facet of the material for integration. A research team led by Japan’s AIST built triangular InGaAs-on-insulator n-MOSFETs with smooth side surfaces along the <111>B crystal facet and with bottom widths as narrow as 30 nm, using a metalorganic vapor phase epitaxy (MOVPE) growth technique. The devices demonstrated a high on-current of 930 µA/µm at a 300-nm gate length, showing they have great potential.

The graph above shows the devices’ high electron mobility.

(Paper 2.2, “High Electron Mobility Triangular InGaAs-OI nMOSFETs with (111)B Side Surfaces Formed by MOVPE Growth on Narrow Fin Structures,” T. Irisawa et al, AIST.)

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