Category Archives: Lithography

A lithographic method for TSV alignment to embedded targets was evaluated using in-line stepper self metrology, with TIS correction.

BY WARREN W. FLACK, Veeco Instruments, Plainview, NY and JOHN SLABBEKOORN, imec, Leuven, Belgium

Demand for consumer product related devices including backside illuminated image sensors, interposers and 3D memory is driving advanced packaging using through silicon via (TSV) [1]. The various process flows for TSV processing (via first, via middle and via last) affect the relative levels of integration required at the foundry and OSAT manufacturing locations. Via last provides distinct advantages for process integration, including minimizing the impact on back end of line (BEOL) processing, and does not require a TSV reveal for the wafer thinning process. Scaling the diameter of the TSV significantly improves the system performance and cost. Current via last diameters are approximately 30μm with advanced TSV designs at 5 μm [2].

Lithography is one of the critical factors affecting overall device performance and yield for via last TSV fabrication [2]. One of the unique lithography requirements for via last patterning is the need for back-to-front side wafer alignment. With smaller TSV diameters, the back-to- front overlay becomes a critical parameter because via landing pads on the first level metal must be large enough to include both TSV critical dimension (CD) and overlay variations, as shown in FIGURE 1. Reducing the size of via landing pads provide significant advantages for device design and final chip size. This study evaluates 5μm TSVs with overlay performance of ≤ 750nm.

Alignment, illumination and metrology

Lithography was performed using an advanced packaging 1X stepper with a 0.16 numerical aperture (NA) Wynne Dyson lens. This stepper has a dual side alignment (DSA) system which uses infrared (IR) illumination to view metal targets through a thinned silicon wafer [3]. For the purposes of this study and its results, the wafer device side is referred to as the “front side” and the silicon side is referred to as the “back side.” The side facing up on the lithography tool is the back side of the TSV wafer, as shown in FIGURE 2.

The top IR illumination method for viewing embedded alignment targets, shown in Fig. 2, provides practical advantages for integration with stepper lithography. Since the illumination and imaging are directed from the top, this method does not interfere with the design of the wafer chuck, and does not constrain alignment target positioning on the wafer. The top IR alignment method illuminates the alignment target from the back side using an IR wavelength capable of transmitting through silicon (shown as light green in FIGURE 2) and the process films (shown in blue). In this configuration the target (shown in orange) needs to be made from an IR reflective material such as metal for optimal contrast. The alignment sequence requires that the wafer move in the Z axis in order to shift alignment focus from the wafer surface to the embedded target.

Back-to-front side registration was measured using a metrology package on the lithography tool which uses the DSA alignment system. This stepper self metrology package (DSA-SSM) includes routines to diagnose and compensate for measurement error from having features at different heights. For each measurement site the optical metrology system needs to move the focus in Z between the resist feature and the embedded feature. Therefore angular differences between the Z axis of motion, the optical axis of the alignment camera, and the wafer normal will contribute to measurement error for the tool [3]. The quality of the wafer stage motion is also very important because a significant pitch and roll signature would result in a location dependent error for embedded feature measurement, which would complicate the analysis.

If the measurement operation is repeatable and consistent across the wafer, then a constant error coming from the measurement tool, commonly referred to as tool induced shift (TIS), can be characterized using the method of TIS calibration, which incorporates measurements at 0 and 180 degree orientations. The TIS error—or calibration—is calculated by dividing the sum of offsets for the two orientations by two [4]. While the TIS calibration is effective for many types of measurements for planar metrology, for embedded feature metrology, the quality of measurement and calibration also depend on the quality and repeatability of wafer positioning, including tilt. In previous studies, the registration data obtained from the current method were self consistent and proved to be an effective inspection method [3, 5]. However given the dependencies affecting TIS calibration for embedded feature metrology, it is desirable to confirm the registration result using an alternate metrology method [5]. In order to independently verify the DSA-SSM, overlay data dedicated electrical structures were designed and placed on the test chip.

Electrical verification of TSV alignment is performed after complete processing of the test chip and relies on the landing position of a TSV on a fork-to-fork test structure in the embedded metal 1 (damascene metal). When the TSV processing is complete the copper filled TSV will make contact with metal 1. The TSV creates a short between the two sets of metal forks, allowing measurement of two resistance values which can be translated into edge measurements. For the case of ideal TSV alignment, the two resistances are equal. The measurement resolution of the electrical structure is limited by the pitch of the fork branches. In this study resolution is enhanced by creating structures with four different fork pitches. A similar fork-to-fork structure rotated 90 degrees is used for the Y alignment. Using this approach both overlay error and size of the TSV in both X and Y can be electrically determined [6].

Experimental methods

This study scrutinizes image placement performance by examining DSA optical metrology repeatability after TSV lithography, and then comparing this optical registration data with final electrical registration data.

The TSV-last process begins with a 300mm device wafer with metal 1, temporarily bonded to a carrier for mechanical support as shown in FIGURE 3. The back side of the silicon device wafer (light green) is thinned by grinding and then polished smooth by chemical mechanical planarization (CMP). The TSV is imaged in photoresist (red) and etched through the thinned silicon layer. FIGURE 3 depicts the complete process flow including the TSV, STI and PMD etch, TSV fill, redis- tribution layer (RDL) and de-bonding from carrier. The aligned TSV structure must land completely on the metal 1 pad (dark blue).

TSV lithography is done with a stepper equipped with DSA. The photoresist is a gh-line novolac based positive- tone material requiring 1250mJ/cm2 exposure dose with a thickness of 7.5μm [5]. The TSV diameter is 5μm, and the silicon thickness is 50μm. TSV etching of the silicon is performed by Bosch etching [7]. Tight control of lithography and TSV etching is required to insure that vias land completely on metal 1 pads, as shown in FIGURE 1.

Acceptable features for DSA-SSM metrology need to fit the via process requirements for integration. Since the TSV etch process is very sensitive to pattern size and density, the TSV layer is restricted to one size of via, and the DSA-SSM measurement structure is constructed using this shape. The design of the DSA-SSM measurement structure uses a cluster of 5μm vias with unique grouping and clocked rotation to avoid confusion with adjacent TSV device patterns during alignment.

FIGURE 4 shows two different focus offsets of DSA camera images of the overlay structure. For this structure, the reference metal 1 feature (outlined by the blue ring) and the resist pattern feature (outlined by the red ring) are not in the same focal plane. For a silicon thickness of 50μm, focusing on one feature will render the other feature out of focus, requiring each feature to have its own focus offset, which is specified in the metrology measurement recipe.

Optical registration process control

This study leveraged a sampling plan of 23 lithography fields with 5 measurements per field, resulting in a total of 115 measurements per wafer. Since the full wafer layout contains 262 fields, this sampling plan provides a good statistical sample for monitoring linear grid and intrafield parameters.

In the initial run, the overlay settings were optimized using the DSA-SSM metrology feedback and then the parameters were fixed to investigate overlay stability over a nine-week period. Trend charts for mean and 3σ for seven TSV lots are shown in FIGURE 5. Each measurement lot consists of 8 wafers, with 115 measure- ments per wafer, and all data is corrected for TIS on a per lot basis using measurements of a single wafer at 0 and 180 degree orientations [3]. The lot 3σ is consistently less than 600nm over the nine-week period. There appears to be a consistent small Y mean error (blue diamond) that could be adjusted to improve subsequent overlay results. With a Y mean correction applied, the registration data shows mean plus 3σ ≤ 600nm.

Validating TSV alignment and in-line optical metrology

Two TSV last test chip wafers were completely processed to the stage that they can be electrically measured. TABLE 1 shows the registration numbers confirming a good match between the two metrology methods. It is important to note that an extra translation step is performed between the optical and the electrical measurement: the TSV etch.

In this analysis the TSV etch is assumed to be perfectly vertical. From the data we can conclude that the TSV etch is indeed vertical enough not to interfere with the overlay data. Otherwise this would show as translation or scaling effects between the two metrology methods.

Conclusions

The lithographic method for TSV alignment to embedded targets was evaluated using in-line stepper self metrology, with TIS correction. Registration data was collected over a nine-week period to characterize the stability of TSV alignment. With corrections applied, the registration data demonstrates mean plus 3σ ≤ 600nm. The in-line optical registration data was then correlated to detailed electrical measurements performed on the same wafers at the end of the process to provide independent assessment of the accuracy of the optical data. Good correlation between optical and electrical data confirms the accuracy of the in-line optical metrology method, and also confirms that the TSV etch through 50μm thick silicon is vertical.

References

1. Vardaman, J. et. al., TechSearch International: Advanced Packaging Update, July 2016.
2. Van Huylenbroeck, S. et. al., “Small Pitch High Aspect Ratio Via Last TSV Module”, The 66th Electronic Components and Technology Conference, Los Vegas, NV, May 2016.
3. Flack, W. et. al., “Optimization of Through Si Via Last Lithography for 3D Packaging”, Twelfth International Wafer- Level Packaging Conference, San Jose, CA, October 2015.
4. Preil, M. et. al, “Improving the Accuracy of Overlay Measurements through Reduction of Tool and Wafer Induced Shifts”, Metrology, Inspection, and Process Control for Microlithography Proceedings, SPIE 3050, 1997.
5. Flack, W. et. al., “Verification of Back-to-Front Side Alignment for Advanced Packaging”, Ninth Interna- tional Wafer-Level Packaging Conference, Santa Clara, CA, November. 2012.
6. Flack, W. et.al., “Overlay Performance of Through Si Via Last Lithography for 3D Packaging”, 18th Electronics Packaging Technology Conference, Singapore, December 2016
7. Slabbekoorn, J. et. al, “Bosch Process Characterization For Donut TSV’s” Eleventh International Wafer-Level Packaging Conference, Santa Clara, CA, November 2014.

The IC industry has been on a mission to pare down older capacity (i.e., ≤200mm wafers) in order to produce devices more cost-effectively on larger wafers.  In its recently released Global Wafer Capacity 2019-2023 report, IC Insights shows that due to the surge of merger and acquisition activity in the middle of this decade and with more companies producing IC devices on sub-20nm process technology, suppliers are eliminating inefficient wafer fabs. Over the past ten years (2009-2018), semiconductor manufacturers around the world have closed or repurposed 97 wafer fabs, according to findings in the new report.

Figure 1 shows that since 2009, 42 150mm wafer fabs and 24 200mm wafer fabs have been shuttered. 300mm wafer fabs have accounted for only 10% of total fab closures since 2009.  Qimonda was the first company to close a 300mm wafer fab after it went out of business in early 2009.

Figure 1

Three 150mm wafer fabs were closed or repurposed in 2018.  Two of these fabs belonged to Renesas.  Renesas closed one fab in Konan, Kochi, Japan that produced analog, logic, and some older microcomponent devices.  A second Renesas fab in Otsu, Shiga, Japan was repurposed and now makes only optoelectronic devices.  A third fab, Fab 1 belonging to Polar Semiconductor (now Sanken) in Bloomington, Minnesota, also was closed.  This fab manufactured analog, discretes, and offered some foundry services.

Given the skyrocketing cost of new wafer fabs and manufacturing equipment, and as more IC companies transition to a fab-lite or fabless business model, IC Insights anticipates there will be additional fab closures in the next few years.  Five closures/repurposed fabs have already been publicly announced. Samsung’s 300mm memory fab (Line 13) will be fully converted this year to produce image sensors and TI’s 200mm analog GFAB in Greenock, Scotland, is expected to close by June 2019.  Renesas plans to close two 150mm fabs (Otsu, Shiga and Ube, Yamaguchi, Japan) in 2020 or 2021, and Analog Devices plans to close its 150mm wafer fab in Milpitas, California in February 2021.

Semiconductor suppliers in Japan have closed a total of 36 wafer fabs since 2009, more than any other country/region.   In the same period, 31 fabs were closed in North America, 18 fabs were shuttered in Europe, and 12 wafer fabs were closed throughout the Asia-Pacific region (Figure 2).  With 36 fab closures and very few new fabs going up there, it is little wonder that Japan now accounts for only 5% of worldwide semiconductor capital spending.

Figure 2

ON Semiconductor (Nasdaq: ON) today announced its top distribution partners for 2018. These awards honor the distributor in each region that led overall channel sales, grew market share, captured increased sales of products and scored highly on overall process excellence in an evolving semiconductor market.

The top 2018 distribution partners are:

  • Americas: Future Electronics
  • APAC: WPI
  • EMEA: Avnet/Silica
  • Japan: OS Electronics
  • Global High Service Distributor: Mouser Electronics
  • Global Distributor: Avnet

ON Semiconductor is an industry leader in leveraging partnerships in the global distribution channel. Approximately 60 percent of the company’s business results from distribution sales, and distribution remains the fastest channel to market. Over the past few years, ON Semiconductor has grown distribution sales, which has attributed to over half of the company’s revenue dating back to 2015.

“Distribution sales accounted for approximately 60 percent of ON Semiconductor’s 2018 annual revenues,” said Jeff Thomson, vice president of global channel sales for ON Semiconductor. “The support of our worldwide distribution partners is fundamental to the success of our company’s ongoing plans to increase market penetration and continue revenue growth at a faster pace than the industry. The collaborative relationships and progressive sales programs we foster with our channel partners are an integral part of comprehensive solution selling. As advocates of these goals, each of the 2018 distribution partner award winners successfully grew product sales, generated significant new business, and effectively supported both our customers’ needs and our company initiatives for operational excellence. We thank our outstanding channel partners for their valuable contributions throughout 2018 and look forward to continued success in the coming year.”

In the third quarter of 2018, ON Semiconductor announced a monumental milestone in the company’s history by reaching over $1 billion in distribution resales. ON Semiconductor distribution partners, and this year’s honorees, have been instrumental to this tremendous milestone. In addition to this accomplishment, ON Semiconductor was recognized in 2018 as a Fortune 500 company, was named as one of Fortune’s 100 Fastest Growing Companies, was listed on the Dow Jones Sustainability Index and received recognition from Ethisphere for the fourth year in a row as one of the World’s Most Ethical Companies.

The IBM (NYSE:IBM) board of directors today elected Admiral Michelle J. Howard to the board, effective March 1, 2019.

Admiral Howard, 58, is a former United States Navy officer and the first woman to become a four-star admiral. She was the first African-American woman to command a ship in the United States Navy (the USS Rushmore). Admiral Howard was also the first African-American and the first woman to be named Vice Chief of Naval Operations when she was appointed to that role by the President in July 2014. She retired in December 2017 as the commander of United States Naval Forces in Europe and Africa and the Allied Joint Forces Command in Naples, Italy, after a distinguished 35-year career.

Admiral Howard is currently the J.B. and Maurice C. Shapiro Visiting Professor of International Affairs at George Washington University, where she teaches in the areas of cybersecurity and international policy.

Ginni Rometty, IBM chairman, president and chief executive officer, said: “Admiral Howard is a groundbreaking leader with a distinguished career in military service. Her leadership skills, international perspective and extensive experience with cybersecurity and information technology will make her a great addition to the IBM board.”

Admiral Howard graduated from the United States Naval Academy in 1982 and from the United States Army’s Command and General Staff College in 1998 with a master’s degree in military arts and sciences. She was the first female graduate of the Naval Academy to be promoted to flag officer.

She has received honorary degrees from Rensselaer Polytechnic Institute, American Public University and North Carolina State University, and is the recipient of many honors, including the NAACP Chairman’s Image Award, the French Legion of Honor and the KPMG Inspire Greatness Award.

By Serena Brischetto

The SEMI Europe Industry Strategy Symposium (ISS Europe) returns in Milan, Italy, this year from 31st March to 2nd April, 2019 to explore new opportunities and challenges in the digital economy. Serena Brischetto of SEMI spoke with GreenWaves Technologies CEO and co-founder Loïc Lietar about the semiconductor start-up and its Internet of Things (IoT) ultra-low-power processing technology ahead of the summit.

SEMI: What are the mission and vision of GreenWaves Technologies?

Lietar: GreenWaves Technologies is a fabless semiconductor start-up that is designing disruptive ultra-low power embedded solutions for image, sound and vibration artificial intelligence (AI) processing in sensing devices. It was founded in late 2014 with the mission to enable the market for intelligent in-device sensors using ultra-low energy and cost-efficient computing solutions. As a result, the GreenWaves GAP8 is the industry’s first ultra-low-power processor to enable battery-operated AI in Internet of Things (IoT) applications.

SEMI: How did you move from the semiconductor industry to the start-up ecosystem?

Lietar: I worked 25 years for STMicroelectronics then four years ago left because a project didn’t materialize. At the same time, I became involved a bit by chance in the founding of GreenWaves, which turned out to be an amazing journey that I rapidly got entirely – and deadly – committed to.

SEMI: Semiconductors are usually not associated with the idea of start-up. What is the key to the success of GreenWaves and its positioning?

Lietar: Start-ups have played a significant role in the formation of our industry and in bringing innovations and disruptions to the market. But as it became more complicated to finance start-ups because of exploding development costs, the number of semiconductor start-ups shrank significantly in the past 10 years.

At GreenWaves we develop and sell IoT application processors – processors tuned for a given class of applications. In our case, we focused on machine learning inference processors and more generally signal processing and IoT for ultra-low power. We typically process and analyze images, sounds and vibrations and our technology is more than one order of magnitude more energy efficient than existing processors. For example, our processor, coupled with an infra-red sensor, can count the number of people present in a room once a minute for more than five years on a single charge.

Our architecture uses RISC-V cores. This free and open Instruction Set Architecture is seeing huge momentum and a rapidly growing community. Second, we leverage an open source project called PULP developed by the Italian Università di Bologna and the Federal Polytechnical School ETH in Zurich. While open source is a well-established model for software, this is pretty unchartered territory in the semiconductor industry. It is working very well for us, as we benefit from robust technology we can incrementally innovate on. This is why we have been able to develop our first product with 4 million Euro.

Competition is now emerging, and this is a good sign: We are not alone in believing in this market but we remain very differentiated!

SEMI: One of the reasons why semiconductor start-ups were no longer attractive to VCs is the amount of capital that start-ups need to invest. Did public funding help you too?

Lietar: Yes, public funding played a crucial role at the beginning. We received rather classically 300K Euro of French grants and then we were lucky enough to win a very selective H2020 grant, the SME instrument, for 1.2M€. In France there is a very powerful scheme of research tax credit that covers more than 30 percent of our R&D costs and French banks know how to lend money to start-ups, with a state warranty.

Source: SEMI Blog

The eBeam Initiative, a forum dedicated to the education and promotion of new semiconductor manufacturing approaches based on electron beam (eBeam) technologies, today announced that ASML Holding N.V. (ASML) has joined the eBeam Initiative. As one of the world’s leading manufacturers of chip-making equipment, ASML will provide its valuable perspective to the educational activities of the eBeam Initiative within the semiconductor photomask and lithography supply chain.

In 2009, the eBeam Initiative was launched to provide a strong voice and educational platform for eBeam technology within the photomask and semiconductor design and manufacturing community. Instrumental to its efforts, the eBeam Initiative leverages its annual perceptions and mask maker surveys to confirm key trends to help guide the industry forward in supporting the introduction of new eBeam technologies. In achieving a new milestone with 50 member companies, the eBeam Initiative continues its charter to enable industry collaboration to advance the eBeam technology ecosystem.

Today, during the SPIE Advanced Lithography Conference being held at the San Jose Convention Center, the eBeam Initiative will host its annual luncheon event featuring presentations from Dr. Yu Cao, senior vice president of ASML; Dr. Harry Levinson, principal at HJL Lithography; and Dr. Leo Pang, chief product officer and executive vice president at D2S. These industry luminaries will cover several eBeam-related topics key to the future success of photomask manufacturing and lithography, including: computations for EUV lithography; GPU-accelerated simulation enabling applied deep learning for photomasks; and applications of machine learning in computational lithography. Copies of these presentations will be made available after February 26 on the eBeam Initiative website at www.ebeam.org.

ASML will provide valuable perspectives to the eBeam Initiative,” stated Aki Fujimura, CEO of D2S, managing company sponsor of the eBeam Initiative. “ASML has significant expertise in modeling and simulation of the lithography process as well as eBeam metrology and inspection, the latter through the acquisition of HMI. This offers expanded insights for eBeam mask writing around metrology and inspection, as well as computational lithography. To continue to develop new innovations in eBeam technology, the need for collaborative industry efforts like those of the eBeam Initiative have never been more important. We are very pleased to welcome ASML as our newest contributor to our mission to provide industry collaboration for new semiconductor manufacturing approaches that accelerate the use of eBeam technology.”

North America-based manufacturers of semiconductor equipment posted $1.89 billion in billings worldwide in January 2019 (three-month average basis), according to the January Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 10.5 percent lower than the final December 2018 level of $2.10 billion, and is 20.8 percent lower than the January 2018 billings level of $2.37 billion.

“January billings of North American equipment manufacturers declined 10 percent when compared to the prior month,” said Ajit Manocha, president and CEO of SEMI. “Weakening smartphone demand and high inventory levels are eroding capital equipment investments, especially by memory suppliers.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg.)
Year-Over-Year
August 2018
$2,236.8
2.5%
September 2018
$2,078.6
1.2%
October 2018
$2,029.2
0.5%
November 2018
$1,943.6
-5.3%
December 2018 (final)
$2,104.0
-10.5%
January 2019 (prelim)
$1,896.4
-20.8%

Source: SEMI (www.semi.org), February 2019

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

The advancement of the IC industry hinges on the ability of IC manufacturers to continue offering more performance and functionality for the money.  As mainstream CMOS processes reach their theoretical, practical, and economic limits, lowering the cost of ICs (on a per-function or per-performance basis) is more critical and challenging than ever. The 500-page, 2019 edition of IC Insights’ McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry (released in January 2019) shows that there is more variety than ever among the logic-oriented process technologies that companies offer.  Figure 1 lists several of the leading advanced logic technologies that companies are presently using. Derivative versions of each process generation between major nodes have become regular occurrences.

Figure 1

Intel — Its ninth-generation processors unveiled in late 2018 have the code-name “Coffee Lake-S” or, sometimes called “Coffee Lake Refresh.” Intel says these processors are a new generation of products, but they seem to be more of an enhancement of the eighth-generation products.  Details are scarce, but these processors appear to be manufactured on an enhanced version of the 14nm++ process, or what might be considered a 14nm+++ process.

Mass production using its 10nm process will ramp in 2019 with the new “Sunny Cove” family of processors that it unveiled in December 2018.  It appears that the Sunny Cove architecture has essentially taken the place of the 10nm Cannon Lake architecture that was supposed to be released in 2019.  In 2020, a 10nm+ derivative process is expected to go into mass production.

TSMC — TSMC’s 10nm finFET process entered volume production in late 2016 but it has moved quickly from 10nm to 7nm.  TSMC believes the 7nm generation will be a long-lived node like 28nm and 16nm.

TSMC’s 5nm process is under development and scheduled to enter risk production in the first half of 2019, with volume production coming in 2020.  The process will use EUV, but it will not be the first of TSMC’s processes to take advantage of EUV technology.  The first will be an improved version of the company’s 7nm technology.  The N7+ process will employ EUV only on critical layers (four layers), while the N5 process will use EUV extensively (up to 14 layers).  N7+ is scheduled to enter volume production in the second quarter of 2019.

Samsung — In early 2018, Samsung started mass production of a second-generation 10nm process called 10LPP (low power plus). Later in 2018, Samsung introduced a third-generation 10nm process called 10LPU (low power ultimate) that provided another performance increase.  Samsung uses triple patterning lithography at 10nm.  Unlike TSMC, Samsung believes its 10nm family of processes (including 8nm derivatives) will have a long lifecycle.

Samsung’s 7nm technology went into risk production in October 2018.  The company skipped offering a 7nm process with immersion lithography and decided instead to move directly to a EUV-based 7nm process.  The company is using EUV for 8-10 layers at 7nm.

GlobalFoundries — GF views and markets its 22nm FD-SOI process as being complementary to its 14nm finFET technology.  The company says the 22FDX platform delivers performance very close to that of finFET, but with manufacturing costs the same as 28nm technology.

In August 2018, GlobalFoundries made a major shift in strategy by announcing it would halt 7nm development because of the enormous expense in ramping production at that technology node and because there were too few foundry customers planning to use the next-generation process.  As a result, the company shifted its R&D efforts to further enhance its 14nm and 12nm finFET processes and its fully depleted SOI technologies.

For five decades, there have been amazing improvements in the productivity and performance of integrated circuit technology.  While the industry has surmounted many obstacles put in front of it, it seems the barriers keep getting bigger.  Despite this, IC designers and manufacturers are developing solutions that seem more revolutionary than evolutionary to increase chip functionality.

pSemi Corporation today announced that its parent company and executive leadership has approved the recommendation of Chairman and Chief Executive Officer Jim Cable for an evolution of the company’s senior leadership structure.  Under the new structure, the company’s current VP of Product Marketing, Sumit Tomar, will succeed Jim as CEO, effective July 1, 2019.  Jim will continue as Chairman and Chief Technology Officer.  In addition, Jim will remain as global semiconductor R&D director for the parent company Murata Manufacturing.

“I am very proud of what we have accomplished here at pSemi Corporation.  In our over 30 years of innovation, we have consistently pushed the envelope of technology.  Now it is time to ensure we can continue to compete just as strongly in the future.  To that end, I have selected an internal candidate to succeed me as CEO,” says Jim Cable.  “I have watched Sumit in action, he knows our company and I am 100 percent committed to a successful transition for him and the company. We did an extensive external search and decided that the right choice was already here.”

Tomar is a 20-year industry veteran with a proven track record of bringing successful products to the market.  An expert in the RF ecosystem, Tomar has a solid understanding of RF products and has driven product execution from inception to production for hundreds of market-shaping products. From 2012 to 2016, Tomar served as the general manager of Qorvo’s wireless infrastructure business unit. In addition, he worked in RF product management at Texas Instruments, Sierra Monolithics and Skyworks. His product marketing experience spans 4/5G smartphone and radio access networks, automotive semiconductors, 802.11ax access points, SDN/NFV for data centers, and machine learning and artificial intelligence for mobile edge networks. In 2016, he co-founded C-RAN Inc., a startup that is developing a 5G RF system prototype. Tomar holds a Master of Science in electrical engineering and completed the StanfordExecutive Management Program. He joined pSemi Corporation in August of 2017 as the Vice President of Product Marketing.  “Sumit has been instrumental in managing our relationship with Murata to ensure that we support our parent company while continuing to innovate new products in the RF space,” continues Cable.

“Murata believes that successful succession planning requires careful consideration and attention to ensure a strong talent pipeline,” says Norio Nakajima, senior executive vice president and board member for Murata Manufacturing. “Jim’s selection of Sumit is an ideal example of outstanding succession planning.  I have had the pleasure of watching Sumit in action and I am convinced he is the right person to succeed Jim.”

GLOBALFOUNDRIES today announced that the company’s mobile-optimized 8SW RF SOI technology platform has delivered more than a billion dollars of client design win revenue since its launch in September 2017. With yields and performance exceeding client expectations, 8SW is enabling designers to develop solutions that offer extremely fast downloads, higher quality connections and reliable data connectivity for today’s 4G/LTE Advanced operating frequencies and future sub-6 GHz 5G mobile and wireless communication applications.

As the industry’s first 300mm RF SOI foundry solution, 8SW delivers significant performance, integration and area advantages, with best-in-class low-noise amplifier (LNA) and switch performance which all together improve integration solutions in the front-end module (FEM). The optimized RF FEM platform is tailored to accommodate aggressive LTE and sub-6 GHz standards for FEM applications, including 5G IoT, mobile device and wireless communications.

“At Qorvo, we continuously expand upon our industry-leading RF portfolio to support all pre-5G and 5G architectures, as such we require the best available technologies to enable us to deliver top-notch solutions with the broadest range of connectivity in sub-6 GHz and mmWave 5G,” said Todd Gillenwater, Qorvo CTO. “GF’s 8SW technology delivers a mix of performance, integration and area advantages in FEM switches and LNAs, giving us a great platform for our world-class products.”

“As new high-speed standards, including 4G LTE and 5G, continue to grow in complexity, innovation in RF Front End radio design must continue to deliver performance commensurate with growing network, data and application demands,” said Bami Bastani, senior vice president of business units at GF. “GF continuously builds on our extensive RF SOI capabilities that are providing our clients a competitive market advantage with first time design success, optimal performance, and the shortest time to market.”

According to Mobile Experts, the mobile RF front-end market is estimated to reach $22 billion in 2022, with a CAGR of 8.3 percent. With more than 40 billion RF SOI chips shipped thru 2018, GF is uniquely positioned to deliver an expanding RF portfolio for a broad range of high-growth applications such as automotive, 5G connectivity and the Internet of Things (IoT).

“Radio complexity promises to increase for both sub-6 GHz and mmWave, driving tight integration of multiple RF functions,” said Joe Madden, Principal Analyst at Mobile Experts. “The market needs RF solutions with high efficiency and linearity performance, but also using scalable processes on large wafers. GF has established an RF SOI process that will enable longer-term market expansion.”

GF combines legacy RF expertise and the industry’s most differentiated RF technology platform spanning advanced and established technology nodes, to help clients develop 5G connectivity solutions for next-generation products.

GF will present its 5G-ready RF solutions with industry experts at MWC Barcelona on February 25 at the NEXTech Labs Theater, in the Fira Gran Via Convention Center, in Barcelona Spain. For more information, go to globalfoundries.com.