Category Archives: Lithography

By Ed Korcynzski

Industry R&D consortium imec runs a series of technology forums around the world, starting in June in Antwerp, Belgium, and including a stop in July in San Francisco in coordination with SEMICON West. Greg McIntyre, imec Director of Advanced Patterning, discussed the state-of-the-art in Extreme Ultra-Violet (EUV) lithography technology with Solid State Technology during the Antwerp event. While still focusing on “path-finding” R&D for industry, the recent technology challenges associated with commercializing EUV lithography has pulled imec into work on patterning ecosystem materials such as resists and pellicles.

With each NXE:3400B model EUV stepper from ASML valued at US$125 million it costs $1 billion to invest in a set of 8 tools to begin high-volume manufacturing, and the entire lithography materials supply-chain is engaged in improving availability and throughput of this expensive tool-set. For high performance logic ICs we need EUV to reach the smallest and most powerful FETs possible, so EUV is in pilot production for logic chips at Samsung and TSMC this year, and will likely begin pilot ramps at Intel and GlobalFoundries next year.

The first use of EUV in IC HVM will be as “cut-masks” for use in self-aligned multi-patterning (SAMP) process flows that start with argon-fluoride-immersion (ArFi) deep ultra-violet (DUV) steppers. Such a first use allows for substitution of three ArFi “multi-color” cut-masks in place of the one EUV mask, in case there are unanticipated issues with the new EUV steppers. Second use in HVM will then happen using a single-exposure of EUV to pattern metal layers, but with no ability to use multiple ArFi exposure as a back-up.

“We will not put EUV in our critical path,” commented Dr. Gary Patton, GlobalFoundries’ CTO and SVP of Worldwide R&D, during a presentation in Antwerp, “But it’s clear that it’s coming and it will offer compelling advantages.” Patton said the company is experimenting with two of ASML’s EUV steppers in a New York fab, and will launch the company’s “7-nm-node” finFET production first with ArFi and then move to EUV when the throughput and uptime of the process make it affordable in their cost models.

Figure 1 shows the extremely small patterning process window around 18nm half-pitch line arrays (P36) using EUV lithography with Dipole source-mask optimization (SMO):  micro-bridging between lines starts below 15.5nm, while breaks within lines start above 18nm. These stochastic failures (Ref:  “Waddle-room for Black Swans:  EUV Stochastics”, SemiMD.com) are caused by variations in the photons absorbed by the resist (a.k.a. “shot noise”), the quantum efficiency of photo-acid generation (PAG) and diffusion, thequencher distribution,and optical and chemical interactions with under-layers for adhesion, anti-reflective coatings, and hardmasks.

Figure 1. Stochastic failures due to atomic-scale variability are shown in top-down CD-SEM images taken from 36-nm Pitch (P36) line/space arrays of post-etched photoresist that had been patterned using EUV lithography, which define the limits of the patterning process window when plotted as Percent Not-OK (%NOK) within an inspected area. (Source: imec)

Every nanometer of resolution is difficult to achieve when patterning below 20nm half-pitch, with many parameters contributing noise to the signal. For EUV lithography using reflective optics, the mask surface causes undesired “flare” reflections from the un-patterned area, such that bright-field masks inherently distort images more than dark-field masks. Since cuts typically only expose <20% of the field, these masks will be much less noisy as dark-fields.

Given the need for dark-field cut-masks, the ideal photoresist will be positive-tone (PT) which means that reformulations of Chemically-Amplified Resists (CAR) based on organic molecules can be used. Standard organic CAR tuned for ArFi lithography provides some sensitivity to EUV, and blends of standard CAR molecules can be tuned to improve trade-offs within the inherent Resolution, Line-Edge-Roughness (LER), and Sensitivity trade-off triangle. Consequently, all of the suppliers of ArFi CAR are capable of supplying some EUV CAR. Since stochastic effects are interdependent, resist vendors have to explore integration options within the entire stack of patterning materials.

JSR co-founded with imec the EUV Resist Manufacturing & Qualification Center NV (EUV RMQC) in Leuven, Belgium, where an EUV stepper at imec is available for experiments. “RMQC is running at full speed, and shipping out production lots,” said McIntyre. “Intel’s Britt Turkot mentioned at SPIE this year that the resist qualification work being done at IMEC has been very beneficial.”

ASML now owns the critical-dimension scanning-electron microscopy (CD-SEM) technology of Hermes Microvision Inc (HMI), and Neal Callan, ASML’s Vice President of Pattern Fidelity Metrology, spoke with Solid State Technologyabout controlling EUV patterning. Electron-beams cause shrinkage in organic films like CAR, and that shrinkage results in a CD bias that can be more than one nanometer. Different CAR formulations from different vendors shrink at different rates, and the effect is more difficult to model in 2D structures. ”We’re being pushed for accurate metrology in terms that can be quantified,” explained Callan. “The biggest issues are in terms of CD-bias with 2D features. We need to build more accurate models to create better data for OPC and for computational lithography, and also for our etch modeling peers.”

“Design rules for EUV need to be stochastically aware,“ confided McIntyre. “Designers need to know how much can be sacrificed in a design rule such as tip-to-tip spacing depending on the pattern pitch. There are different ways that we can think about minimizing stochastic effects.”

While stochastics and systematic yield losses increase in relative importance with decreasing device dimensions, losses due to random defects are also more difficult to control. Figure 2 shows second-generation EUV pellicles made from carbon nano-tubes (CNT) by imec to protect EUV masks from random particles while transmitting ~95%. First-generation pellicles reportedly transmit <90%.

Figure 2. Second generation EUV pellicles based on carbon nano-tubes (CNT) demonstrate increased transmission of ~95% while maintaining sufficient mechanical stability to protect reticles. (Source: imec)

“Today, new purity challenges are not only faced by the fab but also by their materials suppliers driving sharp increases in the use of filtration and purification systems to prevent wafer defects and process excursions,” explained Clint Harris, Senior Vice President and General Manager, Microcontamination Control Division, Entegris, to Solid State Technology.“The transition from 45nm- to 10nm-node has resulted in a 2.5x increase in the changeout frequency of filters as well as a 4x reduction of maximum allowable contaminant size. This trend is expected to continue as device parametric performance becomes more sensitive to particles, gels, metals, mobile ions, and other organic contaminants.”

[As a TECHCET Analyst, Ed Korczynski writes the TECHCET Critical Materials Report (CMR) on Photoresists & Ancillaries. https://techcet.com/product/photoresists-and-photoresist-ancillaries/]

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress.

BY HONGGOO LEEa, SANGJUN HANa, JAESON WOOa, JUNBEOM PARKa, CHANGROCK SONGa, FATIMA ANISb, PRADEEP VUKKADALAb, SANGHUCK JEONc, DONGSUB CHOIc, KEVIN HUANGb, HOYOUNG HEOb, MARK D SMITHb, JOHN C. ROBINSONb

aSK Hynix, Korea
bKLA-Tencor Corp., Milpitas, CA cKLA-Tencor Korea, Korea

As ground rules shrink, advanced technology nodes in semiconductor manufacturing demand smaller process margins and hence require improved process control. Overlay control has become one of the most critical parameters due to the shrinking tolerances and strong correlation to yield. Process-induced overlay errors, from outside the litho cell, including non-uniform wafer stress, has become a significant contributor to the error budget. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control [1, 2]. Patterned wafer geometry (PWG) metrology has been used to reduce stress-induced overlay signatures by monitoring and improving non-litho process steps or by compensation for these signatures by feed forward corrections to the litho cell [3,4]. Of paramount impor- tance for volume semiconductor manufacturing is how to improve the magnitude of these signatures, and the wafer to wafer variability. Standard advanced process control (APC) techniques provide a single set of control parameters for all wafers in a lot, and thereby only provide aggregate corrections on a per chuck basis. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer- level grouping based on incoming process induced overlay.

Wafer stress induced overlay is becoming a major challenge in semiconductor manufacturing, and the percentage contribution to the overlay budget is increasing. Addressing non-litho overlay is paramount to reducing wafer level variability. The amplitude of stress and the overlay budget differ by market segment. We observe from FIGURE 1 that the 3D NAND, for example, has the largest magnitude of wafer shape induced stress, but also has a relatively large overlay budget of 8 to 20 nm. DRAM, on the other hand, has less stress, but has a much tighter overlay spec of 2 to 3 nm. The relative stress level and overlay budget dictate different process control use cases. For the case of 3D NAND, the improved overlay can be achieved using the PWG stress data for process monitoring as mentioned earlier, or by directly providing the stress based feed forward corrections to the litho cell [3, 4]. In this work, we will focus on the DRAM device application. Key topics include identifying process signatures in the shape data, and using those signatures to reduce within lot variability.

Firstly, we will discuss the connection between wafer shape and overlay. During integrated circuit manufacturing many layers are printed on a silicon wafer. There is a critical need to align precisely pattern layers to an underlying pattern. This requirement is often complicated tighter overlay spec of 2 to 3 nm. The relative stress level and overlay budget dictate different process control use cases. For the case of 3D NAND, the improved overlay can be achieved using the PWG stress data for process monitoring as mentioned earlier, or by directly providing the stress based feed forward corrections to the litho cell [3, 4]. In this work, we will focus on the DRAM device application. Key topics include identifying process signa- tures in the shape data, and using those signatures to reduce within lot variability.

Firstly, we will discuss the connection between wafer shape and overlay. During integrated circuit manufac- turing many layers are printed on a silicon wafer. There is a critical need to align precisely pattern layers to an underlying pattern. This requirement is often complicated by process induced stress variations distorting the under- layer pattern, as illustrated in FIGURE 2 [5, 6]. A reference layer pattern is formed at a certain level N (or layer N) and the pattern is initially defined by the characteristic length L shown. To form level N+1, a film is first deposited on top of level N. Film stress causes the wafer to warp in free-state resulting in a change to shape of wafer. This is typically manifested as both out-of-plane displacement (OPD) and in-plane displacement (IPD), affecting lateral placement of the under-layer pattern (level N). To print the level N+1 pattern the wafer is forced flat (e.g. lithog- raphy vacuum chucked). For the most part, chucking the wafer fully reverses the out-of-plane displacement but the in-plane displacement is only partially reversed. Thus, the under-layer pattern is now displaced relative to where it was originally printed. If level N+1 pattern is printed without correcting for the under-layer distortion, it results in misalignment or overlay error between the two layers. Such an overlay error is known as process- induced or process-stress induced overlay error and it can be caused by any type of stress inducing semiconductor process such as film deposition, thermal anneal, etch, CMP, etc.

Wafer shape is measured by a unique implementation of a dual-Fizeau interferometer on KLA-Tencor Corporation’s WaferSightTM PWG patterned wafer geometry and nanotopography metrology system [7]. Simultaneous back side and front side measurements are made with the wafer in a vertical orientation to eliminate gravitational distortion.

Overlay is measured on a KLA-Tencor Corporation ArcherTM 500 overlay metrology system using Archer AIM® optical imaging metrology targets.

It has been shown that process-induced overlay error can be accurately estimated from the change in shape induced by semiconductor processes [2, 6, 8, 9]. FIGURE 3 shows a simplified schematic of a semiconductor process flow of a single layer. To estimate potential overlay error induced by processes between the reference lithography step (e.g. level N) and the current lithography step (e.g. level N+1), it is necessary to make wafer geometry measurement at the two indicated points in the figure as “pre” and “post”, corresponding to before and after the shape or stress inducing process steps. Once wafer geometry measure- ments become available, the change in the shape induced by processing is calculated as the difference between two measurements. Process-induced overlay error can then be calculated from the shape change by using one of several algorithms that have been developed [2, 6, 8, 9]. In this paper, we use an advanced IPD algorithm based on two-dimensional plate mechanics for the accurate estimation of the process-induced overlay error referred to as GEN3 [2].

Shape based overlay for DRAM

As discussed previously, different semiconductor processes have varying levels of stress and different overlay error budgets, including 3D NAND, DRAM, logic, etc. These differences require different process control use cases, such as feedback, feed forward, grouping, etc., alone or in combination. In this work we describe an advanced grouping process control use case for DRAM in order to minimize overlay. For this investigation we look at a specific implementation of wafer grouping which is appropriate to R&D environments and ramp-up of high volume manufacturing (HVM) called here send-ahead grouping (SG). The more general grouping use case for HVM will be addressed in a future report.

In order to meet the tight overlay specifications for the next generation DRAM devices, a send-ahead grouping (SG) based on the shape data has been evaluated. The flow of the proposed SG is outlined in FIGURE 4. Firstly, all the wafers in a lot are measured with a PWG tool for both “pre” and “post” layers. The shape data from the difference of these measurements is then used in the GEN3 algorithm to determine stress or shape based predicted overlay. The wafers are then grouped by similarity of wafer signatures. Grouping optimi- zation is performed using the predicted overlay after removing the POR scanner alignment model. The grouping optimi- zation: (i) decides the optimal number of process signatures; (ii) identifies the process signatures; and, (iii) provides a list of recommended wafers for metrology and exposure (step 2 in Fig. 4). The selected wafers are then exposed by the scanner in step 3 and the overlay measurement is performed in step 4. Finally, the correctable coefficients for each group will be calculated separately using the overlay metrology data. The exposed wafers will be reworked and then the entire lot will be exposed using the group by group corrections.

Within lot variability

The work is aimed at reducing the within lot variability. The within lot variability or wafer by wafer (WxW) variability is becoming one of the most important challenges to achieve tight overlay speci- fications for next generation DRAM devices. First we quantify within lot variability for both the shape and the overlay data using a rigorous analysis of variance (ANOVA). We analyzed seven lots individually and the results for both the overlay and PWG data are presented in FIGURES 5 and 6 respectively. The overlay data show an average of 3.6 nm WxW variation in both the X and Y direction. The shape based overlay average within lot variation is 0.55 nm in X and 0.46 nm in the Y direction.

It should be noted that the within lot variation of the overlay data is comprised of different sources and the shape based overlay explains only part of the total within lot overlay variation. FIGURE 7 shows the ratio % of the within lot variation shape based overlay versus the total overlay for both the X and Y direction. It can be seen that shape overlay can explain as much as up to 25% of the total overlay variability. These findings indicate that minimizing the impact of stress based overlay, from processes outside the litho cell, will provide potentially significant improvement, which is critical in the drive towards 2 nm overlay.

DRAM clustering results

For all of the analyses presented in this study, the GEN3 algorithm was used to calculate stress based overlay. To perform grouping the scanner alignment model was first removed from the stress based overlay for each wafer. The alignment removes some of the within lot varia- tions, however, wafer level alignment is not sufficient to remove all the wafer level variations. One useful way to visualize data variation is by performing Principle Component Analysis (PCA) of the data. By performing PCA, we express data in terms of Eigen functions of the covariance matrix of the data. Eigen values of the covariance matrix are calculated such that the first principle component explains the largest variation of the data, the second explains the second largest variation and so on. The coefficient for each principle component (PC) is referred to as the score. FIGURE 8 shows scores for the PC1 (first principle component) versus the PC2 (second principle component) for all the wafers for a single lot using stress based overlay. Two distinct groups, indicating two distinct process signatures can clearly be observed in this lot.

The same analysis was performed for the rest of the six lots as shown in FIGURE 9. For all the lots in this example, two signatures can clearly be observed in their leading scores plot. Some excursion wafers were removed from the analysis. After observing these clear process signature groupings, it was confirmed that the signatures correspond to the two stages of a process tool. This clearly proves that the stress overlay grouping method can successfully identify and distinguish significant process signatures. It should be noted that in the general case the optimal number of groups would not necessarily be two.

We quantified the stress overlay grouping by performing comprehensive send-ahead grouping (SG) simulation study. Grouping optimization was performed using the shape data to select optimal number of groups and also the send-ahead wafers for processing and metrology. Then using the send-ahead wafers for each group, ideal corrections were simulated and applied to each group in the lot. From the composite group residual, |mean|+3σ for each wafer was recorded. The residual |mean|+3σ was also calculated using the standard plan of record (POR) wafers. The root mean square for the average of the |mean|+3σ for X and Y is compared between SG and POR in FIGURE 10. The average |mean|+3σ improved by more than 0.5 nm using the SG solution.

The range is defined as the difference of the maximum and minimum |mean|+3σ per lot for both the X and Y direction. FIGURE 11 shows the comparison of the RMS of X and Y ranges for the six lots. The range has been improved by about 1 nm, underscoring the benefit of controlling wafer level variation by using shape data to identify signatures and group wafers for exposure and metrology.

Conclusions

Process induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget. It is no longer sufficient to focus exclusively on litho cell overlay improvement. Addressing non-litho overlay is key to reducing wafer level variability. We demonstrated a novel technique of using PWG metrology to provide improved litho control by wafer-level grouping based on incoming process induced overlay in a 19 nm DRAM manufacturing process driving towards a 2 nm overlay budget. Wafer to wafer variability range was reduced by around 1 nm across the lots in this study. Future directions include a full HVM implementation of the grouping methodology.

References

1. Characterization and mitigation of overlay error on silicon wafers with nonuniform stress, T. Brunner, et. al., SPIE Volume 9052: Optical Microlithography XXVII, April 2014.
2. Patterned wafer geometry (PWG) metrology for improving process-induced overlay and focus problems, Timothy A. Brunner, et. al., SPIE Volume 9780: Optical Microlithography XXIX, 97800W March 2016.
3. Improvement of process control using wafer geometry for enhanced manufacturability of advanced semiconductor devices, Honggoo Lee, et. al., SPIE Volume 9424: Metrology, Inspection, and Process Control for Microlithography XXIX, April 2015.
4. Lithography overlay control improvement using patterned wafer geometry for sub-22nm technology nodes, Joel Peterson, et. al., SPIE Volume 9424: Metrology, Inspection, and Process Control for Micro- lithography XXIX, April 2015.
5. 5. Relationship between localized wafer shape changes induced by residual stress and overlay errors, K. T. Turner, et. al., Volume 11(1), J. Micro/ Nanolithog. MEMS MOEMS, 013001 December 2012..
6. Characterization of Wafer Geometry and Overlay Error on Silicon Wafers with Nonuniform Stress, T. A. Brunner, et. al., Volume 12(4), Journal of Micro/ Nanolithography, MEMS, and MOEMS 0001, 043002-043002, September 2013.
7. “Interferometry for wafer dimensional metrology,” , K. Freischlad, S. Tang, and J. Grenfell, Proc. SPIE, 6672,667202 (2007).
8. Monitoring process-induced overlay errors through high resolution wafer geometry measurements, K. T. Turner, et. al., SPIE Volume 9050: Metrology, Inspection, and Process Control for Microlithog- raphy XXVIII, 905013, April 2014.
9. Process tool monitoring and matching using inter- ferometry technique, Doug Anberg, et. al., SPIE Volume 9778: Metrology, Inspection, and Process Control for Microlithography XXX, 977831, April 2015.

Reprinted with permission. Original source: Honggoo Lee, Sangjun Han, Jaeson Woo, Junbeom Park, Changrock Song, et al., “Patterned Wafer Geometry Grouping for Improved Overlay Control,” Metrology, Inspection, and Process Control for Microlithography XXXI, edited by Martha I. Sanchez, Vladimir A. Ukraintsev, Proc. of SPIE Vol. 10145, 101450O, (2017).

Market shares of semiconductor equipment manufacturers shifted significantly in Q1 2018 as Applied Materials, the top supplier dropped, according to the report “Global Semiconductor Equipment: Markets, Market Shares, Market Forecasts,” recently published by The Information Network, a New Tripoli-based market research company.

The chart below shows shares for the first quarter (Q1) of calendar year 2017 and 2018. Market shares are for equipment only, excluding service and spare parts, and have been converted for revenues of foreign companies to U.S. dollars on a quarterly exchange rate.

Applied Materials lost significant market share YoY, from 18.4% of the $13.1 billion Q1 2017 market to 17.7% of the $17.0 billion Q1 2018 market. This drop follows a 1.8 share-point loss by Applied Materials for CY 2017 compared to 2016. The company competes with Lam Research and TEL in the deposition and etch market, and both gained share at the expense of Applied Materials.

At the other end of the spectrum, smaller semiconductor companies making up the “other” category lost 2.4 share points as a whole.

Much of the equipment revenue growth was attributed to strong growth in the DRAM and NAND sectors, as equipment was installed in memory manufacturers Intel, Micron Technology, Samsung Electronics, SK Hynix, Toshiba, and Western Digital. The memory sector, which grew grown 61.5% in 2017, is forecast to add another 28.5% in 2018 according to industry consortium WSTS (World Semiconductor Trade Statistics).

TEL recorded growth of 120.3% YoY in Korea, much of it on NAND and DRAM sales to Samsung Electronics and SK Hynix, and 69.5% YoY in Japan, much of it on NAND sales to Toshiba at its Fab 6 in Kitakami, Japan. Lam Research gained 42.2% and 70.5% YoY, respectively, in Korea and Japan.

Following the strong growth in the semiconductor equipment market, The Information Network projects another 11.5% growth in 2018 for semiconductor equipment.

Smart technologies take center stage tomorrow as SEMICON West, the flagship U.S. event for connecting the electronics manufacturing supply chain, opens for three days of insights into leading technologies and applications that will power future industry expansion. Building on this year’s record-breaking industry growth, SEMICON West – July 10-12, 2018, at the Moscone Center in San Francisco – spotlights how cognitive learning technologies and other disruptors will transform industries and lives.

Themed BEYOND SMART and presented by SEMI, SEMICON West 2018 features top technologists and industry leaders highlighting the significance of artificial intelligence (AI) and the latest technologies and trends in smart transportation, smart manufacturing, smart medtech, smart data, big data, blockchain and the Internet of Things (IoT).

Seven keynotes and more than 250 subject matter experts will offer insights into critical opportunities and issues across the global microelectronics supply chain. The event also features new Smart Pavilions to showcase interactive technologies for immersive, virtual experiences.

Smart transportation and smart manufacturing pavilions: Applying AI to accelerate capabilities

Automotive leads all new applications in semiconductor growth and is a major demand driver for technologies inrelated segments such as MEMS and sensors. The SEMICON West Smart Transportation and Smart Manufacturing pavilions showcase AI breakthroughs that are enabling more intelligent transportation performance and manufacturing processes, increasing yields and profits, and spurring innovation across the industry.

Smart workforce pavilion: Connecting next-generation talent with the microelectronics industry

SEMICON West also tackles the vital industry issue of how to attract new talent with the skills to deliver future innovations. Reliant on a highly skilled workforce, the industry today faces thousands of job openings, fierce competition for workers and the need to strengthen its talent pipeline. Educational and engaging, the Smart Workforce Pavilion connects the microelectronics industry with college students and entry-level professionals.

In the Workforce Pavilion “Meet the Experts” Theater, recruiters from top companies are available for on-the-spot interviews, while career coaches offer mentoring, tips on cover letter and resume writing, job-search guidance, and more. SEMI will also host High Tech U (HTU) in conjunction with the SEMICON West Smart Workforce Pavilion. The highly interactive program supported by Advantest, Edwards, KLA-Tencor and TEL exposes high school students to STEM education pathways and useful insights about careers in the industry.

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced worldwide sales of semiconductors reached $38.7 billion for the month of May 2018, an increase of 21.0 percent compared to the May 2017 total of $32.0 billion. Global sales in May were 3 percent higher than the April 2018 total of $37.6 billion. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“The global semiconductor market has posted consistent growth of greater than 20 percent for 14 consecutive months, and May 2018 marked the industry’s highest-ever monthly sales,” said John Neuffer, president and CEO, Semiconductor Industry Association. “The Americas led the way once again, with sales increasing by more than 30 percent compared to last year, and sales were up across all major semiconductor product categories on both a year-to-year and month-to-month basis.”

Year-to-year sales increased solidly across all regions: the Americas (31.6 percent), China (28.5 percent), Europe (18.7 percent), Japan (14.7 percent), and Asia Pacific/All Other (8.7 percent). Month-to-month sales increased more modestly across all regions: China (6.3 percent), Japan (2.6 percent), Asia Pacific/All Other (1.2 percent), the Americas (1.1 percent), and Europe (1.0 percent).

SEMICON West next week will host a White House-led discussion of the anticipated national leadership strategy for semiconductors, a multi-agency initiative led by top U.S. government national security and economic organizations.

On Wednesday, July 11, a panel of U.S. officials representing agencies involved in leading the strategy will address federal research and development (R&D), investment and acquisition priorities aimed at ensuring the U.S. remains the global leader in the semiconductor industry.

As global economic trends and technologies such as artificial intelligence evolve, and foreign governments increasingly lure microelectronics manufacturing investments overseas, the U.S. strategy for manufacturing advanced semiconductors and driving research and development (R&D) in technology innovation has become an economic priority.

The White House selected SEMICON West, organized by SEMI, as the site for the discussion and this urgent call to action because of the event’s central role in bringing together critical industries across the global electronics supply chain. The multi-agency panel will outline activities and new policies under development to ensure U.S. strategic leadership in microelectronics, including focused investment in innovations key to the next generation of devices for commercial and government use. The initiative also includes public-private partnerships to accelerate the capabilities of advanced semiconductors for critical applications such as artificial intelligence (AI), cyber, secure communications, the internet of things (IoT) and big data analytics.

PANEL:
National Strategy for Semiconductor and Microelectronic Innovation
TIME AND DATE:
10:30 to 11:30 a.m., Wednesday, July 11
LOCATION:
Yerba Buena Theater, 700 Howard St., San Francisco
MODERATOR:
Dr. Lloyd Whitman, Principal Assistant Director, Physical Sciences and Engineering, White House Office of Science and Technology Policy
PANELISTS:
Dr. Sankar Basu, Program Director, Computer and Information Science and Engineering, National Science Foundation
Dr. Eric W. Forsythe, Flexible Electronics Team Leader, U.S. Army Research Laboratory
Dr. Jeremy Muldavin, Deputy Director of Defense Software & Microelectronics Activities, Office of the Deputy Assistant Secretary of Defense for Systems Engineering
Dr. Robinson Pino, Acting Research Division Director, Advanced Scientific Computing Research, Office of Science, Department of Energy

 

SEMICON West is organized by SEMI Americas to connect more than 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMICON West is celebrating its 47th year as the flagship event for the semiconductor industry. Find more at www.semiconwest.org.

Global semiconductor industry revenue declined 3.4 percent in the first quarter of 2018 falling to $115.8 billion. Semiconductor industry performance was negatively affected by the declining sales and first-quarter seasonality in the wireless communications market. Other sectors, such as automotive and consumer semiconductors, experienced nominal market growth, according to IHS Markit (Nasdaq: INFO).

The memory category experienced the highest growth of 1.7 percent in the first quarter, reaching $39.7 billion, as demand for memory components increased in the enterprise and storage markets. In fact, DRAM pricing and shipments both increased during the quarter, as strong demand for server DRAM continued to propel the semiconductor market. However, NAND began to show signs of softening, with slight revenue declines during the quarter, mainly due to single-digit price declines. “Even with the slight revenue decline during the quarter, the NAND market still achieved its second-highest revenue quarter on record, with strong demand coming from the enterprise and client solid-state drive markets,” said Craig Stice, senior director, memory and storage, IHS Markit.

Semiconductor market share

Led by its dominant position in the memory market, Samsung Electronics led the semiconductor industry in the first quarter of 2018, with 16.1 percent of the market, followed by Intel at 13.6 percent and SK Hynix at 7.0 percent. Quarter-over-quarter market shares were relatively flat, with no change in the top-three ranking list. However, on a year-over-year basis, Samsung supplanted Intel as the leading semiconductor company, compared to the first quarter of 2017.

Analog component sales for Texas Instruments, Maxim Integrated, ON Semiconductor and other companies with a strategic focus on industrial and automotive industries managed single-digit sales increases in the first quarter. In contrast, analog component revenue declined by double digits for Qualcomm, Skyworks Solutions, Oorvo and other companies targeting the wireless industry.

Memory IC companies — Samsung Electronics, SK Hynix, Micron Technologies and Toshiba — continued to dominate the top ten semiconductor companies. Micron achieved the highest growth rate in the top ten, recording 9.8 percent growth in the first quarter, compared to the previous quarter. Qualcomm revenue fell 13.6 percent, which was the largest sequential drop, due to the weakness in the wireless communication market. Qualcomm and nVidia were the only two fabless companies remaining in the top ten.

Fujitsu Semiconductor Limited (Fujitsu Semiconductor) and United Microelectronics Corporation (NYSE:UMC; TWSE:2303) (“UMC”), a global semiconductor foundry, today announced that UMC will acquire all of the shares of Mie Fujitsu Semiconductor Limited (MIFS), a 300mm wafer foundry joint venture between both companies.

In addition to the 15.9% of MIFS shares currently owned by UMC, Fujitsu Semiconductor will transfer the remaining 84.1% of its shares in MIFS to UMC, making MIFS a wholly-owned subsidiary of the Taiwan-based foundry. The consideration of the transaction will be around ¥ JPN 57.6 billion. The transfer is planned for January 1, 2019, pending approval by the relevant governmental authorities.

In 2014, both companies concluded an agreement for UMC to acquire a 15.9% stake in MIFS through progressive phases. Since then, besides equity investment, Fujitsu Semiconductor and UMC have been furthering their partnership through licensing of UMC’s 40nm technology and establishment of a 40nm logic production line at MIFS. After several years of joint operations, both companies have agreed on the benefits of integrating MIFS into UMC, which has a strong business foundation as a world leading semiconductor foundry with a broad customer portfolio, enhanced manufacturing expertise and extensive technology offerings enabling MIFS to maximize its values it can deliver to all stakeholders, including its customers.

As a member of UMC, MIFS will continue to provide foundry services of an even higher quality to its customers. While the name of the company and details of distribution after the transaction will soon be determined, for the present, MIFS will maintain its existing distribution channels for customers.

Jason Wang, co-president of UMC said, “UMC is experiencing high demand from mature 12″ processes. With new applications in 5G, IoT, automotive and AI requiring these technologies, we anticipate the market conditions driving this demand to remain strong for the foreseeable future. The acquisition of a fully qualified, equipped, and volume production proven 12″ facility provides greater time and ROI advantages compared to building a fab from scratch, which would cost several billion dollars and several years to construct and equip. With existing 300mm fabs in Taiwan, China and Singapore, Japan-based MIFS will help customers further diversify their manufacturing risk with a robust production base to ensure business continuity, which is especially important for automotive chip makers who require a stable and uninterrupted source of supply. UMC will also be able to leverage its decades of world class IC production experience with Japan’s local talent and world-renowned quality standards to better serve Japanese and international customers. We are excited that the strong partnership between UMC and Fujitsu Semiconductor will enable us to achieve further growth and provide customers with higher value through the acquisition of MIFS.”

“With its strengths in technology, such as ultra-low power consumption process technology, non-volatile memory technology for embedded applications, and RF and mmWave technology, as well as its highly reliable production system, as accepted by automotive customers, and its outstanding and experienced workforce, MIFS has been providing its customers with high quality foundry services” said Kagemasa Magaribuchi, President and Representative Director of Fujitsu Semiconductor. “To sustain its growth in the future and deliver far greater values to its customers, Fujitsu Semiconductor and MIFS have determined that it is the best to further enhance its competitiveness as a pure-play foundry by becoming a member of the UMC Group, a leading global semiconductor foundry. I expect that, by fully leveraging the UMC Group’s strengths, including its expertise and its cost competitiveness driven both by capital investment backed by ample financial resources as well as its globally expanded businesses, MIFS will further grow as a global company. I believe that the further growth of MIFS will also contribute to maintaining and expanding a workforce and to the local economy in the regions MIFS resides.”

Each year at SEMICON West, the “Best of West” awards are presented by Solid State Technology and SEMI. More than 26,000 professionals from the electronics manufacturing supply chain attend SEMICON West and the co-located Intersolar. The “Best of West” award was established to recognize new products moving the industry forward with technological developments in the electronics supply chain.

Selected from over 600 exhibitors, SEMI announced today that the following Best of West 2018 Finalists will be displaying their products on the show floor at Moscone Center from July 10-12:

  • Advantest: T5503HS2 Memory Tester— The T5503HS2 memory tester is the industry’s most productive test solution for the fastest memory devices available today as well as next-generation, super-high-speed DRAMs.  The new system’s flexibility extends the capabilities of the T5503 product family in the current “super cycle,” in which global demand for memories is skyrocketing. (South Hall Booth #1105)
  • BISTel: Dynamic Fault Detection (DFD®) – The DFD system offers full trace data coverage and eliminating the need for timely and costly modeling and set up. DFD® is also a bridge to smart factory manufacturing because it integrates seamlessly to legacy FDC systems meaning customers can access the most comprehensive, and accurate fault detection system on the market. (South Hall Booth 1811)
  • Rudolph Technologies: Dragonfly System with Truebump Technology– Rudolph’s Dragonfly System with Truebump Technology was designed to provide a complete solution for “total bump process control.” Using a unique approach, Truebump Technology combines 2D inspection and measurement information from image-based techniques with 3D data from separate high-precision and high-throughput laser-based techniques to deliver accurate and complete characterization at production-capable throughputs. (North Hall Booth #6170)

Congratulations to each of the Finalists. The Best of West Award winner will be announced during SEMICON West (www.semiconwest.org) on Wednesday, July 11, 2018.

About SEMI

SEMI® connects over 2,000 member companies and 1.3 million professionals worldwide to advance the technology and business of electronics manufacturing. SEMI members are responsible for the innovations in materials, design, equipment, software, devices, and services that enable smarter, faster, more powerful, and more affordable electronic products. FlexTech, the Fab Owners Alliance (FOA) and the MEMS & Sensors Industry Group (MSIG) are SEMI Strategic Association Partners, defined communities within SEMI focused on specific technologies. Since 1970, SEMI has built connections that have helped its members prosper, create new markets, and address common industry challenges together. SEMI maintains offices in Bangalore, Berlin, Brussels, Grenoble, Hsinchu, Seoul, Shanghai, Silicon Valley (Milpitas, Calif.), Singapore, Tokyo, and Washington, D.C.  For more information, visit www.semi.org and follow SEMI on LinkedIn and Twitter.

About Extension Media

Extension Media is a publisher of over 20 business-to-business magazines (including Solid State Technology), resource catalogs, newsletters and web sites that address high-technology industry platforms and emerging technologies such as chip design, embedded systems, software and infrastructure, intellectual property, architectures, operating systems and industry standards. Extension Media publications serve several markets including Electronics, Software/IT and Mobile/Wireless. Extension Media is a privately held company based in San Francisco, Calif. For more information, visit www.extensionmedia.com

IC Insights will release its 200+ page Mid-Year Update to the 2018 McClean Report next month.  The Mid-Year Update will revise IC Insights’ worldwide economic and IC industry forecasts through 2022 that were originally presented in the 2018 McClean Report issued in January of this year.

Figure 1 shows that IC Insights forecasts that China-headquartered companies will spend $11.0 billion in semiconductor industry capex in 2018, which would represent 10.6% of the expected worldwide outlays of $103.5 billion.  Not only would this amount be 5x what the Chinese companies spent only three years earlier in 2015, but it would also exceed the combined semiconductor industry capital spending of Japan- and Europe-headquartered companies this year.

Since adopting the fab-lite business model, the three major European producers have represented a very small share of total semiconductor industry capital expenditures and are forecast to account for only 4% of global spending in 2018 after representing 8% of worldwide capex in 2005.  Although there may be an occasional spike in capital spending from European companies (e.g., the surge in spending from ST and AMS in 2017), IC Insights believes that Europe-headquartered companies will represent only 3% of worldwide semiconductor capital expenditures in 2022.

It should be noted that several Japanese semiconductor companies have also transitioned to a fab-lite business model (e.g., Renesas, Sony, etc.).  With strong competition reducing the number and strength of Japanese semiconductor manufacturers, the loss of its vertically integrated businesses and thus missing out on supplying devices for several high-volume end-use applications, and its collective shift toward fab-lite business models, Japanese companies have greatly reduced their investment in new wafer fabs and equipment.  In fact, Japanese companies are forecast to represent only 6% of total semiconductor industry capital expenditures in 2018, a big decline from the 22% share they held in 2005 and an even more precipitous drop from the 51% share they held in 1990.

Figure 1

Although China-headquartered pure-play foundry SMIC has been part of the list of major semiconductor industry capital spenders for quite some time, there are four additional Chinese companies that are forecast to become significant semiconductor industry spenders this year and next—memory suppliers XMC/YMTC, Innotron, JHICC, and pure-play foundry Shanghai Huali.  Each of these companies is expected to spend a considerable amount of money equipping and ramping up their new fabs in 2018 and 2019.

Due to the increased spending by startup China-based memory manufacturers, IC Insights believes that the Asia-Pac/Others share of semiconductor industry capital spending will remain over 60% for at least the next couple of years.