Category Archives: Lithography

BY RYAN PEARMAN, D2S, Inc., San Jose, CA

There are big changes on the horizon for semiconductor mask manufacturing, including the imminent first production use of multi-beam mask writers, and the preparation of all phases of semiconductor manufacturing for the introduction of extreme ultra-violet (EUV) lithography within the next few years. These changes, along with the increasing use of multiple patterning and inverse- lithography technology (ILT) with 193i lithography, are driving the need for more detailed and more accurate modeling for mask manufacturing.

New solutions bring new mask modeling challenges

Both EUV and multi-beam mask writing provide solutions to many long-standing challenges for the semiconductor industry. However, they both create new challenges for mask modeling as well. Parameters once considered of negligible impact must be added to mask models targeted for use with EUV and/or multi-beam mask writers. In particular, the correct treatment of dose profiles has emerged as a critical component for mask models targeting these new technologies. This is in addition to scattering effects, such as the well-known EUV mid-range scatter, that must be included in mask models to accurately predict the final mask results. Gaussian models, which form the basis for most traditional mask models, will not be sufficient as many of these new parameters are more properly represented with arbitrary point-spread functions (PSFs).

The most obvious – and most desperately needed – benefit of EUV lithography is greater accuracy due to its enhanced resolution. However, this benefit comes along with a mask-making challenge: wafer-printing defects due to mask errors will appear more readily because of this enhanced resolution. Therefore, the introduction of EUV will require the mean-to-target (MTT) variability on photomasks to become smaller. From a mask manufacturability perspective, all sources of printing errors, systematic and random, must be improved. This means that mask models must also be more accurate, not only in predicting measurements, but also in predicting variability.

A well-known challenge for EUV mask modeling is the EUV mid-range scatter effect. The more complex topology of EUV masks leads to broader scattering effects. In addition to “classical” forward- and back-scatter effects, which dominate 193i lithography, there is a mid-range (1μm) scatter that now requires modeling. This phenomenon is non-Gaussian in nature, so cannot be simulated accurately with simple Gaussian (“1G”) models. In combination with better treatment of resist effects, a PSF-based model is a much better represen- tation of the critical lithography process.

The eagerly anticipated introduction of EUV will demand a lower-sensitivity resist to be used for EUV masks due to the smaller size of EUV features. This is one of the reasons why multi-beam mask writers have emerged as the replacement for variable shaped beam (VSB) tools for the next generation of mask writers. Slower resists require higher currents, and VSB tools today are limited thermally in ways the massively parallel multi-beam tools are not. In addition to thermal effects, VSB mask writers are runtime-limited by shot count; we are already approaching the practical limit for many advanced masks. Shot count is only expected to grow in the future as pitches shrink and complex small features become prevalent in EUV masks – and even in 193i masks due to increased use of ILT to improve process windows for 193i lithography.

In contrast to VSB mask writers, which use shaped apertures to project the shapes (usually rectangles) created by optical-proximity correction (OPC) onto the mask, multi-beam mask writers rasterize the desired mask shapes into a field of pixels, each of which are written by one of hundreds of thousands of individual beamlets (FIGURE 1). This enables multi-beam mask writers to write masks in constant time, no matter how complicated the mask shapes. Each of these beamlets can be turned on and off independently to create the desired eBeam input, which enables the fine resolution of smaller shapes. However, it also means that the dose profiles for the multi-beam writers are far more complex, leading to the need for more advanced, separable dose and shape modeling.

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Since the beamlets of a multi-beam tool are smaller than the primary length-scale of the dose blur, a key second advantage of multi-beam writers emerges: the patterns written are intrinsically curvilinear. In contrast, VSB mask writers can only print features with limited shapes – principally rectangular and 45-degree diagonals, although some tools enable circular patterns. The critical process-window enhancements for ILT also rely on curvilinear mask shapes, so a synergy appears: better treatment of curved edges at the mask writing step will lead to better wafer yield.

Dose and shape: New requirements for multi- beam and EUV mask models

Multi-beam mask writers, EUV masks, and even the proliferation of ILT will require mask models to change substantially. Until very recently, curvi-linear mask features have been ignored when characterizing masks, and models, when used, have assumed simplicity. Primary electron blur (“forward scattering”), including chemically amplified resist (CAR) effects, historically have been assumed to be a set of Gaussians, with length scales between 15nm and 300nm. All other effects of the mask making processes – long-range electron scattering (“back-scatter” and “fogging”), electron charging, devel- opment, and plasma-etching effects – have either been assumed to be constant regardless of mask shape or the dose applied, or have been accounted for approxi- mately by inline corrections in the exposure tool.

To meet the challenges posed by both EUV and multi- beam writing – especially since they are likely to be employed together – mask models will need to treat dose and shape separately, and to explicitly account for the various scattering, fogging, etch, and charging effects (FIGURE 2).

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When masks were written entirely at nominal dose, dose-based effects could be handled together with shape-based effects as a single term. Several years ago, overlapping shots were introduced by D2S for VSB tools to both improve margins and reduce shot-count for complex mask shapes. At this time, it became clear that dose modulation (including overlapping shots) required specific modeling. Some effects (like etch) varied only with respect to the resist contour shapes, while other print bias effects were based on differences in exposure slope near the contour edge. For all the complexity of VSB overlapping shots, all identical patterns were guaranteed to print in the same way. Today, with multi-beam writers, there are significant translational differences in features due to dose-profile changes as they align differently with the multi-beam pixel grid.

We discussed earlier that multi-beam tools print curvi-linear shapes. We should point out that even Manhattan designs become corner-rounded on the actual masks at line ends, corners, and jogs. Why? Physics is almost never Manhattan, and treating it as such will be inaccurate, as in the case of etching effects computed in the presence of Manhattan jogs. We need to embrace the fact that all printed mask shapes will be curvilinear and ensure that any shape-based simulation is able to predict effects at all angles, not just 0 and 90.

Increasing mask requirements drive the need for mask model accuracy

As we continue to move forward to more advanced processes with ever-smaller feature sizes, the requirement for better accuracy increases. There is quite literally less room for any defects. This increased emphasis on accuracy and precision is what drives the adoption of new technologies such as EUV and multi-beam mask writing; it drives the increased need for better model performance as well.

We have already discussed several model parameters that will need to be re-evaluated and handled differently in order to achieve greater accuracy. Accuracy also requires a more rigorous approach to the calibration and validation of models with test chips that isolate specific physics effects with specific test structures. For example, masks that include complex shapes require 2D validation. Today’s VSB mask writers are Manhattan (1D) writing instruments, so models built using these tools are by definition 1D-centric. Inaccuracies in 1D models are exacerbated when tested against a 2D validation. Physics-based models are far more likely to extrapolate to 2D shapes, and are better for ILT.

As features shrink, the accuracy of individual shapes on the mask is impacted increasingly by their proximity to other shapes. The context for each shape on the mask becomes as important as the shape itself. The solution is to model each shape within the context of its surroundings. This is driving the need for simulation-based modeling and mask-correction methodologies.

GPU acceleration: Making simulation-based mask modeling practical

Historically, simulation-based processing of mask models resulted in unacceptably long simulation runtimes. The most common approach until recently has been to use model-based or rules-based methodologies that, while providing less accuracy, result in faster runtimes. The advent of GPU-accelerated mask simulation has changed this picture. GPU acceleration is particularly suited to “single instruction, multiple data” (SIMD) computing, which makes it a very good fit for simulation of physical phenomena, and enables full- reticle mask simulation within reasonable runtimes.

An additional advantage of GPU acceleration is the ability to employ PSFs without runtime impact (FIGURE 3). As we’ve already discussed, PSFs are a natural choice for the mask-exposure model, including EUV mask mid-range scattering effects, forward-scattering details, and modeling back-scattering by construction. Using PSFs, any dose effect of any type can be exactly modeled during simulation-based processing.

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GPU acceleration opens the door for simulation-based correction of a multitude of complex mask effects based on physics-based models, affording practical simulation run times for these more complex models.

PLDC: New mask models at work in multi-beam mask writers

As with any big changes to the semiconductor manufacturing process, the industry has been preparing for EUV and multi-beam mask writing for several years. These preparations have required various members of the supply chain to work together to deploy effective solutions. One example of this collaboration in the mask-modeling realm is the introduction by NuFlare Technology of pixel-level dose correction (PLDC) in its MBM-1000 multi-beam mask writer. At the 2017 SPIE Photomask Japan conference, NuFlare and D2S jointly presented a paper [2] detailing the mask modeling – and GPU acceleration – used in this new inline mask correction.

PLDC manipulates the dose of pixels to perform short- range (effects in the 10nm scale to 3-5μm scale) linearity correction while improving the overall printability of the mask. In addition to the traditional four-Gaussian (4G) PEC model, PLDC combines for the first time an inline 10nm-100nm short-range linearity correction with a 1μm scale mid-range linearity correction (FIGURE 4). This mid-range correction is particularly useful for EUV mid-range scatter correction.

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The dose-based effects portion of the D2S mask model, TrueModel, are expressed as a PSF for an interaction range up to 3-5μm, and with a 4G PEC model for interaction range up to 40-50μm. Being able to express any arbitrary PSF as the correction model allows smoothing of “shoulders” that are often present on multiple Gaussian models, and allows proper modeling of effects that are not fundamentally Gaussian in nature (such as the EUV mid-range scatter). This ability to model physical effects and correct for them inline with mask writing results in more accurate masks, including for smaller EUV shapes and for curvilinear ILT mask shapes.

PLDC is simulation-based, so it has the ability to be very accurate regardless of targeted shape, regardless of mask type (e.g., positive, negative EUV, ArF, NIL master) with the right set of mask modeling parameters.

GPU acceleration enables fast computing of PSF convo- lutions for all dose-based effects up to 3-5μm range, performed inline in the MBM-1000, which helps to maintain turnaround time in the mask shop.

Conclusions

Mask models need some significant adaptations to meet the coming challenges. The new EUV/multi-beam mask writer era will require mask models to be more detailed and more accurate. More complex dose profiles and more complex electron scattering require PSFs be added to the industry-standard Gaussian models. More rigorous mask models with specific dose and specific shape effects are now needed. Simulation-based mask processing, made practical by GPU acceleration, is necessary to take context-based mask effects into account.

The good news is that the mask industry has been preparing for these changes for several years and stands ready with solutions to the challenges posed by these new technologies. Big changes are coming to the mask world, and mask models will be ready.

References

1. Pearman, Ryan, et al, “EUV modeling in the multi-beam mask writer era,” SPIE Photomask Japan, 2017.

2. “GPU-accelerated inline linearity correction: pixel-level dose correction (PLDC) for the MBM-1000,” Zable, Matsumoto, et al, SPIE Photomask Japan, 2017.

Samsung Electronics today announced that it broke ground on a new EUV (extreme ultraviolet) line in Hwaseong, Korea.

With this new EUV line, Samsung will be able to strengthen its leadership in single nanometer process technology by responding to market demand from various applications, including mobile, server, network, and HPC (high performance computing), for which high performance and power efficiency are critical.

The new facility is expected to be completed within the second half of 2019 and start production ramp-up in 2020. The initial investment in the new EUV line is projected to reach USD 6 billion by 2020 and additional investment will be determined depending on market circumstances.

“With the addition of the new EUV line, Hwaseong will become the center of the company’s semiconductor cluster spanning Giheung, Hwaseong and Pyeongtaek in Korea,” said Kinam Kim, President & CEO of Device Solutions at Samsung Electronics. “The line will play a pivotal role as Samsung seeks to maintain a competitive edge as an industry leader in the coming age of the Fourth Industrial Revolution.”

Samsung has decided to utilize cutting-edge EUV technology starting with its 7-nanometer (nm) LPP (Low Power Plus) process. This new line will be set up with EUV lithography equipment to overcome nano-level technology limitations. Samsung has continued to invest in EUV R&D to support its global customers for developing next-generation chips based on this leading-edge technology.

Samsung Electronics Hwaseong Campus EUV line bird’s eye view

Samsung Electronics Hwaseong Campus EUV line bird’s eye view

The research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. today announced that its extensive, long-standing collaboration has resulted in the industry’s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence Innovus Implementation System and Genus Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.

The Cadence Innovus Implementation System is a massively parallel physical implementation system that enables engineers to deliver high-quality designs with optimal power, performance and area (PPA) targets while accelerating time to market. The Cadence Genus Synthesis Solution is a next-generation, high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity by up to 10X. For more information on the Innovus Implementation System, please visit www.cadence.com/go/innovus3nm, and to learn about the Genus Synthesis Solution, visit www.cadence.com/go/genus3nm.

For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions. For more information on EUV technology and 193i technology, visit https://www.imec-int.com/en/articles/imec-presents-patterning-solutions-for-n5-equivalent-metal-layers.

Post place and route layout of 21 nm pitch metal layers

Post place and route layout of 21 nm pitch metal layers

“As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,” said An Steegen, executive vice president for semiconductor technology and systems at imec. “Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3nm implementation. Due to Cadence’s well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3nm rule set.”

“Imec’s state-of-the-art infrastructure enables pre-production innovations ahead of industry demands, making them a critical partner for us in the EDA industry,” said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. “Expanding upon the work we did with imec in 2015 on the industry’s first 5nm tapeout, we are achieving new milestones together with this new 3nm tapeout, which can transform the future of mobile designs at advanced nodes.”

Imec continues to advance the readiness of EUV lithography with particular focus on EUV single exposure of Logic N5 metal layers, and of aggressive dense hole arrays. Imec’s approach to enable EUV single patterning at these dimensions is based on the co-optimization of various lithography enablers, including materials, metrology, design rules, post processing and a fundamental understanding of critical EUV processes. The results, that will be presented in multiple papers at this week’s 2018 SPIE Advanced Lithography Conference, are aimed at significantly impacting the technology roadmap and wafer cost of near-term technology nodes for logic and memory.

With the industry making significant improvements in EUV infrastructure readiness, first insertion of EUV lithography in high-volume manufacturing is expected in the critical back-end-of-line metal and via layers of the foundry N7 Logic technology node, with metal pitches in the range of 36–40nm.  Imec’s research focuses on the next node (32nm pitch and below), where various patterning approaches are being considered. These approaches vary considerably in terms of complexity, wafer cost, and time to yield, and include variations of EUV multipatterning, hybrid EUV and immersion multipatterning, and EUV single expose. At SPIE last year, imec presented many advances in hybrid multipatterning and revealed various challenges of the more cost-effective EUV single exposure solution. This year, imec and its partners show considerable progress towards enabling these dimensions with EUV single exposure.

Imec’s path comprises a co-optimization of various lithography enablers, including resist materials, stack and post processing, metrology, computational litho and design-technology co-optimization, and a fundamental understanding of EUV resist reaction mechanisms and of stochastic effects. Based on this comprehensive approach, imec has demonstrated promising advances including initial electrical results, on EUV single exposure focusing on two primary use cases: logic N5 32nm pitch metal-2 layer and 36nm pitch contact hole arrays.

Working with its many materials partners, imec assessed different resist materials strategies, including chemically amplified resists, metal-containing resists and sensitizer-based resists.  Particular attention was paid to the resist roughness, and to nano-failures such as nanobridges, broken lines or missing contacts that are induced by the stochastic EUV patterning regime. These stochastic failures are currently limiting the minimum dimensions for single expose EUV. Based on this work, imec delved into the fundemental understanding of stochastics and identified the primary dependencies influencing failures. Additionally, various metrology techniques and hybrid strategies have been employed to ensure an accurate picture of the reality of stochastics. Imec will report on this collective work, demonstrating the performance of various line-space and contact hole resists.

As resist materials advances alone will likely be inssufient to meet the requirements, imec has also focused on co-optimizing the photomask, film stack, EUV exposures and etch towards an integrated patterning flow to achieve full patterning of the structures. This was done using computational lithography techniques such as optical proximity correction and source mask optimization, complemented by design-technology co-optimization to reduce standard library cell areas. Finally, etch-based post-processing techniques aimed at smoothing the images after the lithography steps yields encouraging results for dense features. Co-optimization of these mulitple knobs is key to achieving optimized patterning and edge placement error control.

Greg McIntyre, Director of advanced patterning at imec summarizes: “We feel these are very promising advances towards enabling EUV to reliably achieve single patterning at these aggressive dimensions.  This would significantly impact the cost effectiveness of patterning solutions for the next few technology nodes.”

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North America-based manufacturers of semiconductor equipment posted $2.36 billion in billings worldwide in January 2018 (three-month average basis), according to the January Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI.  The billings figure is 1.4 percent lower than the final December 2017 level of $2.40 billion, and is 27.2 percent higher than the January 2017 billings level of $1.86 billion.

“The strong billings levels from late 2017 have carried over into the new year,” said Ajit Manocha, president and CEO of SEMI. “We maintain a positive outlook for the 2018 market, marking three years of growth for equipment spending.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg)
Year-Over-Year
August 2017
$2,181.8
27.7%
September 2017
$2,054.8
37.6%
October 2017
$2,019.3
23.9%
November 2017
$2,052.3
27.2%
December 2017 (final)
$2,398.4
28.3%
January 2018 (prelim)
$2.364.8
27.2%

Source: SEMI (www.semi.org), February 2018
SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

Super Micro Computer, Inc. (NASDAQ: SMCI) today announced that it has expanded its Silicon Valley Headquarters to over two million square feet of facilities with the grand opening of its new Building 22.

The Corporate Headquarters includes engineering, manufacturing and customer service making Supermicro the only Tier 1 systems vendor to build its servers in Silicon Valley and worldwide.  Supermicro is ranked as the third largest server systems supplier in the world (Source: IDC).  In addition to the branded solution business used in the ranking, Supermicro also services large OEM and system integrator customers and shipped over 1.2 million units in 2017.

This latest building is the second of five facilities that the company plans to build on the 36-acre property formerly owned by the San Jose Mercury News. Additionally, the company continues to expand its other facilities worldwide.

“Having our design, engineering, manufacturing and service teams all here at our Silicon Valley campus gives Supermicro the agility to quickly respond to the newest technologies in the industry and to our customer’s needs and unique requirements, which is a major advantage that we have over the competition,” said Charles Liang, President and CEO of Supermicro.  “As our business continues to rapidly scale with over 1.2 million server and storage systems shipped globally last year, increasing our production capacity and capabilities is vital to keeping up with our rapid growth.  The opening of Building 22, along with the opening of two new facilities at our technology campus in Taiwan, provides the additional capacity and rack scale integration plug and play capabilities to ensure that we can provide the best possible service to our enterprise, datacenter, channel and cloud customers.”

“We’re thrilled to see an innovative, sustainable, and community-minded leader like Supermicro continuing to invest and grow in San Jose, and we look forward to their continued success now and for years to come!” said San Jose Mayor Sam Liccardo.

“The Corporation for Manufacturing Excellence – Manex would like to congratulate Supermicro for its continued growth through design and engineering excellence,” said Gene Russell, President and CEO of Manex.  “Its investments in workforce, physical plant and equipment are crucial to the Silicon Valley Ecosystem and to its global client base.  Manex, as a network member of the NIST Manufacturing Extension Partnership and the CMTC California network is a proud partner of Supermicro.”

Working closely with key partners like Intel, Supermicro leverages its strength in design and engineering to lead the way with first-to-market server and storage technology innovations. The company offers the industry’s broadest portfolio of advanced server and storage solutions including the popular BigTwin™ and SuperBlade® product lines and provides rack scale integration with rack plug and play capabilities.

In January, Gigaphoton Inc. (Head office: Oyama City, Tochigi Prefecture. President & CEO: Katsumi Uranaka), a major manufacturer of lithography light sources, announced the shipment of an ArF Excimer Laser for advanced immersion exposure (lithography) devices, the “GT65A” Unit 1, as a new product that meets the growing demand for semiconductors in recent years. The new technology of the GT65A significantly contributes to the rise in productivity of lithography equipment by providing stable operation of the laser and improvement of process margins.

The GT65A will also deliver a 50% reduction in service downtime. This key feature is realized by increasing chamber lifetime by 30% as well as improving maintenance efficiency through the utilization of extensive service data expertise acquired through many years of successful service execution.

In addition, the stabilization technology “eMPL Solid” and the control function “hMPL,” which form the spectrum control function, enable the improvement of CD uniformity as well as expanding process latitude.

Furthermore, the GT65A has successfully eliminated the need to use helium gas. Due to this, we are able to contribute to enhancing customers’ sustainability and CSR activities by not only reducing environmental impact, but also by greatly reducing risks associated with future helium gas supply deficits and price increases.

Katsumi Uranaka, President & CEO of Gigaphoton commented, “With the boom in recent years of the semiconductor market, improving the availability of lithography equipment is an important issue for each manufacturer. With the new technology in line with our new roadmap ‘RAM Enhancement,’ we have further strengthened and improved the Reliability, Availability and Maintainability of lithography light sources, contributing to the semiconductor manufacturing industry.”

Peter Trefonas, Ph.D., corporate fellow in Dow Electronic Materials, has recently been elected a Fellow of SPIE, for achievements in design for manufacturing and compact modeling.

SPIE, the international society for optics and photonics, will promote 73 new Fellows of the Society this year, to recognize the significant scientific and technical contributions of each in the multidisciplinary fields of optics, photonics, and imaging. SPIE Fellows are honored for their technical achievements and for their service to the general optics community and to SPIE in particular.

Trefonas has proven himself to be a leader in advanced lithographic technology with numerous highly cited and pioneering papers in key areas of advanced lithography. He contributed to the fundamental investigations of resist chemical mechanisms, such as polyphotolysis, a mechanism of nonlinear development and dissolution rate models based on first principles. He also contributed papers on percolation and reactive diffusion mechanisms. Trefonas authored some of the first papers on shot noise and stochastic effects, as well as the first paper on fractal analysis of development, and the first paper on information theory of lithography. He is coauthor on a simple method to measure the photoacid quantum efficiency, and contributed to a prominent paper on extreme ultraviolet (EUV) stochastics and stochastic development model. He has also published groundbreaking work on deterministic bottom-up/top-down materials designs.

Trefonas has given extensive service to the global optics community, through published literature and his role in technical conferences. He authored significant sections of the ITRS Semiconductor Roadmap, content dedicated to emerging materials. He organized and chaired a conference on emerging display materials for the Materials Research Society, chaired multiple conferences on microlithography for IEEE, and organized and chaired a conference on directed self-assembly (DSA) and block copolymers for the American Physical Society. As a lecturer, he has given full-day tutorials on lithography and antireflectant coatings at multiple locations in the US, Europe, and Asia. He is also helping to build up the next generation of innovators, responsible for hiring and mentoring over 40 scientists who are currently active and contributing to the science and materials of great interest to the optical community.

A long-time member of SPIE, Trefonas has also given significant service to the Society. He has published 41 papers in the Proceedings of SPIE and has published papers in the Journal of Micro/Nanolithography, MEMS, and MOEMS. He is currently an active reviewer of papers on lithographic materials for SPIE journals.

Trefonas’ work has been recognized with many prestigious honors and awards. Among them are the Society of Chemical Industry Perkin Medal for contributions in industrial chemistry, the American Chemical Society Heroes of Chemistry Award for organic fast plasma etch antireflectants, the C. Grant Willson Award for best oral paper at SPIE Advanced Lithography, Rohm and Haas Technology Awards for antireflectants and 248nm resists, the Shipley R&D Innovation Award for i-line photoresists, and the Monsanto Ex Obscura Award for creativity in innovation. He has also recently been elected as a member of the National Academy of Engineering.

Trefonas will be recognized as a new SPIE Fellow at SPIE Advanced Lithography later this month in San Jose, California.

Entering 2018 on solid ground


February 22, 2018

By Walt Custer, Custer Consulting Group

2017 finished on an upturn – both in the USA and globally.  Based on consolidated fourth-quarter actual and estimated revenues of 213 large, global electronic manufactures, sales rose in excess of 7 percent in 4Q’17 vs. 4Q’16 (Chart 1).  This was the highest global electronic equipment sales growth rate since the third quarter of 2011. Because some companies in our sample didn’t close their financial quarter until the end of January, final results will take a few more weeks – but all evidence points to a very strong fourth quarter of last year.

Custer1-Electronic-Equipment

 

Using regional (country specific) data (Chart 2), the normal, consumer electronics driven seasonal downturn began again in January.  However the recent year-over-year growth is still substantial.  On a total electronic equipment revenue basis, January 2018 was up almost 19.5 percent over January 2017.

Custer2-World-Electronic

Because this regional data in local currencies was converted to U.S. dollars at fluctuating exchange, the dollar denominated-growth was amplified by currency exchange effects.  At constant exchange the January growth was only 14 percent.   That is, when the stronger non-U.S. currencies were converted to weakening dollars, the dollar-denominated January 2018 fluctuating exchange growth was amplified by 5.5 percent.

Chart 3 shows 4Q’17/4Q’16 growth of the domestic electronic supply chain.  U.S. electronic equipment shipments were up 9.1 percent.  Only computer equipment and non-defense aircraft sales declined in the fourth quarter.  And of note, SEMI equipment shipments to North America rose almost 31 percent!

Custer3-US-Electronic-Supply

 

Chart 4 shows estimated fourth-quarter growth for the world electronic supply chain.  Only “Business & Office” equipment revenues declined in 4Q’17 vs. 4Q’16.

Custer4-Global-Electronic

Total global electronic equipment sales increased more than 7 percent in the fourth quarter and SEMI equipment revenues rose 32 percent.

2017 was a strong year and 2018 is off to a good start!  The 2017 lofty growth rates will temper, but this current expansion will likely continue.  Watch the monthly numbers!

Originally published on the SEMI blog.

Cymer, a developer of lithography light sources used by chipmakers to pattern advanced semiconductor chips, today announced the first shipment of the newly qualified XLR 800ix light source that improves performance and productivity, as well as lowers cost-of-ownership for leading-edge argon fluoride (ArF) immersion lithography systems.

Several leading semiconductor manufacturers received early access upgrades to the XLR 800ix and their performance exceeded specifications, achieving less than two femtometers total bandwidth variation in every exposure field. This is about 10 times better than existing technology used today.

As chipmakers extend the use of ArF immersion light sources with multi-patterning to the sub-10 nm technology nodes, it becomes increasingly critical to reduce variability across all processes. In partnership with chipmakers, Cymer found that lower bandwidth variation can lead to lower critical dimension (CD) variation, which improves patterning performance both within and wafer-to-wafer. The XLR 800ix introduces new bandwidth stabilization technology, enabling an eight times improvement in bandwidth measurement fidelity, which can be used to tightly control bandwidth stability.

“We are seeing a strong pull to upgrade our installed base light sources to the newest configuration because the XLR 800ix’s performance far exceeds customers’ expectations,” said David Knowles, vice president of the product development group at Cymer. “From technology improvements to application enhancements, the XLR 800ix brings together all our strengths into one platform to deliver powerful results for our customers.”

The XLR 800ix also delivers productivity and cost-of-ownership improvements, enabling a 33% increase in time between service intervals to 40 billion pulses. This is driven by Cymer’s new field-tested chamber and optics modules, which are in production in more than 250 XLR systems. These enhancements also support Cymer’s sustainability initiatives, by lowering total system power consumption by several percentage points.