Category Archives: Lithography

Samsung Electronics Co., Ltd. today announced that it has completed all process technology development and has started wafer production of its revolutionary process node, 7LPP, the 7-nanometer (nm) LPP (Low Power Plus) with extreme ultraviolet (EUV) lithography technology. The introduction of 7LPP is a clear demonstration of Samsung Foundry’s technology roadmap evolution and provides customers with a definite path to 3nm.

Samsung’s newest EUV fab under construction in Hwaseong, South Korea (Photo: Business Wire)

The commercialization of its newest process node, 7LPP gives customers the ability to build a full range of exciting new products that will push the boundaries of applications such as 5G, Artificial Intelligence, Enterprise and Hyperscale Datacenter, IoT, Automotive, and Networking.

“With the introduction of its EUV process node, Samsung has led a quiet revolution in the semiconductor industry,” said Charlie Bae, executive vice president of foundry sales and marketing team at Samsung Electronics. “This fundamental shift in how wafers are manufactured gives our customers the opportunity to significantly improve their products’ time to market with superior throughput, reduced layers, and better yields. We’re confident that 7LPP will be an optimal choice not only for mobile and HPC, but also for a wide range of cutting-edge applications.”

The characteristics and benefits of EUV technology

EUV uses 13.5nm wavelength light to expose silicon wafers as opposed to conventional argon fluoride (ArF) immersion technologies that are only able to achieve 193nm wavelengths and require expensive multi-patterning mask sets. EUV enables the use of a single mask to create a silicon wafer layer where ArF can require up to 4 masks to create that same layer. Consequently Samsung’s 7LPP process can reduce the total number of masks by about 20% compared to non-EUV process, enabling customers to save time and cost.

The EUV lithography improvements also deliver increased performance, lower power and smaller area while improving design productivity by reducing multi-patterning complexity. Compared to its 10nm FinFET predecessors, Samsung’s 7LPP technology not only greatly reduces the process complexity with fewer layers and better yields, but also delivers up to a 40% increase in area efficiency with 20% higher performance or up to 50% lower power consumption.

The road to EUV technology

Since Samsung’s research and development in EUV began in the 2000s, the company has made outstanding progress through collaborative partnerships with industry-leading tool providers to design and install completely new equipment in its manufacturing facilities to ensure the stability of EUV wafers. The initial EUV production has started in Samsung’s S3 Fab in Hwaseong, Korea.

By 2020, Samsung expects to secure additional capacity with a new EUV line for customers who need high-volume manufacturing for next-generation chip designs. As an EUV pioneer, Samsung has also developed proprietary capabilities such as a unique mask inspection tool that performs early defect detection in EUV masks, allowing those defects to be eliminated early in the manufacturing cycle.

“Commercialization of EUV technology is a revolution for the semiconductor industry and will have a huge impact on our everyday lives,” said Peter Jenkins, vice president of corporate marketing at ASML. “It is our great pleasure to collaborate with Samsung and other leading chip makers on this fundamental shift in semiconductor process manufacturing.”

7nm LPP EUV Ecosystem

The Samsung Advanced Foundry Ecosystem™ is also fully prepared for the introduction of 7LPP with EUV. Ecosystem partners across the industry will be providing Foundation and Advanced IP, Advanced Packaging, and Services to fully enable Samsung customers to develop their products on this new platform. From high-performance and high-density standard cells to HBM2/2e memory interfaces and 112G SerDes interfaces, SAFE™ is ready to help customers implement their designs on 7LPP.

With tremendous growth of smartphones over the past decade, foundry sales to the communications market have soared and are now forecast to account for about 3x more than IC foundry sales to the computer market in 2018, based on IC Insights’ extensive part-two analysis of the integrated circuit foundry business in the September Update to The 2018 McClean Report (Figure 1).

Figure 1

Ten years ago, computers/computing systems were easily the largest application for pure-play IC foundry sales, but a relatively flat tablet PC market and lackluster desktop and notebook PC sales since 2011 contributed to weak pure-play foundry sales into the computer segment.

Now, new server applications targeting artificial intelligence (AI), the Internet of Things, Cloud Computing, and cryptocurrency are forecast to breathe new life into this market segment over the next five years. TSMC expects its IC sales into the IoT segment will grow by a CAGR of more than 20% from 2017 through 2022 (the company had greater than $1.0 billion in IoT sales in 2017).

Although IC foundry sales for computer applications are expected to surge 41% this year (driven by TSMC’s cryptocurrency device sales), the communications foundry market is still expected to be about 3x the size of the computer segment in 2018.  The communications foundry market is forecast to display only a 2% growth rate in 2018, six points less than the total pure-play foundry market growth rate expected for this year.

Overall, the communications (52%), computer (19%), and consumer (13%) market segments are forecast to represent 84% of the pure-play IC foundry market in 2018.

By Emir Demircan

SEMI today confirmed its support for a Joint-Industry Cooperation on an RoHS Review aimed at urging the European Commission to, at a minimum, consider dedicating more resources to a targeted outreach programme with third countries. The Joint-Statement is as follows:

Since its inception in 2002, the RoHS Directive has become a global reference point for regulation of hazardous substances in electrical and electronic equipment (EEE). This has been effective and given the EU a competitive advantage. The worldwide impact of RoHS is significant and the undersigned associations consider that this should be considered in the roadmap for reviewing the Directive.

RoHS-type laws have been introduced or are currently being introduced in more than 40 jurisdictions outside the European Economic Area (EEA). These include China, India, the Eurasian Customs Union and the Gulf States. Sometimes RoHS is copied exactly. However, often it is not. For example, countries might introduce a completely different approach on the scope, exemptions and declaration of conformity. Each time a new “RoHS” law is proposed, industry has to establish a bi-lateral dialogue with the relevant local public authorities improving the knowledge and understanding of regulatory stakeholders based on experience with the framework legislation in the EEA. Industry continues to spend a lot of time and money to ensure alignment with EU RoHS as far as possible. This is crucial for the global and complex EEE supply chains.

The European Commission’s DG TRADE “Market Access” services have been helpful with draft laws that have been notified to the WTO and have raised concerns with the Technical Barriers to Trade (TBT) Committee as well as bi-laterally with the countries in question. A recent example was the draft legislation in the United Arab Emirates.

Each time the EU updates the legislation, for example, withdrawing, renewing or granting an exemption, adding a substance, this will have a domino effect on the rest of the world.

To this end, we urge the Commission to, at a minimum, consider dedicating more resources to a targeted outreach programme with third countries. The EU recently adopted a Regulation on responsible minerals supply chains and DG TRADE subsequently launched such outreach with the United States, China, India, United Arab Emirates, Colombia, Mexico, South Africa, Malaysia, Thailand and Canada.

We, the undersigned associations, endorse the Commission’s roadmap for the evaluation and the aim to review and improve the effectiveness, efficiency, relevance of the RoHS Directive, as well as coherence with other EU laws and policies. However, we feel this important global dimension is absent and should be incorporated into the Review.

The Joint-Statement with the full list of participating associations can be accessed here.

SEMI encourages its members to communicate the Joint-Statement at regional and national levels. For more information, contact Emir Demircan, senior manager Advocacy and Public Policy, SEMI Europe, at [email protected].

Total wafer shipments in 2018 year are expected to eclipse the all-time market high set in 2017 and continue to reach record levels through 2021, according to SEMI’s recent semiconductor industry annual silicon shipment forecast. The forecast of demand for silicon units for the period 2018 through 2021 shows polished and epitaxial silicon shipments totaling 12,445 million square inches in 2018; 13,090 million square inches in 2019; 13,440 million square inches in 2020, and 13,778 million square inches in 2021 (see table below).

“As new greenfield fab projects continue to emerge for memory and foundry, silicon shipments are expected to remain strong for 2019 and through 2021,” said Clark Tseng, director of Industry Research & Statistics at SEMI. “Silicon demand will continue to grow as semiconductor content increases in mobile, high-performance computing, automotive, and Internet of Things applications.”

2018 Silicon* Shipment Forecast (MSI = Millions of Square Inches)
Actual
Forecast
2016
2017
2018
2019
2020
2021
MSI
10,577
11,617
12,445
13,090
13,440
13,778
Annual Growth
3.0%
9.8%
7.1%
5.2%
2.7%
2.5%

*Total Electronic Grade Silicon Slices – Excludes Non-Polished Wafers

*Shipments are for semiconductor applications only and do not include solar applications

Source: SEMI (www.semi.org), October 2018

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or chips are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers shipped by the wafer manufacturers to the end-users. Data do not include non-polished or reclaimed wafers.

The average revenue generated from processed wafers among the four biggest pure-play foundries (TSMC, GlobalFoundries, UMC, and SMIC) is expected to be $1,138 in 2018, when expressed in 200mm-equivalent wafers, which is essentially flat from $1,136 in 2017, according to a new analysis by IC Insights (Figure 1).  The average revenue per wafer among the Big 4 foundries peaked in 2014 at $1,149 and then slowly declined through last year, based on IC Insights’ extensive part-two analysis of the integrated circuit foundry business in the September Update to The 2018 McClean Report.

Figure 1

TSMC’s average revenue per wafer in 2018 is forecast to be $1,382, which is 36% higher than GlobalFoundries’ $1,014.  UMC’s average revenue per wafer in 2018 is expected to be only $715, about half of the projected amount at TSMC this year.  Furthermore, TSMC is the only foundry among the Big 4 that is expected to generate higher revenue per wafer (9% more) in 2018 than in 2013.  In contrast, GlobalFoundries, UMC, and SMIC’s 2018 revenue per wafer averages are forecast to decline by 1%, 10%, and 16%, respectively, compared to 2013.

Although the average revenue per wafer of the Big 4 foundries is forecast to be $1,138 this year, the amount generated is highly dependent upon the minimum feature size of the IC processing technology. Figure 2 shows the typical 2Q18 revenue per wafer for some of the major technology nodes and wafer sizes produced by pure-play foundries.  In 2Q18, there was more than a 16x difference between the 0.5µ 200mm revenue per wafer ($370) and the ≤20nm 300mm revenue per wafer ($6,050).  Even when using revenue per square inch, the difference is dramatic ($7.41 for the 0.5µ technology versus $53.86 for the ≤20nm technology).  Since TSMC gets such a large percentage of its sales from ≤45nm production, its revenue per wafer is expected to increase by a compound annual growth rate (CAGR) of 2% from 2013 through 2018 as compared to a -2% CAGR for the total revenue per wafer average of GlobalFoundries, UMC, and SMIC during this same timeperiod.

Figure 2

There will probably be only three foundries able to offer high-volume leading-edge production over the next five years (i.e., TSMC, Samsung, and Intel).  IC Insights believes these companies are likely to be fierce competitors among themselves—especially TSMC and Samsung—and as a result, pricing will likely be under pressure through 2022.

Data provided by the Semiconductor Industry Association (SIA) indicates that worldwide sales of semiconductors reached USD 40.16 Billion for the month of August 2018, representing an increase of 14.9% when compared to the August 2017 total of USD 34.96 Billion. Global sales in August 2018were 1.7% higher than the July 2018 total of USD 39.49 Billion. The semiconductor industry is one of the fastest growing industries of the technology sector. According to Stratistics MRC, many semiconductor companies are beginning to embrace IoT to drive new revenue and growth models. Squire Mining Ltd. (OTC: SQRMF), Taiwan Semiconductor Manufacturing Company Limited (NYSE: TSM), Applied Materials, Inc. (NASDAQ: AMAT), Qorvo, Inc. (NASDAQ: QRVO), Entegris, Inc. (NASDAQ: ENTG)

According to a recent report by Accenture, the semiconductor industry is the most bullish sector when it comes to the integration of blockchain within their industry and the impact of artificial intelligence. “Throughout the industry’s complex supply chain, blockchain simplifies business operations leveraging semiconductor chips and related technologies,” said Syed Alam, a Managing Director in Accenture Strategy who leads Accenture’s Semiconductor practice. “This faster traceability will improve companies’ business operations and accelerate delivery of their products to market – while enabling them to do so at lower costs. Semiconductor companies can also use blockchain to create, scale and manage technology-based collaborations and redefine future business transactions.”

Squire Mining Ltd. (OTCQB: SQRMF) is also listed on the Canadian Securities Exchange under the ticker (CSE: SQR). Just earlier today, the company announced breaking news that, “Ennoconn Corporation (“Ennoconn”) as our hardware manufacturer for next generation mining systems to mine Bitcoin Cash, Bitcoin and other associated cryptocurrencies. Ennoconn is a leading industrial motherboard designer and total hardware system solution provider headquartered in Taipei, Taiwan and listed on the Taiwan stock exchange (TPE:6414). In 2007, Foxconn Technology Group, the largest “Electronic Manufacturing Service” company in the world, became the majority shareholder of Ennoconn, forming a strong strategic alliance in embedded system and electronic manufacturing.

On August 21, 2018, Squire announced that AraSystems Technology Corp. (“AraSystems”), a subsidiary of Squire, had entered into a provisional non-binding agreement with a major global technology assembly company. This company, now revealed to be Ennoconn, will assist in the design and assembly of our next generation mining rig at such time as a working prototype of our debut ASIC chip is completed.

On October 3, 2018 Squire announced the successful completion and testing of its FPGA working prototype microchip, with early results of the terahash-to-energy consumption ratio, indicating that the final ASIC chip and mining system has the potential to reduce operational costs by up to 40% for enterprise mining facilities.

● This cost reduction was estimated by one leading enterprise mining group to be worth up to $60M per year in savings to their operations alone.

● The final ASIC chip and mining system together are expected to provide up to a four times improvement in the performance of mining the blockchain, a process that enables miners to be paid, thereby increasing the return on investment, and profit, for miners. Such calculations are based on comparisons with the majority of current generation mining machines operating inside enterprise facilities around the world.

Following this success, the Company has signed a binding Memorandum of Understanding with Ennoconn and funded work to commence Phase 1 design and development of AraSystem’s next generation mining system in collaboration with its partners in Taipei, Taiwan and in Seoul, South Korea. Definitive documentation will be entered into following delivery of final specifications and data sheets to Ennoconn later this month.

Squire’s engineers are currently working with Ennoconn to design and develop AraSystem’s mining rig which will house the debut ASIC chip currently under development by the Company’s subsidiary AraCore Technology Corp (“AraCore”), in conjunction with GaonChips and Samsung Electronics (see news releases dated September 25 and October 3, 2018). In turn, Ennoconn will be responsible for mass assembly of the mining rig once all design, development and testing work has been completed.

A prototype of the mining rig along with full specifications of the AraCore ASIC chip are expected to be presented at the CoinGeek Conference in London on November 28 – 30, 2018, with presales expected to commence on or around that date. Significant interest has already been expressed by several of the industry’s largest enterprise mining companies, which currently host hundreds of thousands of mining machines in their facilities across the world.”

‘We are very pleased to be partnering with the skilled engineers at Ennoconn, one of the world’s leading electronic manufacturing companies,’ stated Simon Moore, Executive Chairman and CEO of Squire. ‘As we launch our next generation mining rig with a suite of proprietary innovations, it’s imperative that our manufacturing partners have the talent, experience and capacity to not only deliver unique hardware, but also deliver best in class quality. We believe Ennoconn will help ensure the production of an exceptional mining rig for the marketplace,’ he said. Further, Mr. Moore noted, ‘based on initial interest from the sector, the potential for significant sales and the subsequent revenue for Squire is on track in the coming year which would make Squire and its partners a noteworthy industry provider of crypto mining hardware and next generation innovation on a global scale.’

Taiwan Semiconductor Manufacturing Company Limited (NYSE: TSM) is the world’s largest dedicated semiconductor foundry, providing the industry’s leading process technology and the foundry segment’s largest portfolio of process-proven libraries, IPs, design tools and reference flows. TSMC recently announced the initial availability of its Open Innovation Platform® Virtual Design Environment (OIP VDE), which enables semiconductor customers to securely design in the cloud, leveraging TSMC OIP design infrastructures within the flexibility of cloud infrastructures. OIP VDE is the result of TSMC collaboration with TSMC OIP design ecosystem partners and leading cloud providers to deliver a complete systems-on-chip (SoCs) design environment in the cloud. TSMC OIP VDE’s first implementations of digital RTL-to-GDSII and custom schematic capture-to-GDSII flows are via partnerships with TSMC’s inaugural Cloud Alliance partners, Amazon Web Services (AWS), Cadence, Microsoft Azure, and Synopsys. In TSMC’s enablement of OIP VDE, both digital and custom design flows have been validated in the cloud, along with OIP design collateral-including process technology files, PDKs, foundation IP, and reference flows. To ensure low barriers to entry and high technical support levels, Cadence and Synopsys act as the focal point helping customers to set up VDE and providing first line support.

Applied Materials, Inc. (NASDAQ: AMAT) is a developer of materials engineering solutions used to produce virtually every new chip and advanced display in the world. Applied Materials recently celebrated the 20th anniversary and 5,000th shipment of the Producer® platform, a manufacturing system that helps make virtually every chip in the world. The Producer platform was launched in July of 1998 to help enable chips to run faster by changing their wiring from aluminum to copper, which is a better conductor. The transition was needed by the industry to drive the performance and power improvements associated with Moore’s Law, but it also required many additional steps that could have made the progress unaffordable. To help, Applied Materials designed every element of the Producer platform to give customers the highest performance at the lowest possible operating cost. “With the landmark Producer platform, Applied achieved something that had never been done before on this scale: create a highly flexible architecture that can support multiple technology generations and still remain incredibly productive,” said G. Dan Hutcheson, Chief Executive Officer of VLSIresearch. “Today, the Producer platform continues to allow chipmakers to imagine and build chips in entirely new ways. Congratulations to Applied Materials on this impressive milestone for one of the most important process systems in the semiconductor industry.”

Qorvo, Inc. (NASDAQ: QRVO) recently introduced a new System in Package (SiP) that enables dynamic, simultaneous support for Zigbee® 3.0, Green Power, Thread and Bluetooth Low Energy (BLE). This new SiP integrates Qorvo power amplifier technology providing 20 dBm output, which is especially important for U.S. smart home applications. The Qorvo QPG6095M is a fully integrated SiP for ultra-low power wireless communications. It is BLE 5.0 and Zigbee 3.0 platform and product certified, and offers Green Power energy efficiency. This SiP also extends range and battery life and enables robust interference mitigation. The QPG6095M delivers optimized connectivity throughout the home, eliminating the need for complex mesh architectures and unnecessary battery consumption in intermediate devices. The QPG6095M blends Qorvo’s power amplifier (PA) technology with a multi-standard, multi-protocol chip. Its level of integration and performance benefit product designers by lowering development costs and speeding time to market. Cees Links, General Manager of Qorvo’s Wireless Connectivity business unit, said, “This new SiP is another example of Qorvo’s commitment to combining and leveraging RF technologies to improve the consumer’s connected experience. Developers can now deliver BLE, Zigbee and Thread simultaneously with more range and reliability, and reduce concerns about future compatibility.”

Entegris, Inc. (NASDAQ: ENTG) is a developer and provider of specialty chemicals and advanced materials solutions for the microelectronics industry and other high-tech industries. Entegris, Inc. recently released the next generation EUV 1010 Reticle Pod for high-volume IC manufacturing using extreme ultraviolet (EUV) lithography. Developed in close collaboration with ASML, one of the world’s largest manufacturers of chip-making equipment, Entegris’s EUV 1010 is the first to be qualified by ASML for use in the NXE:3400B and beyond. As the semiconductor industry begins ramping EUV lithography for the high-volume manufacturing (HVM) of advanced technology nodes, keeping EUV reticles defect-free is more demanding than ever. Entegris’s EUV 1010 Reticle Pod is now fully qualified by ASML for their latest generation scanner having demonstrated outstanding protection of the EUV reticles, including against the most critical particle challenges. As a result, Entegris’s EUV 1010 enables customers to safely transition to smaller and smaller line widths, as needed for the most advanced lithography processes.

Toshiba Memory Corporation (TMC) today announced the appointment of Stacy J. Smith as Executive Chairman, effective on October 1, 2018.

Smith brings a long and proven track record of executive leadership to TMC. He has extensive international experience, having both lived and led organizations in the Asia-Pacific, Latin America, Europe, the Middle East and Africa. He will work closely with CEO Yasuo Naruke to provide overall leadership to the business.

Smith previously spent three decades at Intel leading organizations across multiple disciplines. In his role as President, Manufacturing, Operations and Sales, from 2016 to 2018, he led 40,000 employees involved in worldwide manufacturing, technology development, supply chain, pricing and sales. He also served as Intel’s Chief Financial Officer for almost a decade and in this role also had responsibility for corporate strategy, M&A, and Intel Capital. Prior to that he served as Intel’s Chief Information Officer and Vice President for Sales for Europe, the Middle East and Africa.

Smith also brings strong board leadership experience. He currently serves as board chairman at Autodesk and as a director for Metromile. He served previously as a director for Virgin America and for GEVO. He also serves on the Board of Trustees for The Nature Conservancy of California and on the University of Texas McCombs School of Business Advisory Board. Smith attended The University of Texas at Austin, where he received his MBA in 1988 and his BBA in 1985.

“We are thrilled that Stacy is joining Toshiba Memory Corporation in this crucial leadership role at an important time in the company’s history,” said Yasuo Naruke, President and CEO of TMC. “With Stacy’s wealth of international leadership experience and knowledge of the semiconductor space, there is no doubt he is the perfect person to help lead our company in the next phase of growth as an independent company.”

“I am excited to take on this important challenge, and honored to join the TMC team,” said Smith. “Toshiba invented flash memory, and with TMC now operating as an independent company with increased capacity to invest in developing and growing semiconductor technology, the company has a strong growth trajectory ahead of it.”

Smith’s hiring follows the acquisition this year of TMC by an industry consortium led by Bain Capital Private Equity. Bain Capital Private Equity has a long history of successful investments in Japan including Skylark, Jupiter Shop Channel, BellSystem24, Domino’s Pizza Japan, Ooedo Onsen, and Asatsu-DK. The firm’s deep market knowledge, extensive local networks and expertise in driving operational improvement strategies have made Bain Capital a valued partner for Japanese companies.

“Stacy is the right leader to help TMC, already a technology leader in the flash memory industry, achieve its potential as an independent company,” said David Gross-Loh, a director of TMC and a managing director and co-head of Asia for Bain Capital Private Equity. “We are very pleased to welcome Stacy to TMC and look forward to working closely with him and the expanded management team.”

By Alan Weber

Even for someone who has been in this industry since the days of the TI Datamath 4-function calculator and the TMS1100 4-bit microcontroller (yes, that’s been a LONG time – the movie Grease premiered the same year!), it is sometimes hard to grasp the scope and complexity of what happens in today’s leading-edge semiconductor gigafabs. In fact, the only way to comprehend the enormous volume of transactions that occur is to consider what happens in a single minute – this is illustrated in the infographic we have labeled “The Gigafab Minute.”*

It’s amazing enough to think that a single factory can start 100,000 wafers every month on their cyclical journey through 1500 process steps… and have 99%+ of them emerge 4 months later to be delivered to packaging houses and then on to waiting customers. It’s quite another to realize that all of this happens continuously (24 x 7) and automatically.

“How is this possible?” you ask.

Well, a big part of the solution is the body of SEMI standards which have evolved since the early 80s to keep pace with the ever-changing demands of the industry. From an automation standpoint, many of these standards deal with the communications between manufacturing equipment and the factory information and control systems that are essential for managing these complex, hyper-competitive global enterprises.

A significant characteristic of these standards is that they have been carefully designed to be “additive.” This means that new generations of SEMI’s communications standards do not supplant or obsolete the previous generations, but rather provide new capabilities in an incremental fashion. To appreciate the importance of this in actual practice, consider how the GEM, GEM300, and EDA/Interface A standards support the transactions that occur in a single Gigafab Minute.

Starting at 1:00 o’clock on the infographic and moving clockwise, you first notice that 2.31 wafers enter the line. Of course, these are actually released in 25-wafer 300mm FOUPs (Front-Opening Unified Pod), but 100K wafers per month translates to 2.31 per minute. Since these factories run continuously, once the line is full, it stays full. And with an average total cycle time of 4 months, this means that there are 400K wafers of WIP (work in process) in the factory at any given time. This number, and the total number of equipment (5000+), drive the rest of the calculations.

GEM (Generic Equipment Model) – SEMI E30, etc.

The GEM messaging standards were initially defined in the early 90s to support the factory scheduling and dispatching applications that decide what lots should go to what equipment, the automated material handling systems that deliver and pick-up material to/from the equipment accordingly, the recipe management systems that ensure each process step is executed properly, and the MES (Manufacturing Execution System) transactions that maintain the fidelity of the factory system’s “digital twin.”

Every minute of every day, GEM messages support and chronicle the following activities: 240 process steps are completed (i.e., 240 25-wafer lots are processed), 300 recipes are downloaded along with a set of run-specific adjustable control parameters, and 600 FOUPs are moved from one place to another (equipment, stockers, under-track storage, etc.). For each of these activities, the factory’s MES is notified instantaneously.

GEM300 – SEMI E40, E87, E90, E94, E157

With the advent of 300mm manufacturing in the mid-to-late 90s, a global team of volunteer system engineers from the leading chip makers defined the GEM300 standards to support fully automated manufacturing operations. Starting at 5:00 o’clock on the infographic, the number of transactions per minute jumps almost 3 orders of magnitude, from the monitoring of 900 control jobs across 4000 process tools to the tracking of 360,000 individual recipe step change events. This level of event granularity is essential for the latest generation of FDC (Fault Detection and Classification) applications, because precise data framing is a key prerequisite for minimizing the false alarm rate while still preventing serious process excursions. In this context, more than 6000 recipe-, product- and chamber-specific fault models may be evaluated every minute.

Simultaneously, the applications that monitor instantaneous throughput to prevent “productivity excursions” and identify systemic “wait time waste” situations depend on detailed intra-tool wafer movement events. In a fab with hundreds of multi-chamber, single-wafer processes, 75,000 or more of these events occur every minute.

EDA (Equipment Data Acquisition) – SEMI E120, E125, E132, E134, E164, etc.

Rounding out the SEMI standards in our example gigafab is the suite of EDA standards which complement the command and control functions of GEM/GEM300 with flexible, high-performance, model-based data collection. The EDA standards enable the on-demand collection of the volume and variety of “big data” required from the equipment to support the advanced analysis, machine learning, and other AI (Artificial Intelligence) applications that are becoming increasingly prevalent in leading semiconductor manufacturers. As EUV (Extreme Ultraviolet) lithography moves from pilot production to high-volume manufacturing at the 7nm process node and beyond, the litho process area will become a major source of process data by itself, generating 10 GB of data every minute. This is in addition to the 100 GB of data collected from other process areas.

The End Result

The final wedge (12:00 o’clock) in our infographic highlights the real objective – which is producing the millions of integrated circuits that fuel our global economy and provide the technologies that are an integral part of our modern way of life. Assuming a nominal die size of 50 square mm (typical of an 8 GB DRAM), the 2.31 wafers we started at 1:00 o’clock result in almost 3200 individual chips. But none of this would be possible without the pervasive factory automation technology we now take for granted. So, as you finish reading this posting on whatever device you happen to be using, take a micro-moment to acknowledge and thank the hundreds of standards volunteers whose insights and efforts made this a reality!

You may not be responsible for running a gigafab anytime soon, but the SEMI standards used in this setting are no less applicable to any Smart Manufacturing environment. Give us a call if you’d like to know more about how these technologies can benefit your operations for many years to come.

Alan Weber is Vice President, New Product Innovations, at Cimetrix Incorporated. Previously he served on the Board of Directors for eight years before joining the company as a full-time employee in 2011. Alan has been a part of the semiconductor and manufacturing automation industries for over 40 years. He holds bachelor’s and master’s degrees in Electrical Engineering from Rice University.

Originally published on the SEMI blog.

According to data compiled by Inkwood Research, the global semiconductor market is projected to grow at a CAGR of 7.67% during the forecast period from 2017 to 2024. Data reflects that the market is driven by rising demand for consumer electronics, the growing automotive semiconductor market, the emerging internet of things (IoT) market and investments into New Product Development and R&D. Consumer electronics are primarily fueling the market due to demand for products such as tablets, smartphones, laptops and wearable devices. As semiconductor technology begins to advance, new segments are swiftly being integrated into the market, such as Machine Learning. Squire Mining Ltd. (OTC: SQRMF), Intel Corporation (NASDAQ: INTC), Texas Instruments Incorporated (NASDAQ: TXN), NXP Semiconductors N.V. (NASDAQ: NXPI), Skyworks Solutions, Inc. (NASDAQ: SWKS)

According to data by MarketsandMarkets, the global machine learning sector is expected to grow from USD 1.41 Billion in 2017 to USD 8.81 Billion in 2022 while registering a CAGR of 44.1% during the forecast period. The segment is rapidly growing due to many businesses adopting machine learning to gather intelligence for security and consumer interaction benefits, which can help eliminate human errors. However, machine learning is also being integrated into modern day technology, such as the automotive industry, to build autonomous vehicles. In a report by Forbes, Daniel Newman Principal Analyst and Founding Partner of Futurum Research, explained, “When dealing with a technology as advanced as machine learning, there simply isn’t an industry that would not benefit. I mean how could a business not take advantage of a technology that would make them more successful? In the next year, there will be multiple new uses for machine learning in all of these industries available for the taking and I’m not just talking about in marketing and sales.”

Squire Mining Ltd. (OTCQB: SQRMF) is also listed on the Canadian Securities Exchange under the ticker (CSE: SQR). Yesterday, the Company announced breaking news that, “to report on its prototype ASIC chip testing event held in Seoul, South Korea. With executives and board members from Squire, Future Farm, CoinGeek, Gaonchips and Samsung Electronics in attendance, Peter Kim, President of Squire’s subsidiary AraCore Technology Corp. (“Aracore”), and his team of front-end microchip engineers and programmers, unveiled and tested a working prototype mining system comprised of a newly engineered FPGA (field programmable gate array) ASIC microchip that will be converted into AraCore’s first ASIC chip utilizing 10 nanometer technology for mining Bitcoin Cash, Bitcoin and other associated cryptocurrencies. The test results confirm Aracore’s original design specifications indicating that the ASIC chip, once mass manufactured by Samsung Electronics, will be capable of delivering a projected hash rate of 18 to 22 terahash per second (TH/s) with an energy consumption of between 700 and 800 watts.

Taras Kulyk, Chief Executive Officer of CoinGeek Mining and Hardware, said ‘The CoinGeek team is very pleased with the progress of our strategic partners; Squire Mining and Aracore. With this next generation technology, CoinGeek will continue to pull the blockchain industry out of the proverbial basement and into the boardroom.’

Stefan Matthews, Chairman of nChain, one of the industry leaders in blockchain research and development, and a director of Squire Mining added, ‘The early results indicate that this ASIC microchip has the potential to be the next generation leader in providing hash power for enterprise mining of Bitcoin Cash and other associated crypto currencies. It has also demonstrated the potential to rapidly process consensus protocols across the blockchain faster whilst utilizing less energy than anything currently in this sector.’

Hash rate speed and microchip efficiency are the two most important measuring criteria in the crypto-mining industry to enable end-users to maximize profitability and ROI in their day to day mining operations.

Simon Moore, Executive Chairman and CEO of Squire Mining, stated, ‘Aracore’s time and investment to date have been validated by the impressive results of this new microchip. Once completed, we believe the speed and efficiency of our ASIC microchip combined with our respective mining systems powered by this Samsung manufactured microchip together have the potential to substantially increase the profitability of enterprise mining facilities around the globe. We look forward to releasing our mining system to the market in the first half of next year through our exclusive distribution partners CoinGeek, and competing for a significant piece of this multi-billion-dollar enterprise mining market.’

ANSYS (NASDAQ: ANSS) announced TSMC certified ANSYS solutions for the 7 nanometer FinFET Plus (N7+) process node with extreme ultraviolet lithography (EUV) technology and validated the reference flow for the latest Integrated Fan-Out with Memory on Substrate (InFO_MS) advanced packaging technology. The certifications and validations are vital for fabless semiconductor companies that require their simulation tools to pass rigorous testing and validation for new process nodes and packaging technologies.

ANSYS® RedHawk™ and ANSYS® Totem™ are certified for TSMC N7+ process technology that provides EUV-enabled features. Certification for N7+ includes extraction, power integrity and reliability, signal electromigration (EM) and thermal reliability analysis.

Industry-leading TSMC InFO advanced packaging technology is extended to integrate memory subsystem with logic die. TSMC and ANSYS enhanced the existing InFO design flow to support the new InFO_MS packaging technology, and validated the reference flow using ANSYS SIwave-CPA, ANSYS® RedHawk-CPA™, ANSYS® RedHawk-CTA™, ANSYS® CMA™ and ANSYS® CSM™ with the corresponding chip models. The InFO_MS reference flow includes die and package co-simulation and co-analysis for extraction, power and signal integrity analysis, power and signal electromigration analysis and thermal analysis.

“TSMC and ANSYS’ latest N7+ certification and InFO_MS enablement empowers customers to address growing performance, reliability and power demands for their next generation of chips and packages,” said Suk Lee, Senior Director of Design Infrastructure Marketing Division at TSMC.

“The number of smart, connected electronic devices continues to grow and manufacturers must keep pace to design power efficient, high-performing and reliable products at a lower cost and with a smaller footprint,” said John Lee, General Manager at ANSYS. “ANSYS semiconductor solutions address complex multi-physics challenges such as power, thermal, reliability and impact of process variation on product performance. ANSYS’ comprehensive Chip Package System solutions for chip aware system and system aware chip signoff help mutual customers accelerate design convergence with greater confidence.”