Category Archives: Manufacturing

SEMI today announced that all legal requirements have been met for the ESD (Electronic Systems Design) Alliance to become a SEMI Strategic Association Partner.

Full integration of the Redwood City, California-based association representing the semiconductor design ecosystem is expected to be complete by the end of 2018. The integration will extend ESD Alliance’s global reach in the electronics manufacturing supply chain and strengthen engagement and collaboration between the semiconductor design and manufacturing communities worldwide.

As a SEMI Strategic Association Partner, the ESD Alliance will retain its own governance and continue its mission to represent and support companies in the semiconductor design ecosystem.

The ESD Alliance will lead its strategic goals and objectives as part of SEMI, leveraging SEMI’s robust global resources including seven regional offices, expositions and conferences, technology communities and activities in areas such as advocacy, international standards, environment, health and safety (EH&S) and market statistics.

With the integration, SEMI adds the design segment to its electronics manufacturing supply chain scope, connecting the full ecosystem. The integration is a key step in streamlining SEMI members’ collaboration and connection with the electronic system design, IP and fabless communities. The Strategic Association Partnership will also enhance collaboration and innovation across the collective SEMI membership as ESD Alliance members bring key capabilities to SEMI’s vertical application platforms such as Smart Transportation, Smart Manufacturing and Smart Data as well as applications including AI and Machine Learning.

“The addition of ESD Alliance as a SEMI Strategic Association Partner is a milestone in our mission to drive new efficiencies across the full global electronics design and manufacturing supply chain for greater collaboration and innovation,” said Ajit Manocha, president and CEO of SEMI. “This partnership provides opportunities for all SEMI members for accelerated growth and new business opportunities in end-market applications. We welcome ESD Alliance members to the SEMI family.”

“Our members are excited about becoming part of SEMI’s broad community that spans the electronics manufacturing supply chain,” said Bob Smith, executive director of the ESD Alliance. “Global collaboration between design and manufacturing is a requirement for success with today’s complex electronic products. Our new role at SEMI will help develop and strengthen the connections between the design and manufacturing communities.”

All ESD Alliance member companies, including global leaders ARM, Cadence, Mentor, a Siemens business, and Synopsys, will join SEMI’s global membership of more than 2,000 companies while retaining ESD Alliance’s distinct self-governed community within SEMI.

By Laith Altimime

In a bid to reinvigorate Europe’s electronics strategy and strengthen the region’s position in key emerging technologies, European electronics industry CEOs in June called on public and private actors to accelerate collaboration at the European Union and national levels. The CEO’s proposed new strategic actions include creating a European Design Alliance to pool the expertise of design houses and forming an electronics education and skills task force consisting of representatives from industry, research, European institutions, member states and SEMI.

The business executive’s calls – embodied in “Boosting Electronics Value Chain in Europe,” a report submitted to Mariya Gabriel, Commissioner for Digital Economy and Society, of the European Commission – come as global competition in the electronics industry intensifies. The document highlights Europe’s need to buttress its position amongst others in artificial intelligence (AI), autonomous driving and personalized healthcare – applications that rely on new semiconductor architectures, materials, equipment and design methodologies.

The European semiconductor industry plans to pour more than 50 billion EUR into technology development and innovation by 2025, deepening its investments in research, innovation and manufacturing to help drive Europe’s digital transformation.

For its part, SEMI, as the industry association connecting the electronics value chain, is well-positioned to bring together member companies and public actors to address key challenges facing the sector. This year in April, SEMI announced that Electronics System Design Alliance (ESD Alliance) will join SEMI, adding key electronics design companies to SEMI membership and unlocking the full potential of collaboration between electronics design and manufacturing.  With the ESD Alliance, SEMI adds the product design segment to the electronics supply chain, streamlining and connecting the full ecosystem. The integration also promises to support the industry coordination required to develop specialized (AI) chips used in various smart applications.

SEMI Europe is also accelerating its education and workforce development activities. SEMI Europe this year created its Workforce Development Council Europe, chaired by Emir Demircan, SEMI Europe’s senior manager of public policy, based in Brussels. The council is designed to connect electronics industry human resources representatives with members to evolve best practices in hiring that help Europe gain, train and retain world-class talent.

Other SEMI Europe workforce development activities include the following:

  • SEMI member forums across Europe are helping young talent with career opportunities in the semiconductor industry.
  • In November, SEMICON Europa will host a Career Café where STEM students will explore careers in electronics design and manufacturing.
  • With the participation of representatives from the European Commission, SEMI Europe’s Industry Strategy Symposium in April focused on strategies for attracting more skilled workers into electronics design and manufacturing.

Looking ahead, semiconductor sales is forecast to reach USD 1 trillion by 2030. The global semiconductor industry is at the heart of a new era of connectivity, developing breakthrough solutions for ascendant data-driven technologies such as AI and Internet of Things (IoT). SEMI Europe’s role in strengthening the region’s position in the global electronics industry to help drive this extraordinary growth is critical. SEMI Europe will continue to foster public-private partnerships to tackle industry challenges that are too big, too risky and too costly for companies and government institutions to address alone.

Contact: Laith Altimime, President, SEMI Europe, [email protected] ; Emir Demircan, Sr Manager Public Policy, [email protected]

Originally published on the SEMI blog.

The semiconductor industry today is faced with several substantial issues-not the least of which are the continuing rise in design costs for complex SoCs, the decrease in the incidence of first-time-right designs and the increase in the design cycle time against shrinking market windows and decreasing product life cycles. An additional factor has now been added to SoC design costs with the emergence of very complicated software applications intended to run on the SoC silicon. The costs of the software effort have outstripped the silicon design costs and have become the major part of the cost of these designs. IP integration is also a growing part of design costs. Semico’s new report SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts addresses these and many other design concerns while reporting that the average design cost for Basic SoCs across all geometries in 2017 was $1.7 million.

“Analysis of design activity for the three types of SoC profiled in this report shows that while design costs at new nodes continue to increase, the average design cost at each node is not increasing as quickly, giving room for designers to still accomplish their silicon solutions at reasonable costs if they are prudent in their design selection,” says Rich Wawrzyniak, Sr. Market Analyst for ASIC & SoC at Semico. “For each of the three types of SoC there is still considerable activity at the older nodes of 90nm, 65nm and 40nm. Costs at these geometries are much less than at 10nm and 7nm so even though these newer designs cost much more, the average for all SoCs has dropped due to the increase in new designs for Basic SoC.”

Key findings of the report include:

  • The average design cost for Value Multicore SoCs across all geometries was $4.8M in 2017.
  • The average design cost for all SoCs across all geometries is forecast to increase to $5.3M by 2023.
  • The number of ‘first-time-right’ designs has dropped at every process geometry since the 180nm node.
  • Silicon design costs at the 7nm node for an Advanced Performance Multicore SoC first-time effort are projected to be 23% higher than at the 10nm node.

In a unique, insightful look at this constantly evolving market, Semico Research’s new report, SoC Silicon and Software 2018 Design Cost Analysis: How Rising Costs Impact SoC Design Starts, examines the primary forces and integration pressures that are driving this market today in 135 pages, with 41 tables and 64 graphs. This study analyzes many important questions facing the semiconductor industry today including:

  • What is the current cost for a Complex System-on-a-Chip (SoC) design, and what will it be in the near future?
  • Is it possible to do SoC designs without maximizing the costs for these designs?
  • What is the incidence of ‘first-time-right’ for these designs today and in the near future?
  • How is the design cycle time for these designs changing?
  • How do complicated software applications impact the design costs?
  • How fast are IP integration costs rising, and how high will they go?
  • What strategies are designers using to cope with rising design costs?
  • What is the average silicon design cost today for each process geometry and SoC type, and how quickly is it rising?
  • What impact will EDA tools that include some artificial intelligence (AI) and machine learning (ML) functionality have on design costs for complex silicon?

Keysight Technologies, Inc. (NYSE: KEYS), a technology company that helps enterprises, service providers, and governments accelerate innovation to connect and secure the world, announced the Keysight MX0100A InfiniiMax micro probe head, the industry’s smallest solder-in probe head for high performance oscilloscopes, optimized for modern high-speed devices.

The size of electronic devices continues to shrink, resulting in smaller pads and narrower pitch spacing. Additionally, as data rates for applications such as DDR memory increase, conventional probing pads work as a stub, becoming a source for electromagnetic interference (EMI). As a result, customers are actively seeking high density, small geometry solutions for probing modern electronic technologies to analyze and measure signals without interference.

Keysight’s new InfiniiMax micro probe head is a micro solder-in head for use with the company’s InfiniiMax I/II probe amplifiers and is designed to access small geometry target devices. The lead wires can be adjusted to accommodate targets from 0 mm to 7 mm apart. When used in conjunction with Keysight’s 1169B 12 GHz InfiniiMax II probe amplifier, the MX0100A delivers up to full 12 GHz bandwidth. Offering the best probe loading performance in its class (0.17 pF, 50 kΩ differentially), the extremely low input capacitance of the MX0100A minimizes the probe loading effect and maximizes signal integrity when measuring high-speed signals.

“Existing oscilloscope probe head solutions available today are even larger than the devices being tested in some cases. This makes signal probing access a continual challenge for modern electronic technologies,” said Dave Cipriani, Vice President of the Digital and Photonics Center of Excellence at Keysight Technologies. “Unlike conventional solder-in probe heads in this class, Keysight specifically designed this micro probe to be less than half the size of existing solder-in probe heads for high density, fine pitch devices. It is the first, and only, of its kind on the market today.”

A new way of arranging advanced computer components called memristors on a chip could enable them to be used for general computing, which could cut energy consumption by a factor of 100.

This would improve performance in low power environments such as smartphones or make for more efficient supercomputers, says a University of Michigan researcher.

This is the memristor array situated on a circuit board. Credit: Mohammed Zidan, Nanoelectronics group, University of Michigan.

“Historically, the semiconductor industry has improved performance by making devices faster. But although the processors and memories are very fast, they can’t be efficient because they have to wait for data to come in and out,” said Wei Lu, U-M professor of electrical and computer engineering and co-founder of memristor startup Crossbar Inc.

Memristors might be the answer. Named as a portmanteau of memory and resistor, they can be programmed to have different resistance states–meaning they store information as resistance levels. These circuit elements enable memory and processing in the same device, cutting out the data transfer bottleneck experienced by conventional computers in which the memory is separate from the processor.

However, unlike ordinary bits, which are 1 or 0, memristors can have resistances that are on a continuum. Some applications, such as computing that mimics the brain (neuromorphic), take advantage of the analog nature of memristors. But for ordinary computing, trying to differentiate among small variations in the current passing through a memristor device is not precise enough for numerical calculations.

Lu and his colleagues got around this problem by digitizing the current outputs–defining current ranges as specific bit values (i.e., 0 or 1). The team was also able to map large mathematical problems into smaller blocks within the array, improving the efficiency and flexibility of the system.

Computers with these new blocks, which the researchers call “memory-processing units,” could be particularly useful for implementing machine learning and artificial intelligence algorithms. They are also well suited to tasks that are based on matrix operations, such as simulations used for weather prediction. The simplest mathematical matrices, akin to tables with rows and columns of numbers, can map directly onto the grid of memristors.

Once the memristors are set to represent the numbers, operations that multiply and sum the rows and columns can be taken care of simultaneously, with a set of voltage pulses along the rows. The current measured at the end of each column contains the answers. A typical processor, in contrast, would have to read the value from each cell of the matrix, perform multiplication, and then sum up each column in series.

“We get the multiplication and addition in one step. It’s taken care of through physical laws. We don’t need to manually multiply and sum in a processor,” Lu said.

His team chose to solve partial differential equations as a test for a 32×32 memristor array–which Lu imagines as just one block of a future system. These equations, including those behind weather forecasting, underpin many problems science and engineering but are very challenging to solve. The difficulty comes from the complicated forms and multiple variables needed to model physical phenomena.

When solving partial differential equations exactly is impossible, solving them approximately can require supercomputers. These problems often involve very large matrices of data, so the memory-processor communication bottleneck is neatly solved with a memristor array. The equations Lu’s team used in their demonstration simulated a plasma reactor, such as those used for integrated circuit fabrication.

Researchers at the National Institute of Standards and Technology (NIST) have made a silicon chip that distributes optical signals precisely across a miniature brain-like grid, showcasing a potential new design for neural networks.

NIST’s grid-on-a-chip distributes light signals precisely, showcasing a potential new design for neural networks. The three-dimensional structure enables complex routing scheme, which are necessary to mimic the brain. Light could travel farther and faster than electrical signals. Credit: Chiles/NIST

The human brain has billions of neurons (nerve cells), each with thousands of connections to other neurons. Many computing research projects aim to emulate the brain by creating circuits of artificial neural networks. But conventional electronics, including the electrical wiring of semiconductor circuits, often impedes the extremely complex routing required for useful neural networks.

The NIST team proposes to use light instead of electricity as a signaling medium. Neural networks already have demonstrated remarkable power in solving complex problems, including rapid pattern recognition and data analysis. The use of light would eliminate interference due to electrical charge and the signals would travel faster and farther.

“Light’s advantages could improve the performance of neural nets for scientific data analysis such as searches for Earth-like planets and quantum information science, and accelerate the development of highly intuitive control systems for autonomous vehicles,” NIST physicist Jeff Chiles said.

A conventional computer processes information through algorithms, or human-coded rules. By contrast, a neural network relies on a network of connections among processing elements, or neurons, which can be trained to recognize certain patterns of stimuli. A neural or neuromorphic computer would consist of a large, complex system of neural networks.

Described in a new paper, the NIST chip overcomes a major challenge to the use of light signals by vertically stacking two layers of photonic waveguides–structures that confine light into narrow lines for routing optical signals, much as wires route electrical signals. This three-dimensional (3D) design enables complex routing schemes, which are necessary to mimic neural systems. Furthermore, this design can easily be extended to incorporate additional waveguiding layers when needed for more complex networks.

The stacked waveguides form a three-dimensional grid with 10 inputs or “upstream” neurons each connecting to 10 outputs or “downstream” neurons, for a total of 100 receivers. Fabricated on a silicon wafer, the waveguides are made of silicon nitride and are each 800 nanometers (nm) wide and 400 nm thick. Researchers created software to automatically generate signal routing, with adjustable levels of connectivity between the neurons.

Laser light was directed into the chip through an optical fiber. The goal was to route each input to every output group, following a selected distribution pattern for light intensity or power. Power levels represent the pattern and degree of connectivity in the circuit. The authors demonstrated two schemes for controlling output intensity: uniform (each output receives the same power) and a “bell curve” distribution (in which middle neurons receive the most power, while peripheral neurons receive less).

To evaluate the results, researchers made images of the output signals. All signals were focused through a microscope lens onto a semiconductor sensor and processed into image frames. This method allows many devices to be analyzed at the same time with high precision. The output was highly uniform, with low error rates, confirming precise power distribution.

“We’ve really done two things here,” Chiles said. “We’ve begun to use the third dimension to enable more optical connectivity, and we’ve developed a new measurement technique to rapidly characterize many devices in a photonic system. Both advances are crucial as we begin to scale up to massive optoelectronic neural systems.”

Park Systems announced the opening of the Park Nanoscience Lab at the prestigious Indian Institute of Science (IISC) Bangalore India, which has been upgraded to the status of Institute of Eminence.

The Nanoscience Lab will be equipped with Park NX20 AFM at the Centre for Nano Science and Engineering (CeNSE) and will hold workshops and symposiums on the latest advancements in nanometrology and offer researchers a chance to experience the latest in AFM technology.

The official inauguration ceremony of the Park Nanoscience Lab in India will be held on Wednesday July 25, 2018 at 10 AM featuring a talk by Dr. San Joon Cho of Park Systems Corporation,who will make an official presentation, declaring the Park NanoScience Lab, a national facility where researchers will have access to Park Systems cutting-edge Atomic Force Microscopes with high resolution nanoscale imaging.The event will also include an AFM live demonstration and is open to the press and public. To register to attend go to: http://www.parksystems.com/iisc

“We are honored to have the Park Nanoscience Lab here at Indian Institute of Science,” The Director, CeNSE- Indian Institute of Science further added, “The partnership with Park Systems and their Atomic Force Microscope technology strengthens our academic and scientific community by bringing an exciting new research tool to a shared access location, supporting the growing demand for nanotechnology here in India.”

The Park Nanoscience Labwill showcase advanced atomic force microscopy systems, demonstrate a wide variety of applications ranging from materials, to chemical and biological to semiconductor and devices, and provide hands on experience, training and service, year-round.

“Increasingly, AFM is being selected for Nanotechnology research over other metrology techniques due to its non-destructive measurement and sub-nanometer accuracy,” states Dr. Sang-il Park, Park Systems Chairman and CEO. “The new Park Nanoscience Lab at Indian Institute is a tremendous step forward for researchers in India who work in the advancing fields of nano science and technology.”

Park Systems advanced AFM platform includes SmartScan, an innovative and pioneering AFM intelligence that produces high quality imaging with very few clicks. Park SmartScan’s unique design opens up the power of AFM to everyone and drastically boosts the productivity of all users.

Since going public and listing on KOSDAQ in 2016, Park Systems’ stock has quadrupled as they continue to lead the world in growing AFM market share. Park Systems, a global AFM manufacturer, has Nanoscience Centers in key cities world-wide including Santa Clara, CA, Albany NY, Tokyo, Japan, Singapore, Heidelberg, Germany, Suwon and Seoul.

A new manufacturing technique uses a process similar to newspaper printing to form smoother and more flexible metals for making ultrafast electronic devices.

The low-cost process, developed by Purdue University researchers, combines tools already used in industry for manufacturing metals on a large scale, but uses the speed and precision of roll-to-roll newspaper printing to remove a couple of fabrication barriers in making electronics faster than they are today.

Roll-to-roll laser-induced superplasticity, a new fabrication method, prints metals at the nanoscale needed for making electronic devices ultrafast. Credit: Purdue University image/Ramses Martinez

Cellphones, laptops, tablets, and many other electronics rely on their internal metallic circuits to process information at high speed. Current metal fabrication techniques tend to make these circuits by getting a thin rain of liquid metal drops to pass through a stencil mask in the shape of a circuit, kind of like spraying graffiti on walls.

“Unfortunately, this fabrication technique generates metallic circuits with rough surfaces, causing our electronic devices to heat up and drain their batteries faster,” said Ramses Martinez, assistant professor of industrial engineering and biomedical engineering.

Future ultrafast devices also will require much smaller metal components, which calls for a higher resolution to make them at these nanoscale sizes.

“Forming metals with increasingly smaller shapes requires molds with higher and higher definition, until you reach the nanoscale size,” Martinez said. “Adding the latest advances in nanotechnology requires us to pattern metals in sizes that are even smaller than the grains they are made of. It’s like making a sand castle smaller than a grain of sand.”

This so-called “formability limit” hampers the ability to manufacture materials with nanoscale resolution at high speed.

Purdue researchers have addressed both of these issues – roughness and low resolution – with a new large-scale fabrication method that enables the forming of smooth metallic circuits at the nanoscale using conventional carbon dioxide lasers, which are already common for industrial cutting and engraving.

“Printing tiny metal components like newspapers makes them much smoother. This allows an electric current to travel better with less risk of overheating,” Martinez said.

The fabrication method, called roll-to-roll laser-induced superplasticity, uses a rolling stamp like the ones used to print newspapers at high speed. The technique can induce, for a brief period of time, “superelastic” behavior to different metals by applying high-energy laser shots, which enables the metal to flow into the nanoscale features of the rolling stamp – circumventing the formability limit.

“In the future, the roll-to-roll fabrication of devices using our technique could enable the creation of touch screens covered with nanostructures capable of interacting with light and generating 3D images, as well as the cost-effective fabrication of more sensitive biosensors,” Martinez said.

By Yoichiro Ando

The Japan semiconductor manufacturing supply chain is a global semiconductor industry workhorse, producing about one third of world’s chip equipment and more than half of its semiconductor materials. In contributing the vast majority of these products, SEMI Japan member companies hold the high distinction of enabling continuous development of the worldwide semiconductor industry. Aptly, then, technology powerhouses IBM, Nissan Motors and Toshiba offered insights into the latest trends and innovations in computing and smart cars at the late-May SEMI Japan Members Days in Tokyo with 133 technologists from member companies in attendance.

As the audience discovered, chip innovation never sleeps and, as futuristic as it can be, invariably gives rise to possibilities beyond the human imagination. That was the message of kickoff presentation “Computing Reimagined – AI/Quantum/IoT” – by Dr. Shintaro Yamamichi, Senior Manager, Science & Technology at IBM Research-Tokyo. Dr. Yamamichi cited three examples of how semiconductors uncover new technology frontiers.

  • Computational materials discovery, a novel methodology, is the application of theory and computation to unearthing new materials and the key to enabling an ongoing stream of semiconductor innovation. In particular, using cognitive technology to mine huge volumes of literature reveal new insights into materials that uncover even more functionality such as greater conductivity and heat resistance. With new materials the oxygen of ever more advanced semiconductor chip manufacturing, the semiconductor industry will surely benefit from this methodology.
  • The opportunity to accelerate quantum computing innovation is now. Launched in May 2016, the IBM Quantum Experience gives students, researchers and general science enthusiasts hands-on access to IBM’s experimental cloud-enabled quantum computing platform. The online platform features a forum for discussing quantum computing topics, tutorials on how to program IBM Q devices, and other educational material about quantum computing. Dr. Yamamichi encouraged the audience to join the program.
  • The world’s tiniest computer, unveiled by IBM at the company’s Think 2018 conference in Las Vegas, packs several hundred thousand transistors and, IBM claims, the equivalent power of a 1990s x86 chip into a package smaller than a grain of salt. The computer’s small form factor (less than 1mm x 1mm) and low manufacturing cost means it can be embedded in product price tags and packages as an anti-fraud device using blockchain technology.

Vehicles need to be both electric and intelligent as countries become more populous and traffic density increases. More drivers extend average drive time, boost greenhouse emissions, devour precious energy resources and lead to more traffic congestion and accidents. Dr. Haruyoshi Kumura, fellow at Nissan Motor, highlighted these issues in stressing the importance of a new era of intelligent mobility. To mitigate these problems, Nissan is focusing on the electrification and intelligence of its vehicles:

  • Nissan’s electric vehicle, Leaf, reduces accidents with electric intelligence systems such as e-Pedal, which uses an accelerator pedal only for both acceleration and deceleration, and ProPILOT Park, a feature that automatically parks the car by using multiple cameras and ultrasonic sonars to detect pedestrians and other objects around the vehicle.

  • With more than 90 percent of traffic accidents caused by driver error, Nissan plans to introduce autonomous driving on multi-lane highways by the end of 2018 and on city streets by 2020. By 2022, the company plans to roll out full autonomous driving to reduce traffic accidents caused by inattentive drivers.
  • For full autonomous driving to materialize, sensor fusion technology must incorporate a combination of technologies – radar systems, light detection and ranging (LiDAR) systems and cameras – to identify the shapes and locations of nearby moving objects and measure their speed. Sensed information is then processed by a 3D graphic analyzer to make electric throttle, braking and steering decisions.

The outlook for automotive industry includes car sharing and more electrification – both insights from Yoshiki Hayakashi, general manager, automotive solution strategic planning division at Toshiba Electronic Devices & Storage, who offered his perspectives on trends in Japan’s automotive industry and beyond.

  • To meet the requirements of the COP21 Paris agreement, the global automotive industry is shifting to electrification. Toshiba estimates 60 percent of new cars will be electric vehicles by 2040 to meet the International Energy Agency’s global EV outlook.
  • In Japan, autonomous driving or advanced driver assistance systems (ADAS) will be offered in certain areas by 2020, the year of the Tokyo Olympic games. Growth of these advanced driving systems hinges on infrastructure development. Supporting data centers, intelligent transport systems, vehicle-to-everything connections, and smart city are all necessary components.
  • Car ownership will begin to cede ground to car sharing with technology elites such as Tesla, Apple and Google leading the way. To expand the car-sharing industry, new alliances will take shape between new and old-guard automotive companies and electronics manufacturing services (EMS) providers.
  • Autonomous driving requires precise 3D renderings of actual roadways using sensors for route mapping. While sensor fusion must be deployed for these capabilities, LiDAR offers better sensing range and space resolution precision than ultrasonic sonars, radars, and cameras.

The next SEMI Japan members day is scheduled for October 30 in Tokyo. SEMI holds similar events in most regions where SEMI and its members operate. For the members events in your region, contact the SEMI office nearest you.

Yoichiro Ando is a marketing director in SEMI Japan.

Originally published on the SEMI blog.

Silicon Labs (NASDAQ: SLAB), a provider of silicon, software and solutions for a smarter, more connected world, announces two new executive appointments. Daniel Cooley has been named Senior Vice President and Chief Strategy Officer. In this new role, Mr. Cooley will focus on Silicon Labs’ overall growth strategy, business development, new technologies and emerging markets. Matt Johnson, a semiconductor veteran with more than 15 years of industry experience, joins Silicon Labs as Senior Vice President and General Manager of IoT products. Both executives will report to Tyson Tuttle, CEO.

Mr. Cooley has led Silicon Labs’ IoT business for the past four years. Under his leadership, the company built an industry-leading portfolio of secure connectivity solutions, with IoT revenue now exceeding a $100 million per quarter run rate. Mr. Cooley joined Silicon Labs in 2005 as a chip design engineer developing broadcast audio products and short-range wireless devices. Over the years, he has served in various senior management, engineering and product management roles at the company’s Shenzhen, Singapore, Oslo and Austin sites. The new role leverages Mr. Cooley’s proven talents in strategy and business development.

Mr. Johnson will lead Silicon Labs’ IoT business including the development and market success of the company’s broad portfolio of wireless products, microcontrollers, sensors, development tools and wireless software. Mr. Johnson has a track record of growing revenue and leading large global teams, and he brings a deep understanding of analog, MCU and embedded software businesses to Silicon Labs. Previously, he served as Senior Vice President and General Manager of automotive processing products and software development at NXP Semiconductors/Freescale, as well as SVP and General Manager of mobile solutions at Fairchild Semiconductor.

“With these executive appointments, we are expanding our ability to execute on large and growing market opportunities in the IoT,” said Tyson Tuttle, CEO of Silicon Labs. “Together, these two talented leaders will help Silicon Labs scale the business to the next level and focus on future growth.”