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The 2018 Symposia on VLSI Technology & Circuits will deliver a unique perspective into the technological ecosystem of converging industry trends – machine learning, IoT, artificial intelligence, wearable/implantable biomedical applications, big data, and cloud computing – the emerging technologies needed for ‘smart living.’ In a weeklong conference packed with technical presentations, a demonstration session, panel discussions, focus sessions, short courses, and a new “Friday Forum” on machine learning, the microelectronics industry’s premiere international conference covers technology, circuits, and systems with a range and scope unlike any other conference.

Built around the theme of “Technology, Circuits & Systems for Smart Living,” the Symposia programintegrates advanced technology developments, innovative circuit design, and the applications that they enable as part of our global society’s adoption of smart, connected devices and systems that change the way humans interact with each other.

Plenary Sessions (June 19):
The Symposia will open with two technology plenary sessions, including “Memory Technology: The Core to Enable Future Computing Systems” by Scott DeBoer, executive VP for technology development, Micron; and “Revolutionizing Cancer Genomic Medicine by Artificial Intelligence & Supercomputing with Big Data” by Satoru Miyano, director of the Human Genome Center, Institute of Medical Science at University of Tokyo.

The following Circuits plenary sessions include “Hardware-Enabled Artificial Intelligence” by Dr. Bill Dally, chief scientist & senior VP, Nvidia; and “Semiconductor Technologies Accelerate Our Future Vision: ‘ANSHIN Platform'” by Tsuneo Komatsuzaki, advisor, SECOM.

Focus Sessions (June 19, 20 & 21):
As part of the Symposia’s ongoing program integration, a series of joint focus sessions will be held to present contributed papers from the Technology and Circuits Symposia on June 20 and 21. Topics will include: “Heterogeneous System Integration,” “Power Devices & Circuits,” “New Devices & Systems for AI,” and “Design & Technology Co-Optimization (DTCO) in Advanced CMOS Technology.”

On June 19, the Technology focus sessions will include: “Back-End Compatible Devices & Advanced Thermal Management“ and “Sensors and Devices for IoT, Medicine, & Smart Living.” The Circuits focus sessions, held on June 21, include “Machine Learning Circuits & SoCs,” and “Advanced Wireline Techniques.”

Evening Panel Sessions (June 18 & 19):
A joint panel discussion, bringing together leading experts from Technology & Circuits programs will be held June 18 to answer the question, “Is the CPU Dying or Dead? Are Accelerators the Future of Computation?”

As Moore’s Law slows down and processor architecture innovations move away from single thread performance, the future of computing seems to be moving away from the general purpose CPU. Is the era of the CPU over? Will future CPUs simply coordinate activity among accelerators and other specialized processing units? The panel will examine future computing workloads as well as the innovative technology and circuit solutions that enable them, from moving computation closer to memory, and developing bio-inspired systems.

The Technology evening panel session panel discussion, held on June 19 will examine “Storage Class Memories: Who Cares? DRAM is Scaling Fine, NAND Stacking is Great.” Memory – DRAM and NAND scaling – though difficult, has persisted due to rapid innovations and continued engineering. Although there are new economic and fundamental challenges posed to continued memory scaling, a new class of memories – Storage Class memories, appears to bridge the latency gap that exists in the memory hierarchy and promises to improve system performance. Now the real question becomes – who really cares now? System architects, DRAM/NAND manufacturers? End users? The panel will discuss the challenges and opportunities of storage class memories in the environment where DRAM and NAND scaling continue.

The question to be addressed by the Circuits evening panel session, also held on June 19, is “What’s The Next Big Thing After Smartphones?” Although smartphones have driven the industry for more than a decade, the pace of innovation is slowing, and market saturation is occurring. What will be the next big thing? The Internet of Things? Automotive electronics? Virtual reality? Something else? A set of panelists with diverse expertise will discuss the possibilities.

Thursday Luncheon (June 21):
Continuing the Symposia’s tradition of thought-provoking presentations centered around the conference theme is the Thursday luncheon talk, entitled “The Hardware of The Mind, from Turing to Today,” by Grady Booch, chief scientist for software engineering at IBM Research. As scientists continue to the computing power of the human mind, they strive to bridge the gap between the physicality of silicon and the exquisite wonder of the brain. This presentation examines the journey of the hardware of the mind – from the Iliad, to da Vinci, to Edison, to Turing, to today – including an examination of how the growing understanding of the brain transforms the engineering of silicon, and how the laws of physics as well as the laws of humanity constrain that journey.

Full Day Short Courses (June 18):
The Technology Short Course – “Device & Integration Technologies for Sub-5nm CMOS & the Next Wave of Computing” will cover a range of topics, including CMOS technology beyond the 5nm node, MOL/BEOL interconnects, atomic-level analysis for FinFET & Nanowire design, 3D integration for image sensors, neuromorphic AI hardware, memory technologies for AI/machine learning, and sensors & analog devices for next generation computing.

The first Circuits Short Course – “Designing for the Next Wave of Cloud Computing” will address advanced computer architectures, GPU applications and FPGA acceleration, the evolution of memory and in-memory computation, and advanced packaging, power delivery and cooling for cloud computing, as well as the impact of quantum computing.

The second Circuits Short Course – “Bio-Sensors, Circuits & Systems for Wearable & Implantable Medical Devices” will cover circuits and systems for mobile healthcare, analog front-ends for bio-sensors, digital phenotyping using wearable sensors, bi-directional neural interfacing, body-area networking and body-coupled communications, ultrasound-on-a-chip, as well as a CMOS-based implantable retinal prosthesis.

Demonstration Session (June 18):
Following a successful launch last year in Kyoto, the popular demonstration session will again be part of the Symposia program, providing participants an opportunity for in-depth interaction with authors of selected papers from both Technology and Circuits sessions. These demonstrations will illustrate technological concepts and analyses through table-top presentations that show device characterization, chip operational results, and potential applications for circuit-level innovations.

Friday Forum (June 22):
New to the Symposia program this year will be the Friday Forum – a full-day series of presentations focusing on how technology and circuit designers engage in and drive the future of AI/machine learning systems, a subject area that continues to evolve as an impactful driver of the integrated systems that are part of the Symposia’s “Smart Living” theme. “Machine Learning Today & Tomorrow: A Technology, Circuits & Systems View” will provide the foundations and performance metrics for machine learning systems, an examination of advanced and emerging circuit architectures for next-generation systems, as well as highlighting tools and datasets for benchmarking and evaluating service-oriented architecture (SoA) machine learning systems.

The annual Symposium on VLSI Technology & Circuits will be held at the Hilton Hawaiian Village in Honolulu, Hawaii from June 18-22, 2018, with Short Courses held on June 18 and a special Friday Forum dedicated to machine learning/AI topics on June 22. The two conferences have been held together since 1987, providing an opportunity for the world’s top device technologists, circuit and system designers to exchange leading edge research on microelectronics technology, with alternating venues between Hawaii and Japan. A single registration enables participants to attend both Symposia.

By Jay Chittooran, SEMI Public Policy

Following through on his 2016 campaign promise, President Trump is implementing trade policies that buck conventional wisdom in Washington, D.C. and among U.S. businesses. Stiff tariffs and the dismantling of longstanding trade agreements – cornerstones of these new actions – will ripple through the semiconductor industry with particularly damaging effect. China, a chief target of criticism from President Trump, has again found itself in the crosshairs of the administration, with trade tensions rising to a fever pitch.

The Trump Administration has long criticized China for what it considers unfair trade practices, often zeroing in on intellectual property. In August 2017, the Office of the U.S. Trade Representative (USTR), charged with developing and recommending U.S trade policy to the president, launched a Section 301 investigation into whether China’s practice of forced technology transfer has discriminated against U.S. firms. As the probe continues, it is becoming increasingly clear that the United States will impose tariffs on China based on its current findings. Reports suggest that the tariffs could come soon, hitting a range of products from consumer electronics to toys. Other measures could include tightening restrictions on the trade of dual-use goods – those with both commercial and military applications – curbing Chinese investment in the United States, and imposing strict limits on the number of visas issued to Chinese citizens.

With China a major and intensifying force in the semiconductor supply chain, raising tariffs hangs like the Sword of Damocles over the U.S. and global economies. A tariff-ignited trade war with China could stifle innovation, undermine the long-term health of the semiconductor industry, and lead to unintended consequences such as higher consumer prices, lower productivity, job losses and, on a global scale, a brake on economic growth.

Other recently announced U.S. trade actions could also cloud the future for semiconductor companies. The Trump administration, based on two separate Section 232 investigations claiming that overproduction of both steel and aluminum are a threat to U.S. national security, recently levied a series of tariffs and quotas on every country except Canada and Mexico. While these tariffs have yet to take effect, the mere prospect has angered U.S. trading partners – most notably Korea, the European Union and China. Several countries have threatened retaliatory action and others have taken their case to the World Trade Organization.

Trade is oxygen to the semiconductor industry, which grew by nearly 30 percent last year and is expected to be valued at an estimated $1 trillion by 2030. Make no mistake: SEMI fully supports efforts to buttress intellectual property protections. However, the Trump administration’s unfolding trade policy could antagonize U.S. trade partners.

For its part, SEMI is weighing in with USTR on these issues, underscoring the critical importance of trade to the semiconductor industry as we educate policymakers on trade barriers to industry growth and encourage unobstructed cross-border commerce to advance semiconductors and the emerging technologies they enable. On behalf of our members, we continue our work to increase global market access and lessen the regulatory burden on global trade. If you are interested in more information on trade, or how to be involved in SEMI’s public policy program, please contact Jay Chittooran, Public Policy Manager, at [email protected].

Originally published on the SEMI blog.

GLOBALFOUNDRIES today announced a new ecosystem partner program, called RFWave, designed to simplify RF design and help customers reduce time-to-market for a new era of wireless devices and networks.

The last few years there has been an increasing demand for connected devices and systems that will require innovations in radio technologies to support the new modes of operation and higher capabilities. The RFWave Partner Program builds upon GF’s 5G vision and roadmap, with a focus on the company’s industry-leading radio frequency (RF) solutions, such as FD-SOI, RF CMOS (bulk and advanced CMOS nodes), RF SOI and silicon germanium (SiGe) technologies. The program provides a low-risk, cost-effective path for designers seeking to build highly optimized RF solutions for a range of wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband.

RFWave enables customers to build innovative RF solutions as well as packaging and test solutions. Initial partners have committed a set of key offerings to the program, including:

  • tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage features of GF’s RF technology platforms,
  • a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs using pre-validated IP elements,
  • resources (design consultation, services), trained and globally distributed, for Partners to gain easy access to support in developing solutions using GF’s RF technologies

“An explosion of digital information is expected to drive an enormous amount of growth in the coming years and our customers are already preparing for a future of seamless, reliable ultra high data rate wireless connectivity everywhere,” said Bami Bastani, senior vice president of GF’S RF Business Unit. “As a leader in RF, GF’s RFWave program takes industry collaboration to a new level, enabling our customers to build differentiated, highly integrated RF-tailored solutions that are designed to accelerate the next wave of technology.”

The RFWave Partner Program creates an open framework to allow selected partners to integrate their products or services into a validated, plug-and-play catalog of design solutions. This level of integration allows customers to create high-performance designs while minimizing development costs through access to a broad set of quality offerings, specific to RF technology. The partner ecosystem positions members and customers to take advantage of ubiquitous connectivity and the broad adoption of GF’s industry-leading RF technology platforms.

Initial members of the RFWave Partner Program are: asicNorth, Cadence, CoreHW, CWS, Keysight Technologies, Spectral Design, and WEASIC. These companies have already initiated work to deliver innovative, highly optimized RF solutions.

Imec, a research and innovation hub in nanoelectronics and digital technologies, today presented its annual Lifetime of Innovation Award to Dr. Irwin Jacobs, Founding Chairman and CEO Emeritus of Qualcomm. The annual industry honor is presented to the individual who has significantly advanced the field of semiconductor technology.  The formal presentation will be made at the global Imec Technology Forum (ITF) in May in Belgium.

In making the announcement, Luc Van den hove, president and CEO of imec, said: “Irwin Jacobs’ many technological contributions laid the groundwork for creating the mobile industry and markets that we know today. Under his leadership, Qualcomm developed two-way mobile satellite communications and tracking systems deemed the most advanced in the world. He pioneered spread-spectrum technology and systems using CDMA (code division multiple access), which became a digital standard for cellular phone communications. Together, these technologies opened mobile communications to the global consumer market.”

Irwin Jacobs began his career first as an assistant and then associate professor of electrical engineering at MIT and, later, as professor of computer science and engineering at the University of California in San Diego. While at MIT, he co-authored Principles of Communication Engineering, a textbook still in use. He began his corporate life as a cofounder of Linkabit, which developed satellite encryption devices.  In 1985, he co-founded Qualcomm, serving as CEO until 2005 and chairman through 2009.  His numerous awards include the National Medal of Technology, the Marconi Prize, and the Carnegie Medal of Philanthropy.  His honors include nine honorary degrees including doctor of engineering from the National Tsing Hua University, Taiwan.

Imec initiated the Lifetime of Innovation Award in 2015 at their annual global forum known as ITF (Imec Technology Forum).  The award marks milestones that have transformed the semiconductor industry.  The first recipient was Dr. Morris Chang, whose foundry model launched the fabless semiconductor industry, spurring creation of new innovative companies.  In 2016, Gordon Moore was honored, creator of the famous Moore’s law theory and co-founder of Intel.  Dr. Kinam Kim was honored in 2017 for his contributions in memory technologies and his visionary leadership at Samsung.

Luc Van den hove concluded, saying: “Our mission is to create innovation through collaboration. By gathering global technology leaders at the ITF, imec provides an open forum to share issues and trends challenging the semiconductor industry. In this international exchange, imec and participants outline ways to collaborate in bringing innovative solutions to market.”

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, and IBM (NYSE: IBM) today announced that the companies agreed to sign a license agreement on laser debonding technology. EVG plans to integrate IBM’s patented Hybrid Laser Release process into EVG’s advanced, field-proven temporary bonding and debonding equipment solutions, which can provide high-volume manufacturers with greater flexibility to implement optimized temporary bonding and debonding process flows. Thanks to the added process variants from IBM that will be supported by EVG’s equipment portfolio, customers can choose from a wide range of bonding, cleaning and metrology process options to help address their temporary bonding and debonding requirements and applications.

The result, which is an advanced laser debonding solution based on EVG’s combination of the technology licensed from IBM with EVG’s know-how, encompasses methods and designs for UV and IR laser debonding (designed to enable the use of glass or silicon carriers) as well as inspection of the bond interfaces. The technologies contributed by IBM help EVG implement designs that address the industry’s critical requirements for temporary bonding and debonding, including high throughput, low wafer stress for high yield, and low cost of ownership of the laser equipment, processing and consumables. The advanced EVG solution encompasses techniques to help protect chips from heat and laser damage, as well as chemical clean technologies for device and carrier wafers.

A scientific team led by the Department of Energy’s Oak Ridge National Laboratory has found a new way to take the local temperature of a material from an area about a billionth of a meter wide, or approximately 100,000 times thinner than a human hair.

This discovery, published in Physical Review Letters, promises to improve the understanding of useful yet unusual physical and chemical behaviors that arise in materials and structures at the nanoscale. The ability to take nanoscale temperatures could help advance microelectronic devices, semiconducting materials and other technologies, whose development depends on mapping the atomic-scale vibrations due to heat.

From left, Andrew Lupini and Juan Carlos Idrobo use ORNL's new monochromated, aberration-corrected scanning transmission electron microscope, a Nion HERMES to take the temperatures of materials at the nanoscale. Credit: Oak Ridge National Laboratory, US Dept. of Energy; photographer Jason Richards

From left, Andrew Lupini and Juan Carlos Idrobo use ORNL’s new monochromated, aberration-corrected scanning transmission electron microscope, a Nion HERMES to take the temperatures of materials at the nanoscale. Credit: Oak Ridge National Laboratory, US Dept. of Energy; photographer Jason Richards

The study used a technique called electron energy gain spectroscopy in a newly purchased, specialized instrument that produces images with both high spatial resolution and great spectral detail. The 13-foot-tall instrument, made by Nion Co., is named HERMES, short for High Energy Resolution Monochromated Electron energy-loss spectroscopy-Scanning transmission electron microscope.

Atoms are always shaking. The higher the temperature, the more the atoms shake. Here, the scientists used the new HERMES instrument to measure the temperature of semiconducting hexagonal boron nitride by directly observing the atomic vibrations that correspond to heat in the material. The team included partners from Nion (developer of HERMES) and Protochips (developer of a heating chip used for the experiment).

“What is most important about this ‘thermometer’ that we have developed is that temperature calibration is not needed,” said physicist Juan Carlos Idrobo of the Center for Nanophase Materials Sciences, a DOE Office of Science User Facility at ORNL.

Other thermometers require prior calibration. To make temperature graduation marks on a mercury thermometer, for example, the manufacturer needs to know how much mercury expands as the temperature rises.

“ORNL’s HERMES instead gives a direct measurement of temperature at the nanoscale,” said Andrew Lupini of ORNL’s Materials Science and Technology Division. The experimenter needs only to know the energy and intensity of an atomic vibration in a material–both of which are measured during the experiment.

These two features are depicted as peaks, which are used to calculate a ratio between energy gain and energy loss. “From this we get a temperature,” Lupini explained. “We don’t need to know anything about the material beforehand to measure temperature.”

In 1966, also in Physical Review Letters, H. Boersch, J. Geiger and W. Stickel published a demonstration of electron energy gain spectroscopy, at a larger length scale, and pointed out that the measurement should depend upon the temperature of the sample. Based on that suggestion, the ORNL team hypothesized that it should be possible to measure a nanomaterial’s temperature using an electron microscope with an electron beam that is “monochromated” or filtered to select energies within a narrow range.

To perform electron energy gain and loss spectroscopy experiments, scientists place a sample material in the electron microscope. The microscope’s electron beam goes through the sample, with the majority of electrons barely interacting with the sample. In electron energy loss spectroscopy, the beam loses energy as it passes through the sample, whereas in energy gain spectroscopy, the electrons gain energy from interacting with the sample.

“The new HERMES lets us look at very tiny energy losses and even very small amounts of energy gain by the sample, which are even harder to observe because they are less likely to happen,” Idrobo said. “The key to our experiment is that statistical physical principles tell us that it is more likely to observe energy gain when the sample is heated. That is precisely what allowed us to measure the temperature of the boron nitride. The monochromated electron microscope enables this from nanoscale volumes. The ability to probe such exquisite physical phenomena at these tiny scales is why ORNL purchased the HERMES.”

ORNL scientists are constantly pushing the capabilities of electron microscopes to allow new ways of conducting forefront research. When Nion electron microscope developer Ondrej Krivanek asked Idrobo and Lupini, “Wouldn’t it be fun to try electron energy gain spectroscopy?” they jumped at the chance to be the first to explore this capability of their HERMES instrument.

Nanoscale resolution makes it possible to characterize the local temperature during phase transitions in materials–an impossibility with techniques that do not have the spatial resolution of HERMES spectroscopy. For example, an infrared camera is limited by the wavelength of infrared light to much larger objects.

Whereas in this experiment the scientists tested nanoscale environments at room temperature to about 1300 degrees Celsius (2372 degrees Fahrenheit), the HERMES could be useful for studying devices working across a wide range of temperatures, for example, electronics that operate under ambient conditions to vehicle catalysts that perform over 300 C/600 F.

Micron Technology Inc. (Nasdaq:MU) announced today that the company has appointed Raj Talluri as senior vice president and general manager of the Mobile Business Unit.

In this role, Talluri will be responsible for leading and growing Micron’s mobile business. This includes building world-class mobile solutions to address the growing market opportunity driven by new usage models, from low-end devices to flagship smartphones. Talluri will report to Sumit Sadana, Micron’s executive vice president and chief business officer.

Talluri is a seasoned leader, with 25 years of experience in the semiconductor industry in executive roles spanning business, engineering management and strategic marketing. He joins Micron after nine years at Qualcomm, where he most recently served as senior vice president of product management, responsible for the company’s Internet of Things business and, before that, its mobile computing platform. Before joining Qualcomm, Talluri held executive positions at Texas Instruments, where he worked for sixteen years. His last role was general manager of the cellular media solution business in the wireless terminals business unit.

“Emerging usage models such as artificial intelligence, augmented reality and advanced imaging are increasing the complexity of devices, requiring new ways of processing, sharing and utilizing data, and making memory and storage increasingly critical to the mobile platform,” said Sadana. “Raj’s deep technical expertise and customer relationships in the mobile space, combined with his vision and business experience, make him the ideal choice to lead our mobile business unit.”

Talluri earned a Ph.D. in electrical engineering from the University of Texas in Austin. He also earned a Master of Engineering degree from Anna University in Chennai, India, and a Bachelor of Engineering from Andhra University in Waltair, India. He holds 13 U.S. patents relating to image processing, video compression and media processor architectures.

Scientists at Rice University and the Indian Institute of Science, Bangalore, have discovered a method to make atomically flat gallium that shows promise for nanoscale electronics.

The Rice lab of materials scientist Pulickel Ajayan and colleagues in India created two-dimensional gallenene, a thin film of conductive material that is to gallium what graphene is to carbon.

Extracted into a two-dimensional form, the novel material appears to have an affinity for binding with semiconductors like silicon and could make an efficient metal contact in two-dimensional electronic devices, the researchers said.

The new material was introduced in Science Advances.

Gallium is a metal with a low melting point; unlike graphene and many other 2-D structures, it cannot yet be grown with vapor phase deposition methods. Moreover, gallium also has a tendency to oxidize quickly. And while early samples of graphene were removed from graphite with adhesive tape, the bonds between gallium layers are too strong for such a simple approach.

So the Rice team led by co-authors Vidya Kochat, a former postdoctoral researcher at Rice, and Atanu Samanta, a student at the Indian Institute of Science, used heat instead of force.

Rather than a bottom-up approach, the researchers worked their way down from bulk gallium by heating it to 29.7 degrees Celsius (about 85 degrees Fahrenheit), just below the element’s melting point. That was enough to drip gallium onto a glass slide. As a drop cooled just a bit, the researchers pressed a flat piece of silicon dioxide on top to lift just a few flat layers of gallenene.

They successfully exfoliated gallenene onto other substrates, including gallium nitride, gallium arsenide, silicone and nickel. That allowed them to confirm that particular gallenene-substrate combinations have different electronic properties and to suggest that these properties can be tuned for applications.

“The current work utilizes the weak interfaces of solids and liquids to separate thin 2-D sheets of gallium,” said Chandra Sekhar Tiwary, principal investigator on the project he completed at Rice before becoming an assistant professor at the Indian Institute of Technology in Gandhinagar, India. “The same method can be explored for other metals and compounds with low melting points.”

Gallenene’s plasmonic and other properties are being investigated, according to Ajayan. “Near 2-D metals are difficult to extract, since these are mostly high-strength, nonlayered structures, so gallenene is an exception that could bridge the need for metals in the 2-D world,” he said.

Brown University engineers have devised a new method of measuring the stickiness of micro-scale surfaces. The technique, described in Proceedings of the Royal Society A, could be useful in designing and building micro-electro-mechanical systems (MEMS), devices with microscopic moving parts.

With slight modifications, an atomic force microscope could be used to measure adheasion in micro-materials. Credit: Kesari Lab/Brown University. Credit: Kesari Lab/Brown University

With slight modifications, an atomic force microscope could be used to measure adheasion in micro-materials. Credit: Kesari Lab/Brown University. Credit: Kesari Lab/Brown University

At the scale of bridges or buildings, the most important force that engineered structures need to deal with is gravity. But at the scale of MEMS — devices like the tiny accelerometers used in smartphones and Fitbits — the relative importance of gravity decreases, and adhesive forces become more important.

“The main thing that matters at the microscale is what sticks to what,” said Haneesh Kesari, an assistant professor in Brown’s School of Engineering and coauthor of the new research. “If you have parts of your device sticking together that shouldn’t be, it’s not going to work. So in order to design MEMS devices, it helps to have a good way of measuring adhesion in the materials we use.”

That’s what Kesari and two Brown graduate students, Wenqiang Fang and Joyce Mok, looked to accomplish with this new research. Specifically, they wanted to measure a quantity known as “work of adhesion,” which roughly translates into the amount of energy required to separate a unit area of two adhered surfaces.

The key theoretical insight developed in the new study is that thermal vibrations of a microbeam can be used to calculate work of adhesion. That insight suggests a method in which a slightly modified atomic force microscopy (AFM) system can be used to probe adhesive properties.

Standard AFM works a bit like a record player. A cantilever with a sharp needle moves across a target material. A laser shown on the cantilever measures the tiny undulations it makes as it moves along the material’s contours. Those undulations can then be used to map out the material’s surface properties.

Adapting the method to measure adhesion would require simply removing the metal tip from the cantilever, leaving a flat microbeam. That beam can then be lowered onto a target material, where it will adhere. When the cantilever is raised slightly, some portion of the beam will become unstuck, while the rest remains stuck. The unstuck portion of the beam will vibrate ever so slightly. The authors found a way to use the extent of that vibration, which can be measured by an AFM laser, to calculate the length of the unstuck portion, which can in turn be used to calculate the target material’s work of adhesion.

With slight modifications, an atomic force microscope could be used to measure adheasion in micro-materials. Credit: Kesari Lab/Brown University Fang says the technique could be useful in assessing new material coatings or surface textures aimed at alleviating the failure of MEMS devices through sticking.

“Once you have a robust technique for measuring the material’s work of adhesion, then you have a systematic way of evaluating these methods to get the level of adhesion needed for a particular application,” Fang said. “The main advantage to this method is that you don’t need to change a standard AFM setup very much in order to do this.”

The approach is also much simpler than other techniques, according to Mok.

“Previous methods based on interferometry are labor intensive and may require many data points to be taken,” she said. “Our theoretical framework would give a value for the work of adhesion from a single measurement.”

Having demonstrated the technique numerically, Kesari says the next step is to build the system and start collecting some experimental data. He’s hopeful that such a system will aid in pushing the MEMS field forward.

“We have MEMS accelerometers and gyroscopes, but I don’t think the field has quite lived up to its promise yet,” Kesari said. “Part of the reason for that is that people haven’t completely understood adhesion at the small scale. We think that a more robust way of measuring adhesion is the first step towards gaining such an understanding.”

Each year, Solid State Technology turns to industry leaders to hear viewpoints on the technological and economic outlook for the upcoming year. Read through these expert opinions on what to expect in 2018.

Enabling the AI Era with Materials Engineering

Screen Shot 2018-03-05 at 12.24.49 PMPrabu Raja, Senior Vice President, Semiconductor Products Group, Applied Materials

A broad set of emerging market trends such as IoT, Big Data, Industry 4.0, VR/AR/MR, and autonomous vehicles is accelerating the transformative era of Artificial Intelligence (AI). AI, when employed in the cloud and in the edge, will usher in the age of “Smart Everything” from automobiles, to planes, factories, buildings, and our homes, bringing fundamental changes to the way we live

Semiconductors and semiconductor processing technol- ogies will play a key enabling role in the AI revolution. The increasing need for greater computing perfor- mance to handle Deep Learning/Machine Learning workloads requires new processor architectures beyond traditional CPUs, such as GPUs, FPGAs and TPUs, along with new packaging solutions that employ high-density DRAM for higher memory bandwidth and reduced latency. Edge AI computing will require processors that balance the performance and power equation given their dependency on battery life. The exploding demand for data storage is driving adoption of 3D NAND SSDs in cloud servers with the roadmap for continued storage density increase every year.

In 2018, we will see the volume ramp of 10nm/7nm devices in Logic/Foundry to address the higher performance needs. Interconnect and patterning areas present a myriad of challenges best addressed by new materials and materials engineering technologies. In Inter- connect, cobalt is being used as a copper replacement metal in the lower level wiring layers to address the ever growing resistance problem. The introduction of Cobalt constitutes the biggest material change in the back-end-of-line in the past 15 years. In addition to its role as the conductor metal, cobalt serves two other critical functions – as a metal capping film for electro- migration control and as a seed layer for enhancing gapfill inside the narrow vias and trenches.

In patterning, spacer-based double patterning and quad patterning approaches are enabling the continued shrink of device features. These schemes require advanced precision deposition and etch technologies for reduced variability and greater pattern fidelity. Besides conventional Etch, new selective materials removal technologies are being increasingly adopted for their unique capabilities to deliver damage- and residue-free extreme selective processing. New e-beam inspection and metrology capabilities are also needed to analyze the fine pitch patterned structures. Looking ahead to the 5nm and 3nm nodes, placement or layer-to-layer vertical alignment of features will become a major industry challenge that can be primarily solved through materials engineering and self-aligned structures. EUV lithography is on the horizon for industry adoption in 2019 and beyond, and we expect 20 percent of layers to make the migration to EUV while the remaining 80 percent will use spacer multi- patterning approaches. EUV patterning also requires new materials in hardmasks/underlayer films and new etch solutions for line-edge-roughness problems.

Packaging is a key enabler for AI performance and is poised for strong growth in the coming years. Stacking DRAM chips together in a 3D TSV scheme helps bring High Bandwidth Memory (HBM) to market; these chips are further packaged with the GPU in a 2.5D interposer design to bring compute and memory together for a big increase in performance.

In 2018, we expect DRAM chipmakers to continue their device scaling to the 1Xnm node for volume production. We also see adoption of higher perfor- mance logic technologies on the horizon for the periphery transistors to enable advanced perfor- mance at lower power.

3D NAND manufacturers continue to pursue multiple approaches for vertical scaling, including more pairs, multi-tiers or new schemes such as CMOS under array for increased storage density. The industry migration from 64 pairs to 96 pairs is expected in 2018. Etch (high aspect ratio), dielectric films (for gate stacks and hardmasks) along with integrated etch and CVD solutions (for high aspect ratio processing) will be critical enabling technologies.

In summary, we see incredible inflections in new processor architectures, next-generation devices, and packaging schemes to enable the AI era. New materials and materials engineering solutions are at the very heart of it and will play a critical role across all device segments.

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