Category Archives: Materials and Equipment

September 2, 2009: A new Microelectronics Innovation Center is being formed at the Université de Sherbrooke in Bromont, Québec, to focus on 200mm microelectromechanical systems (MEMS) and 3D wafer-level packaging (WLP), and “advanced technologies associated with the assembly and packaging of silicon chips.”

Initial investments come from the governments of Québec ($94.95M) and Canada ($82.95M), and another $40.6M from center cofounders DALSA, IBM Canada, and the U. of Sherbrooke along with unidentified semiconductor equipment suppliers. Participatory interest also has been expressed by other universities, research centers, and industrial partners both in Canada and globally, they note.

The group’s stated “prime purpose” is to “leverage the best from the Canadian and international research community to address industry’s most challenging problems,” with end goals of both technology transfer and spinoffs. It also will be the centerpiece of a planned “true microelectronics cluster in Québec” hoped to extend from activities centered around Albany, NY. An estimated 250 researchers will be involved, and >3000 jobs will be created.

“The project marks the birth of a value chain that could eventually match the Québec economy’s flagship innovation sectors — life sciences, aerospace, and computer technologies,” said Clément Gignac., Minister of Economic Development, Innovation and Export Trade, in a statement.

Debbie Forray and Ilya Furman, Henkel Corp., compare a self-filleting die attach paste to film-based adhesives.

Strong consumer demand for increased stored content on cell phones, MP3 players, and digital cameras continues to drive the memory market to higher production volumes. This is an intensely competitive marketplace that pushed selling prices lower in 2007 vs. 2006 and even lower still in late 2008 and early 2009.

In light of these market developments, semiconductor companies are seeking lower-cost die attach material solutions to replace the higher-cost, film-based adhesive materials used for certain applications. One such material is self-filleting die attach paste. 

Read the full article "Self-filleting technology using smart die-attach paste"

Kwan-yu Lai, Micralyne, and Jeffrey G. Stark, Sensor Products, describe the use of color-coded pressure-indicating film to ensure uniform, correct pressure during wafer bonding. Wafers are bonded by applying precise combinations of physical pressure, temperature, and/or voltage. Pressure is measured as an average, assuming perfectly flat pressure plates. In practice, the pressure plates are often non-ideal, or they may have degraded over time. Applied pressure characterization is important for high yielding eutectic/thermocompression bonds.

Bond recipes are tested for consistency then adjusted based on the results from the pressure-indicating film. There are also specific benefits that are distinct to each type of bonding application: metal eutectic bonding, anodic bonding, fusion bonding, metal diffusion bonding, glass frit bonding, polymer adhesive bonding.

Read the full article, “Pressure indicating film characterization of wafer-to-wafer bonding”

Non-silicone Thermal Grease


August 28, 2009

Fujipoly America released two non-silicone thermally conductive grease compounds. The polysynthetic-based thermal interface material (TIM) suits thin bond line applications that are also adverse to silicone contamination.

The low-bleed, low-resistance grease is infused with heat-conductive metal oxides to deliver thermal conductivity from 0.75 to 2.60 W/m&#176K. Sarcon non-silicone greases offer low evaporation characteristics and are engineered to deliver consistent performance across temperatures from -55&#176 to +205&#176C.

Multiple packaging options include pre-filled 3cc (6g), 10cc (28g), and 30cc (72g) syringes and 1 lb. (454g) jars for stencil deposition and automated application.

Fujipoly America Corporation, a wholly owned subsidiary of Fuji Polymer Industries Co. Ltd. of Japan, Carteret, NJ; (732) 969-0100; www.fujipoly.com.

Extending its capabilities for placing solder spheres at high speed, DEK’s proven DirEKt Ball Placement process now enables accurate solder sphere deposition for spheres as small as 200µm in diameter with pitches as tight as 300µm. With the ability to achieve this accuracy and precision at a first pass yield of over 99.99%, DirEKt Ball Placement delivers the speeds necessary for modern package manufacture without sacrificing anything in the way of performance.

Unlike alternative methods that employ serial approaches for placement of solder balls, the parallel print process of DirEKt Ball Placement allows for unmatched, repeatable accuracy and exceptionally fast cycle times which are completely independent of I/O count. While these statistics are arguably impressive and consistent with requirements for next-generation wafer-level CSP devices, DEK is also upholding its pledge to continuously enhance DirEKt Ball Placement capability.

As part of this commitment, the mass imaging leader has designed the Galaxy Thin Wafer System, a high-accuracy print platform capable of meeting the demands of thinned wafer processes and precision microsphere ball placement. The system’s newly engineered wafer pallet, which is flat to less than 10µm with the ability to accommodate wafers as large as 300mm and as thin as 75µm, is the foundation for advancing sphere placement processes to the next-generation.

"While we have achieved 99.99% repeatable first pass yield with 200µm balls at 300µm pitch in high-volume production, even more highly miniaturized spheres have been successfully placed in a lab environment, with work ongoing to prove the process in the field," says DEK’s Semicon and Alternative Applications Manager, David Foggie. "Our active development program to deliver sub-100µm microsphere placement is well underway, with early results delivering an exceptionally high first-pass yield"

The DirEKt Ball Placement system utilizes two side-by-side print platforms, with the first system using flux imaging technology to precisely deposit flux at each interconnect site. The second printer, a Galaxy Thin Wafer System equipped with an advanced enclosed sphere transfer head capable of holding up to 100 million solder balls, then accurately seats each ball into the flux. Enabled by the enhanced stability and security of the Galaxy Thin Wafer System, DEK’s DirEKt Ball Placement technology can process as many as 45 wafers per hour.

"High UPH microsphere placement is clearly the cost-effective way forward for wafer-level CSP manufacture," concludes Foggie. "DEK’s DirEKt Ball Placement system delivers the precision, repeatability, platform flexibility and low cost of ownership commitment necessary for advancement of this critical packaging technology."

August 25, 2009: The Nanoscale Science and Engineering Research Center for High-rate Nanomanufacturing, a joint venture pooling efforts from Northeastern, U. of Massachusetts/Lowell, and U. of New Hampshire, has received a five-year, $12.25M renewal grant from the National Science Foundation to continue its work with commercializing nanoscale scientific process.

Work going on at the center, centered at Northeastern in Boston, MA, runs the gamut from nanobiosensors for cancer detection to flexible solar cells to nanodrug-delivery systems to batteries to flexible electronics. It also investigates the environmental, economic, regulatory, social, and ethical impacts of nanomanufacturing.

In a statement, the center cited projections from the NSF of a $1 trillion market for nanotech products by 2015 — and that getting there will require perfecting mass-production techniques of nanostructures. “The collaborative research partnership between the Center and industry is accelerating the development of nanotechnology-based products that can impact a number of industries, including healthcare and energy,” stated Ahmed Busnaina, director of the Center and prof. of mechanical and industrial engineering at Northeastern. “Our research is developing more cost-effective, safe, and highly reliable processes that can be scaled up for large-scale manufacturing.”

Established in 2004, the Center now has more than 160 researchers and staff members working on developing nanoscale processes and applications. Leadership includes deputy director Joey Mead, prof. of plastics engineering at UMass Lowell; associate director Glen Miller, prof. of chemistry and director of UNH’s materials science program; associate director Carol Barry, prof. of plastics engineering at UMass Lowell; associate director Jackie Isaacs, prof. of mechanical engineering at Northeastern; and associate director Nick McGruer, prof. of electrical and computer engineering at Northeastern.

August 24, 2009: Carbon nanotube developer Surrey NanoSystems says it has secured a second round of funding totaling £2.5M (US $4.2M) to help commercialize its low-temperature growth process for carbon nanotubes, targeted for use as a replacement for copper interconnects in semiconductor devices.

Investors participating in this round include Octopus Ventures (£1.75M/$3.0M), with the rest coming from Surrey’s initial venture capital investor IP Group and the U. of Surrey, as well as other investors. The company was spun out of U. Surrey’s Advanced Technology Institute in 2006.

Typical CNT growth requires ~700°C deposition temperatures, but the company says it has developed a fabrication system and process enabling ~350°C temperatures, usable in silicon-based semiconductor manufacturing processes. “If you can solve the problem of growing precision carbon nanotubes at silicon-friendly temperatures — and we have — it opens up a massive potential market,” says Ben Jensen, CTO of Surrey NanoSystems, in a statement. “We expect to be the company that is able to offer a viable new interconnection process for high-volume semiconductor fabrication.”

After an initial focus of providing equipment to developers researching and prototyping CNTs, the firm will use the new funding to scale its hardware and optimize the materials process technology from its current 100mm wafer-size capabilities to a mass-production friendly 300mm wafer-size. A SEMI interface also will be added to the equipment for integration into wafer-processing cluster tools. The firm says it also is “pursuing technology partnerships” with both chipmakers and cluster tool suppliers.

The new funding will be used to scale the company’s materials growth technology from its current 100 mm wafer size capability, to the 300 mm sizes used in commercial wafer fabrication plants. Surrey NanoSystems will also add an industry-standard SEMI interface to its process equipment, allowing it to be integrated easily onto standard wafer-processing cluster tools. Alongside this development work, Surrey NanoSystems is pursuing technology partnerships with both semiconductor manufacturers and volume cluster tool suppliers, to shorten the path to market for its technology.

August 24, 2009 — SVTC Technologies was chosen by technology startup siXis, Inc. to supply silicon manufacturing services for their compact, high-speed embedded computing modules that bridge the gap between programmable devices and costly, customized semiconductors.

The siXis modules utilize a unique silicon circuit board (SiCB) architecture using flip-chip bare die and through-silicon vias. This next-generation technology enables siXis to provide smaller, lighter, and lower power embedded computing modules for use in various markets including communications, medical imaging, test and measurement, high-performance computing, and defense and aerospace, as well as advanced semiconductor packaging.

“We needed a fab that could do both process development and provide a bridge to high-volume production,” said John Goehrke, founder and CEO. “SVTC distinguished themselves with their responsiveness, technical capabilities and business processes. They clearly understand our needs, and we’re looking forward to a very successful relationship.”

Joe Bronson, CEO of SVTC Technologies said, “We’re pleased to be working with siXis to help commercialize their remarkable technology. Startup companies such as siXis can depend on SVTC to develop and commercialize their unique products quickly in an open-access, IP-secure environment.”

David Blaker, siXis Vice President of Engineering, said the company’s embedded computing modules allow manufacturers to avoid building expensive application-specific integrated circuits (ASICs) for improved functionality.

“There’s a gap between programmable devices and ASICs, and we offer the opportunity to extend those programmable devices into higher-end systems,” Blaker said. “You can build a cutting-edge device with higher integration for one tenth the cost of an ASIC.”

Blaker added that siXis’ modules are lighter, more compact, and use less energy than traditional computing modules, filling an increasing market demand for reduced size, weight, and power (SWaP). The modules also enable faster memory processing, which lags the speed of logic devices. “Memory bandwidth is a real pain point in the marketplace, and we offer a cost-effective solution,” he said.

August 24, 2009 — SVTC Technologies was chosen by technology startup siXis, Inc. to supply silicon manufacturing services for their compact, high-speed embedded computing modules that bridge the gap between programmable devices and costly, customized semiconductors.

The siXis modules utilize a unique silicon circuit board (SiCB) architecture using flip-chip bare die and through-silicon vias. This next-generation technology enables siXis to provide smaller, lighter, and lower power embedded computing modules for use in various markets including communications, medical imaging, test and measurement, high-performance computing, and defense and aerospace, as well as advanced semiconductor packaging.

“We needed a fab that could do both process development and provide a bridge to high-volume production,” said John Goehrke, founder and CEO. “SVTC distinguished themselves with their responsiveness, technical capabilities and business processes. They clearly understand our needs, and we’re looking forward to a very successful relationship.”

Joe Bronson, CEO of SVTC Technologies said, “We’re pleased to be working with siXis to help commercialize their remarkable technology. Startup companies such as siXis can depend on SVTC to develop and commercialize their unique products quickly in an open-access, IP-secure environment.”

David Blaker, siXis Vice President of Engineering, said the company’s embedded computing modules allow manufacturers to avoid building expensive application-specific integrated circuits (ASICs) for improved functionality.

“There’s a gap between programmable devices and ASICs, and we offer the opportunity to extend those programmable devices into higher-end systems,” Blaker said. “You can build a cutting-edge device with higher integration for one tenth the cost of an ASIC.”

Blaker added that siXis’ modules are lighter, more compact, and use less energy than traditional computing modules, filling an increasing market demand for reduced size, weight, and power (SWaP). The modules also enable faster memory processing, which lags the speed of logic devices. “Memory bandwidth is a real pain point in the marketplace, and we offer a cost-effective solution,” he said.

August 19, 2009 – The good news: semiconductor equipment sales, and especially orders, soared in July to re-achieve parity for the first time in two and a half years. The bad news: the balanced levels are still a third of what they were then.

North American equipment bookings (a three-month average) came in at $569.7B, a 62% spike from the prior month and more than double where they started the year. Tool sales rose 22.1% M/M to $538.0B. Both are by far the best growth numbers seen in a long time, though Y/Y comparisons are still not pretty (-36% bookings, -50% sales).

Those spikes pushed the book-to-bill ratio (B:B) to 1.06, the first time it’s been above the 1.0 parity mark since Jan. 2007, and its highest since July 2006. That means $106 worth of orders came in for every $100 worth of product billed for the month. But don’t get misled; those previous marks were three times the volume of current levels: ~$1.45B in Jan.2007, and $1.64-$1.74B in Jul.2006.

And there’s the rub with focusing on B:B. While historically it’s been an indicator of future industry performance (≥1.0 indicates more orders than sales, i.e. good demand), they cloud the greater issue of dollar levels being so low. If parity is reestablished at a third of what they were, some question whether a true rebound is realistic, and claim visibility is still too poor to hold much confidence.

Things seem better in Japan, where the B:B has surged well above the 1.0 parity mark for two months in a row, pushing to 1.34 in July on a 23% increase in domestic semiconductor orders to ¥43.79B/US $462M (though down 53% from a year ago), according to the Semiconductor Equipment Association of Japan (SEAJ).