Category Archives: Materials and Equipment

January 23, 2009: After announcing last April a method for growing exceptionally long, straight, numerous and well-aligned carbon cylinders only a few atoms thick, a Duke University-led team of chemists has now modified that process to create exclusively semiconducting versions of these single-walled carbon nanotubes.

The achievement paves the way for manufacturing reliable electronic nanocircuits at the ultra-small billionths of a meter scale, said Jie Liu, Duke’s Jerry G. and Patricia Crawford Hubbard Professor of Chemistry, who headed the effort.

“I think it’s the holy grail for the field,” Liu said. “Every piece is now there, including the control of location, orientation and electronic properties all together. We are positioned to make large numbers of electronic devices such as high-current field-effect transistors and sensors.”

A report on their achievement, co-authored by Liu and a team of collaborators from his Duke laboratory and Peking University in China, was published Jan 20, 2009 in the research journal Nano Letters. Their work was funded by the United States Naval Research Laboratory, the National Science Foundation of China, carbon nanotube manufacturer Unidym Inc., Duke University and the Ministry of Science and Technology of the People’s Republic of China.

Liu has filed for a patent on the method.

January 23, 2009: SiMPore Inc., a company commercializing nanotechnology invented at the University of Rochester, has developed an ultrathin microscope slide that significantly improves high-resolution imaging of nanoscale materials such as proteins, viruses and carbon nanotubes, the company announced in a news release.

This is the first commercial application of a unique nanomembrane initially reported in Nature in 2007, the release said.

These new slides, more commonly called windows for electron microscopy, are made of a proprietary silicon membrane so thin that it is invisible edge-on. The extreme thinness of the windows — less than 50 atoms thick — reduces background interference and improves contrast in images generated with transmission electron microscopes ( TEM ), making individual biological molecules, like proteins or viruses, easier to analyze.

Unlike conventional TEM windows, SiMPore’s also have a pure silicon composition meaning that they can be subjected to intense plasma cleaning to remove contaminants, which further improves image quality.


SiMPore’s slides, or windows, are made of a proprietary silicon membrane so thin that it is invisible edge-on. (Image courtesy of SiMPore Inc.)

TEM windows are effectively used as slides to support samples that will be imaged and analyzed with an electron microscope. Imaging is done by focusing a beam of electrons onto a sample, whereby some electrons transmit through the sample and others are scattered out of the beam. The electrons that emerge from the sample carry structural information about the sample that can be magnified by the lens system of the microscope and used to produce a detailed image of atomic scale features.

While the best light microscopes have magnifications of up to 2,000×, some electron microscopes can magnify objects at millions of times their actual size.

Christopher Striemer, now vice president of membrane development at SiMPore, discovered the membrane technology that underlies the new TEM windows while working with nanocrystalline silicon films for computer chip memory applications. By transforming those films into membranes only 15 nanometers thick, he could more precisely image the intricate crystalline structures of his samples using an electron microscope.

Jan. 19, 2009 – Ahead of keenly anticipated 4Q08 results that will set the stage for how long the industry’s dark winter will be, two analysts are casting their vote for chips and equipment, suggesting the former will touch bottom in 1H09, while the other thinks bad times will persist longer than feared.

“We believe a fundamental bottom will form in 1H09 for chip suppliers, and that customers will replenish component and device inventories sometime this summer,” writes Craig Berger of FBR Research, in a recent report. He sees shipments (and thus sales) declining -16% in 2009, after a -2% decline in 2008, pushed down by a seasonally slow 1H09, but a “snapback” in 3Q will push 2H09 to better than seasonal.

“It is clear that the global recession is negatively impacting unit demand for all types of devices,” he writes, adding that chip content per device will also be pressured by tight-fisted consumers. And lower sales might cause some chip suppliers to try and spark competitive pricing in order to win designs and market share.

Key technologies driving demand include:

– Netbook demand was a primary source of strength in 2008, and we expect netbook demand to remain robust in 2009,” Berger writes. He projects a -2% decline in PC units, but -12% if you take out the netbook segment, which he thinks could quadruple or more to 35-50M units in 2009. He also points to a continued shift to portable PCs, and continued corporate push to distributed computing.

– Handset chips will drop about -5% in 2009 to 1.17B units, following significant consolidation in 2008 (Ericsson/ST-NXP Wireless JV, proposed sales of TI’s and Freescale’s baseband units). Look for “very aggressive pricing” and more consolidation as companies who don’t have key IP such as Bluetooth, GPS, Wi-Fi, mobile TV, video processing, and power management to be “marginalized.”

– Prepare for a proliferation of wireless technologies, especially 3G, as “the world ‘unwires’ itself,” Berger writes.

– Look for even more content to be delivered digitally/online, notably video and more social network, which will pump up demand for servers, storage, and networking equipment used in ever bigger hosting-based server farms.

Berger notes that perhaps the most sustainable business is in analog and power discretes, with applications in battery life and mobility, and also with low capital expenditure requirements and high depreciation. On the other end of the scale, memory (both DRAM and NAND flash) will continue to suffer as key players reign in spending and output, and pricing and profits remain squeezed tightly.

Equipment firms: “Abysmal” conditions to persist

Think 4Q08 was bad? Wait until companies report for 1Q09, warns Deutsche Bank analyst Stephen O’Rourke. The key to watch, he says, is not the depth of the current downturn, but the duration. “The near-term abysmal industry conditions will likely persist longer than many think,” he warns. He projects a -37% decline in semiconductor capex in 2009 — a number that is “biased quite negatively” — and he sees no signs of recovery until 2010, and even then it’ll be “very modest.” Recent pickups in memory pricing are not a bounce, he noted, but rather a reflection of widespread shutdowns over the holiday period. “We hardly see a balancing of memory supply and demand,” he writes. And even when memory pricing creeps up to the neighborhood of costs, memory suppliers will simply add capacity they’ve taken offline, which will require no new equipment.

What does this mean for equipment suppliers? “Weakness is pronounced in memory, foundry and IDM segments, with aggressive spending cuts across the board,” O’Rourke writes. “We believe that the current downturn has yet to trough and will likely last quite a bit longer than past downturns.” Look for more bloodletting in the frontend semiconductor equipment sector, “significantly deeper than in past downturns” — including the early-2000s tech meltdown.

Scanning the smoldering equipment supplier landscape, O’Rourke takes note of the estimated casualties:

– Applied’s diversity will barely maintain breakeven over the next couple of quarters;
– KLA-Tencor will likely lose money for the first time in 15 years;
– Lam Research will see volume purchases “evaporate”;
– Look for yet another warning from Novellus, after two in recent weeks;
– Expect more cost-cutting at Varian;
– Another ~20% layoffs at Mattson;
– Sales at Rudolph won’t recover much at all in 2009 (sales or losses) after a 1Q trough;
– FEI…actually will outperform! Bookings are said to outpace expectations by $20M.

Turning to the automation sector, O’Rourke sees declining revenues at Brooks and Asyst, as OEM shipments slide. Brooks sales could be down “well over 20% Q-Q” with losses lasting through the year; Asyst, meanwhile, is helped by new AMHS orders (~$86M) but the company won’t be spared overall cutbacks in semi and FPD fabs.

Elsewhere, O’Rourke is somewhat more optimistic about MEMC, which should stay profitable as wafer starts stabilize over the next couple of months, returning to “moderate” unit growth. Not so lucky is Cabot Microelectronics; O’Rourke points out that idling memory fabs mean sharply lower sales of higher-margin tungsten and oxide slurries, the impact of which will be felt across sales and margins through 1H09.

Jan. 16, 2009 – The chip giant’s outlook for the current quarter is unnervingly cloudy, but the message from the chip industry giant is of continued investment in leading-edge technology.

Intel’s 4Q08 results were generally in line with what it and Wall Street had expected, after a couple of late revisions: $2.27B in sales (-23% Q-Q and -19% Y-Y) and a $234M profit, a ~90% plunge Q-Q and Y-Y, with gross margins slipping to ~53% from ~59% in the prior quarter. For FY08, sales slipped -2% from 2007 to $8.2B, with a $5.3B profit off -24% from a year ago.

Noting that the current global economic uncertainty hampers the ability to gauge product demand, Intel refused to pin down 1Q09 estimates, except a general “in the vicinity of $7B,” with gross margins sliding to “the low 40s” due to costs associated with factory underutilization and ramping 32nm manufacturing.

But while others in the chip industry are battening down the fiscal hatches, Intel intends to maintain its investment pace and technology schedule in 2009. “We remain on track for introducing our 32nm process technology in the second half of this year, and we will not slow down this introduction,” said Intel president/CEO Paul Otellini, kicking off the company’s investor/analyst conference call. That said, CFO Stacy Smith noted that the company incurred $250M underutilization charges in 4Q08 (equaling about three points of gross margin) and will “bring the utilization of the factories down dramatically in Q1,” to the tune of an additional eight-point margin decline, amid efforts to work down inventory; utilizations not returning to “a normal range” until sometime in 2H09, he said.

For 2009, Smith said R&D spending would be $5.4B, with capital spending “flat to slightly down” from 2008, primarily to invest in 32nm process technology with an eye toward 2010. “Getting the first capability on 32nm is key to our strategy, and we’re going to get there as quickly as possible,” he said during the call. If adjustments to capex are deemed necessary, echoed Otellini, they’d likely first look at adjusting 45nm work. “We take advantage of the fact that we have reusability and roll-forward capability of stuff we bought for 45nm, so we’d convert that over and still get to leading-edge as fast as possible but do it by reusing investments we’ve already made,” he said. “You can’t do that in a six-month horizon, but you can certainly do that in a horizon that stretches out a year or so.”

So what do analysts think of Intel’s 2009 outlook, particularly in terms of investing and capex?

Deutsche Bank’s Stephen O’Rourke thinks the chipmaker’s 2009 capex will be lower than the $5.2B it spent in 2008, not flat, but the company probably will still be the No. 1 spender for the year as the rest of the industry weathers sharp cutbacks in capex (he projects ≥37% Y-Y). Just about everyone in the frontend semiconductor equipment sector has exposure to Intel, he pointed out; Lam Research and Mattson have no production tools of record at the chipmaker, he writes, but both may have dev tools competing for POTR at the 32nm node, for which all tool selections are likely to be finalized by mid-year prior to a full-scale ramp in early 2010. “A win or a loss of a critical PTOR position at Intel could have material implications to SCE companies as the industry recover,” O’Rourke writes, noting to pay particular attention to Intel’s gate etch and reticle inspection POTR selections.

Meanwhile, FBR Research’s Craig Berger thinks Intel’s foggy 1Q09 guidance was actually “not too bad” and just below consensus of $7.2B, though he considers the gross margins “surprisingly low.” While applauding “Intel’s stellar execution and strong product roadmap,” he recommends investors stay on the sidelines in part because there is “more attractive upside” elsewhere in the semiconductor universe where stocks have been brutalized and theoretically better chance to improve.

January 14, 2009: Nanotubes, the tiny honeycomb cylinders of carbon atoms only a few nanometers wide, are perhaps the signature material of modern engineering research, but actually trying to organize the atomic scale rods is notoriously like herding cats. A new study from the National Institute of Standards and Technology (NIST) and Rice University, however, offers an inexpensive process that gets nanotubes to obediently line themselves up — that is, self-assemble — in neat rows, more like ducks.

A broad range of emerging electronic and materials technologies take advantage of the unique physical, optical and electrical properties of carbon nanotubes, but most of them — nanoscale conductors or “nanowires,” for instance — are predicated on the ability to efficiently line the nanotubes up in some organized arrangement. Unfortunately, just mixed in a solvent, the nanotubes will clump together in a black goo. They can be coated with another molecule to prevent clumping (DNA is sometimes used), but spreading the mixture out to dry results in a random, tangled mat of nanotubes.

There have been a variety of mechanical approaches to orienting carbon nanotubes on a surface, but a more elegant and attractive solution would be to get them to do it themselves — self assembly.

NIST researchers studying better ways to sort and purify carbon nanotubes to prepare standard samples of the material were using a bile acid to coat the nanotubes to prevent clumping. “Bile acids,” says NIST research chemist Erik Hobbie, “are biological surfactants, and like most surfactants they have a part that likes water and a part that doesn’t. This is a slightly complex surfactant because instead of having a head and a tail, the usual geometry, it has two faces, one that likes water and one that doesn’t.”


Single wall carbon nanotubes enclosed in bile acid shells self assembled into a sheaf of long ordered fibrils each composed of several nanotube rods. Treating the microscope slide with a hydrophobic compound causes the fibrils to cluster like this at specific sites. (Image Courtesy of NIST)

Mixed in water, such hydrophobic/hydrophilic molecules normally want to group together in hollow spheres with their hydrophobic “tails” sheltered on the inside, Hobbie explains, but the two-faced geometry of this bile acid makes it form hollow rod shapes instead. Conveniently, the hollow rods can house the rod-shaped nanotubes.

As it turns out, there’s a bonus. Over the course of about a day, the bile acid shells cause the nanotubes to begin lining up, end to end, in long strands, and then the strands begin to join together in twisted filaments, like a length of twisted copper wire.

The discovery is a long way from a perfect solution for ordering nanotubes, Hobbie cautions, and a lot of development remains to be done. For one thing, ideally, the bile acid shells would be removed after the nanotubes are in their ordered positions, but this has proven difficult. And the surfactant is toxic to living cells, which precludes most biomedical applications unless it is removed. On the other hand, he says, it already is an easy and extremely inexpensive technique for researchers interested in studying, for example, optical properties of carbon nanotubes.

“It gives a recipe for how to create ordered, aligned arrangements of individual carbon nanotubes. You don’t need to use any external magnetic or electrical fields, and you don’t need to dry the tubes out in a polymer and heat it up and stretch it. You can get fairly significant regions of very nice alignment just spontaneously through this self assembly.”

(January 13, 2009) SAINT JEOIRE, France &#151 Smart Equipment Technology (S.E.T.), a wholly-owned subsidiary of Replisaurus Technologies, announced a collaboration with IMEC to develop die pick-and-place and bonding processes for 3D chip integration using S.E.T.’s flip chip bonder equipment. As part of the collaboration, S.E.T. will join IMEC’s Industrial Affiliation Program (IIAP) on 3D integration.

IMEC’s 3D integration program explores 3D technology and design for applications in various domains, focusing on 3D wafer-level packaging and 3D stacked-ICs, to find cost-effective uses for 3D interconnects. The joint development program will use the S.E.T. FC300, a high-accuracy (=0.5&#181m), high force (4,000N) device bonder system for D2D and D2W bonding on wafers up to 300mm. The parties will collaborate to develop highly-accurate pick-and-place and low-temperature bonding processes, which are required by advanced 3D integration schemes. The program is scheduled to begin during the first quarter of ’09.

Luc van den Hove, executive V.P. and COO of IMEC, says both Replisaurus and S.E.T. technologies are interesting for advanced packaging applications, and that S.E.T.’s FC300 device bonder system will help complete IMEC’s program.”The integration of the FC300 will be a welcome addition to our 3D program, as is the participation of S.E.T. and Replisaurus,” said van den Hove.

The FC300 is complimentary to electrochemical pattern replication (ECPR) technology, which is well-suited for advanced 3D integration and related applications, notes James Quinn, CEO of Replisaurus. “IMEC’s installation of the FC300 is fully in line with Replisaurus’ product and technology portfolio, which offers game-changing opportunities to the global chip market,” he said.

DECEMBER 19, 2008–VILLE ST. LAURENT, QC, CANADA–Dorsey Marketing Inc. (DMI) is voluntarily recalling the following three G&J Gourmet Market cocoa products because they may contain melamine:

  • G&J Hot Cocoa Stuffer Item 120144 (UPC 061361201444). This hot cocoa product was sold in small green and blue boxes with a backer card, candy cane, and marshmallows.
  • G&J His and Hers Hot Cocoa Set Item 120129 (UPC 489702201296). This cocoa product was sold with two ceramic mugs in a brown box.
  • G&J Cocoa item 120126, sold in 2 flavors: French Vanilla Cocoa and Double Chocolate Cocoa. G&J French Vanilla Cocoa (UPC 061361201260) was sold in a small green bag with a whisk attached. G&J Double Chocolate Cocoa (UPC 061361201260) was sold in a small pink bag with a whisk attached.

No injuries have been reported and only a few samples have, in fact, been found to include melamine. However, DMI is proceeding with this recall in the interest of public health and safety of consumers.

The above recalled products were imported into the United States by DMI and distributed nationwide to retailer Big Lots during the weeks of September 22, 2008 and September 29, 2008 and to retailer Shopko during the week of October 10, 2008.

Consumers who purchased the products are urged to return them to the place of purchase for a refund. Consumers with questions may contact Tim Acheson of DMI Monday through Friday, excluding holidays, between 9:00 AM and 5:00 PM EST toll free at 1-888-645-1053 or e-mail [email protected].

Source: DMI/FDA

Visit www.fda.gov

Moving from DFM to MFD


January 8, 2009

Martin van den Brink, EVP, Marketing & Technology, ASML, Veldhoven, The Netherlands

As the global economic tide starts to recede, it exposes many high technology manufacturing challenges that were otherwise hidden. In the semiconductor industry, these challenges are often opportunities for innovation — and the situation we face in lithography today is an excellent example.

At 32nm and smaller, the design for manufacturing (DFM) approach employs ever-more sophisticated off-line manipulations of illumination shapes and mask patterns (through optical proximity correction and other resolution enhancement techniques), to accommodate fab-floor lithography. Is this the right strategy going forward? What if we took a different approach? What if we questioned the DFM concept?

I believe the coming year will bring a shift toward manufacturability for design (MFD). Fortunately, the industry has the technology in place and the ability to accomplish this shift in production almost immediately. Crucial to this ability is computational modeling and analysis of patterning. These techniques, coupled with double patterning, will allow current systems to address the early 22nm node.

While computational design techniques have been leveraged very successfully, they are by definition using a generic representation of scanner performance. Manufacturing was left with the task of getting the real-world mix of scanners in the fab to match these ideal generic designs. Now, however, the margins required for critical dimension uniformity and overlay have become tight enough that individual scanners must be optimized for each layer of each design in the fab — placing even more importance on MFD.

Computational lithography can be leveraged to apply full-chip modeling and analysis to fleets of optimized scanners on the fab floor, by modeling the unique performance characteristics of each scanner. By combining these models with existing knowledge of tunable scanner parameters, each system can be quickly optimized for each layer and design.

Computational lithography is no longer limited to simply making the mask design suitable for a general scanner type in the fab — DFM. It is now ready to optimize each scanner in the fab to each incoming design — MFD.

Bob Akins, co-founder/CEO, Cymer, San Diego, CA USA

Some industry observers may be under the impression that the cause of the current semiconductor and equipment slowdown is the traditional one — chipmaking overcapacity. However, while there is overcapacity in the memory sector, the primary cause of this slowdown is simply reduced consumer demand. This is not just a semiconductor industry-specific slowdown — housing, financial, automobile, and most other business sectors are in a growing crisis worldwide, resulting in consumer confidence dropping to an all-time low.

Over the past decade, we have watched happily as the consumer has become the largest user of ICs, driving the end demand for more than 60 percent of all chips manufactured; but this is a double-edged sword. When consumers enjoyed plentiful disposable income and there were compelling new electronic applications available, market growth has indeed been very robust. But in this degenerating economic environment, consumers are highly uncertain about the future and not inclined to make discretionary purchases, resulting in dramatically decreased demand for electronic appliances and the chips from which they are built.

During extreme times like these, semiconductor equipment suppliers that will fare best will be those that do three things exceptionally well: 1) Invest in leading-edge technologies and next-generation tools to meet the smaller, but ongoing, demand from chipmakers for leading edge production and advanced process development; 2) introduce new and innovative ways to lower the cost of ownership and increase the efficiency of their customers’ installed base of tools; and 3) leverage the above with lean and efficient business operations management to maintain strength of balance sheet. Suppliers who excel at these endeavors will be best positioned to realize the benefits when worldwide economic conditions improve and the semiconductor industry recovers.

January 7, 2009: Liquidia Technologies, Inc. has entered into a collaboration and license agreement with Abbott to develop PRINT nanoparticles for the delivery of siRNA-based therapeutics. Liquidia’s PRINT (Pattern Replication In Non-wetting Templates) technology offers the ability to fabricate nanoparticles of precisely defined size, shape, surface chemistry, and composition, which offers the potential to develop safer and more effective therapies.

January 7, 2009: Microfluidics, a supplier of advanced fluid processing equipment and reaction technology for the formulation and manufacture of nanomaterials and nanoscale products; and HORIBA Instruments, Inc., maker of analytical instrumentation and measurement technology, announced that their long standing partnership has been formalized. Previously, the two companies have shared marketing efforts, such as seminars and joint customer presentations. From this point forward, these efforts also will include shared exhibit booths at trade shows and exhibitions, and joint advertising and lead generation.