Category Archives: Materials and Equipment

Nov. 6, 2008 – Chipmakers hope that forging new, more open alliances with process tool vendors will enable them to run much more productive, efficient wafer fabs in the future. Tension between chip companies and tool vendors developed with the off-again, on-again transition from 200mm to 300mm wafers. After hundreds of millions were spent on an aborted attempt to make the transition, the actual insertion of 300mm wafers came at a new node, requiring additional costly tool redesigns. Tool vendors traditionally have been wary of letting users understand what goes on inside their equipment. Internal workings of many individual tools have been cloaked in secrecy through the use of operating software, sometimes in binary or assembly code, that is hard or impossible for a user to fathom. This made it difficult for fabs to develop process control to improve processing and maintenance procedures.

Next-Generation Factory (NGF) concepts under the International SEMATECH Manufacturing Initiative (ISMI) call for new standards and more accessible tool operating data so that chipmakers and tool suppliers can collaborate on improving tool utilization and productivity. Many presentations at the recent ISMI Symposium on Manufacturing Effectiveness (Oct. 22-23) probed different aspects of this emerging collaboration.

Traditional barriers must be broken down for this more open approach to take hold. Informal exchanges at past conferences revealed some of the attitudes that must change. Litho engineers from a major chipmaker complained bitterly, for example, that they learned their exposure tool supplier was gathering data from its tool about lens imperfections to use in improving future lens designs. The toolmaker, however, refused to share this information with the customer. An engineer for a major toolmaker explained that a tool’s internal operating instructions should not be accessible to users because any changes could create hazardous conditions.

While chipmakers do want access to tool parameters and some metrics, this can be done without making potentially hazardous changes to internal controls. But there is still concern about built-in sensors revealing too much about a tool’s internal operations, according to Paul McGuire of Alan Weber & Associates. Control data may be the source for customer complaints, and intellectual property may “leak.” Also, service and spares revenue may be reduced if maintenance is stretched out using a condition-based maintenance (CbM) regime. McGuire showed an example where periodic maintenance had been replaced by CbM, so it was done only when needed (see Fig. 1).


Fig. 1: Example of condition-based maintenance replacing periodic maintenance.
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McGuire addressed both of these issues. sometimes maintenance may actually be done sooner rather than delayed. in any event, warrantees may have to be modified for flexible equipment maintenance, with charges for extra support in return for less maintenance and longer MTBFs.

Equipment-Performance Indicators (EPIs) are a way to shield IP, he explained. A single EPI value may be derived using data from multiple internal sensors, but only the EPI will be externally accessible (see Fig. 2). An internal tool model can be used to synthesize an EPI value, and EPIs can provide a status hierarchy for the process and equipment. This aggregates a measure of the health of lower-level modules in the hierarchy, he said. (see Fig. 3)


Fig. 3: EPI summary status values by equipment module or subsystem, can be defined hierarchically to aggregate health of lower level modules into higher ones.

These internal metrics will be needed to move beyond preventative maintenance to the predictive maintenance and anticipatory prognostics envisioned in the NGF, according to McGuire. If the EPI approach is adopted, tool designers will have to find a way to recalibrate internal sensors that are not externally accessible to ensure that readings remain accurate over the various sensors’ ranges.


Fig. 2: EPIs can be hierarchically related, matching the equipment structure hierarchy.
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Eliminating delays in processing and dealing with large amounts of data acquisition as process complexity increases was discussed by Rebecca Cooper of Adventa Control Technologies. Adventa works with Lam Research on “300 Prime” projects, which aim toward NGF goals with classic 300mm technologies.

Automated maintenance procedures can achieve a 31% reduction in data handling, she suggested (see Fig. 4) Maintenance data can be stored on a tool but sent to another site for data analysis and crunching, she said. Modular equipment design with smart wafer scheduling can also shift work to other modules on a cluster tool.


Fig. 4: Example of positive impact of automated procedures/maintenance on mean-time-to-clean (MTTC).
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Cooper said that targets include reducing first-wafer delay, recipe-to-recipe delay, lot-to-lot changeover, and job preparation times. The goal is seamless cascading of lots with different processing requirements (see Fig. 5)


Fig. 5: Cascading host & tool-level recipe tuning for run-to-run control.
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One example she cited was gathering lots of data during the 10-15 sec wafer transfer time. This might require a second port just for gathering data and supplemental communication ports. A Multi-GEM port is one without remote operations capability, she explained (see Fig. 6). Harvey Wohlwend of SEMATECH, the session moderator, added that such a port might handle 10k parameters/sec.


Fig. 6: Data collection using Multi-GEM ports.
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Recipe and parameter (RaP) management is a set of advanced factory capabilities now being devised that could be deployed as part of the NGF transition, according to Lance Rist of ISMI. It will provide tighter control of recipes stored on equipment and also provide for parameterization and on-demand visualization, according to Rist, who is both a chemical engineer and software specialist.

Seventeen device-maker members of ISMI have been working with Selete and other groups on early conceptualization and standards for RaP. The objective, Rist said, is to give chipmakers what they need while keeping requirements reasonable for toolmakers. Early prototyping has already begun with multiple versions ready to go as an alternative to SECS transport using an XML/SOAP protocol now in place in SEMI E139.3. To avoid excessive XML coding, Rist explained, recipes are put into ZIP files for transfer.

One advantage of RaP is that it thus eliminates recipe downloading during a process step, cutting operating costs. Costly “wrong recipe” mistakes caused by unmanaged recipe changes are eliminated by check-sum coding. Gathering use data makes it quicker to trace scrap due to recipe- and parameter-related errors, Rist said. On-demand access to recipe parameters as run-time changeable variable parameters can also speed APC implementation. He added that although RaP does not define how parameters are changed, it does show limit bands in XML format.

An RaP reference implementation (RRI), an executable emulator, has been devised as a tool for developers and users, according to Rist. This provides a learning aide showing how the program works, and it is now available from ISMI.

Implementing the NGF vision will require complete new approaches to enhance chip manufacturing capabilities, Rist stated, and RaP is one example of how this can be accomplished. — B.H.

November 4, 2008: Carl Zeiss SMT, a global provider of electron- and ion-beam imaging and analysis equipment, was honored recently with a prestigious R&D 100 Award for one of the 100 most technologically significant new products in 2008.

R&D Magazine recognized Carl Zeiss SMT’s new Orion Helium-Ion-Microscope for its ability to produce images showing features never seen before. For example, the ORION system can differentiate clearly between materials within semiconductor device cross sections, even in the case of extremely thin layers consisting of only a few atoms. And, as another example, the Orion instrument allows precise imaging and measuring of carbon nanotubes, the building blocks of the new world of nanotechnology.

Based on its resolution of surface details, its unique contrast mechanisms and new analytical capabilities, the Orion microscope enables scientists and researchers to understand the composition of samples and materials close to the atomic level. This will allow new discoveries and product developments within nanotechnology, life sciences and the semiconductor industry.

Dr. Nicholas P. Economou, SVP of Carl Zeiss SMT, stated, “Our team of researchers worked for years to develop this breakthrough microscope technology, which now is empowering scientists in a wide range of scientific endeavors around the world. Having our efforts recognized by an industry-leading technical journal like R&D Magazine is a great honor for our organization and its efforts in fulfilling our commitment.”

According to Martha Walz, editor-in-chief of R&D Magazine, “Winning an R&D 100 Award provides a mark of excellence known to industry, government, and academia as proof that the product is one of the most innovative ideas of the year. We congratulate Carl Zeiss SMT, an organization that is clearly a global leader in the creation of technology-based products that make a difference in how we work and live.”


David Voci, business development manager (left), and Dr. Nicholas P. Economou, SVP of Carl Zeiss SMT, receive the R&D 100 Award from R&D Magazine in recognition of a breakthrough helium-ion-microscope that enables further advancements in nanotechnology. (Photo: Business Wire)

November 3, 2008: NeoPhotonics has been named the 4th ranked firm in Deloitte’s “Technology Fast 50” for Silicon Valley, a ranking of the 50 fastest growing technology, media, telecommunications, and life sciences companies in the region by Deloitte & Touche USA LLP, one of the nation’s leading professional services organizations. Rankings for Deloitte’s Fast 50 list are based on the percentage revenue growth over five years from 2003-2007.

NeoPhotonics is a developer of photonic integrated circuit-based components for telecommunications networks, which include active semiconductor, passive PLC, and MEMS multi-dimensional switching functions in a single product.

NeoPhotonics chairman and CEO Tim Jenks attributes the company’s strong performance in recent years to deepening relationships with the world’s leading manufacturers of telecommunications equipment, including Ciena, ECI Telecom, and Huawei. In addition, the company’s advanced technology platforms and product designs for access, metro and long-haul network applications have the company positioned well for the future.

“Over the last five years we have made significant inroads with tier one customers around the world with multiple products based on our leadership position in optical integration and low-cost manufacturing,” said Jenks, in a statement. “Despite the current economic uncertainty, overall signs are encouraging for continued growth and the skill sets that help us to achieve recognition such as this — innovation, research and the dedication of more than 2000 employees worldwide — will see us through.”

NeoPhotonics revenues soared 15,159% from 2003 to 2007, placing the company fourth in the Internet, Media & Entertainment and Communication category of the 2008 Technology Fast 50 for Silicon Valley. According to Deloitte, the average increase in revenues among companies who made the Technology Fast 50 was 3,242%.

How can smaller operations make existing facilities fit their budgets and their processes with renovations and upgrades?

By Thomas E. Hansz, AIA, Facility Planning & Resources, Inc.

As nanoscale research and analysis is becoming increasingly more and more prevalent in today’s economy, we have seen a significant increase in the need for small-scale clean laboratories. This need is expressed in manufacturing, corporate research centers, and academic research facilities. Whether used for composite materials for cars and packaging materials; in paints, optics, biological and chemical detection systems, or antiseptics; or for cancer therapeutics, drug delivery, imaging, diagnostics, and monitoring applications, new clean laboratories are in demand as never before.

Many times these clean labs are renovations within existing facilities. Recently we have found that some companies and institutions are looking at leased facilities for new controlled laboratories. To complicate matters, some are even considering leased facilities that were never intended for laboratory use, let alone for cleanrooms. For the most part, renovating existing facilities and upgrading leased facilities have many issues in common and this article will touch upon some of them.

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(October 29, 2008) DURHAM, NC &#151Time flies when you’re having fun, or when you’re getting a start-up off the ground. From the introduction of an enabling technology, the thermal copper pillar bump (TCPB), through several rounds of funding, award of the North Carolina Green Business Grant, four product launches incorporating said technology, the construction and grand opening of a manufacturing facility, RoHS compliance, and ongoing plans for more, the past year has been peppered with notable events for Nextreme Thermal Solutions. Paul Magill, Ph.D., V.P of marketing and business development at Nextreme, talked to AP about the company’s philisophy and plans for the future.

“Cool what you need to cool, than manage it appropriately,” noted Magill, referring to Nextreme’s philosophy. From this premise, thermal management takes on new significance. Traditional cooling merely shifts heat to the next level without controlling it, whether it is away from the chip, package, board, system, and beyond. As the problem gets passed up, the solution cost does too. Unfortunately, as Magill explained, this ultimately leads to addressing the problem at the most expensive level. Therefore, by only cooling the part that needs to be cooled, heat abatement becomes much less of a problem at the next level. To illustrate his point, Magill cited energy consumption in data centers, where a fair amount of consumption is attributed to cooling the centers themselves. If these data centers applied Nextreme’s approach of cooling hot spots at the chip level with its TCPB technology, he noted, less energy would be required keep the room’s temperature at a level tolerable to humans.

The concept has caught on quickly. Nextreme first introduced the TCPB technology in October, 2007, and has integrated it successfully into several cooling and power generation devices. With the recent creation of the thermal management products business unit, headed up by Jim Mundell, the company intends to focus on thermal management products and aggressively engage with the telecommunications and photonics markets to enable the integration of the OptoCooler product line into optoelectronic devices.

The OptoCooler UPF4 and OptoCooler UPF40, for LED applications, pump heat at rates of .4 and 4 watts/cm2 respectively. Magill demonstrated how cooling the LED increases its light intensity, which translates to less power consumption and improved reliability. Further modifications included development of an array-based assembly process with bump sizes reduced by 75% to address telecom industry needs for higher voltage and lower current. The result is the recently launched OptoCooler HV14, which is a drop-in device that doesn’t require power conversion.

Additionally, Magill announced the company’s latest news that the OptoCooler UPF4 has been integrated successfully into Voxtel Inc.’s line of hermetically packaged avalanche photodiode (APD) receivers (Figure 1). Used for applications in military laser radar and optical communications and commercial telecommunications, the OptoCooler-equipped APDs reportedly offer improved efficiency, less noise, broader spectral and frequency response; improved overall gain, greater reliability, and a longer life span.

Figure 1: OptoCooler-equipped APDs. (Source: Nextreme)

“We are pleased that Voxtel has chosen Nextreme’s OptoCooler UPF4 for their thermal management solution.,” said Magill. “This represents further validation of our technology in a new application space and opens up a new channel for our OptoCooler product line.”

In addition to cooling applications, TCPB technology is also making inroads in power generation application as a thermoelectric generator (eTEG). When used in conjunction with a heat source and a heatsink the resulting temperature differential generates power. “eTEGs offer a way to convert waste heat into useful electrical energy,” explained Magill. Potential applications for the eTEG devices include powering gas sensor detectors on gas water heaters, or as include trickle charging of batteries for effluent sensors on smoke stacks.

Oct. 24 2008: NaturalNano and Oxford Performance Materials (OPM) have signed an exclusive joint development and supply agreement. Within the scope of the agreement, OPM and NaturalNano will work to develop products, applications and markets for the combination of OPM’s OXPEKK and NaturalNano’s Pleximer technology.

This new class of high-performance thermoplastics, OXPEKK-DRT, is expected to significantly improve the processing and mechanical properties of OXPEKK, while increasing the range of potential applications for current OXPEKK materials. Under the agreement, NaturalNano will purchase certain polyketone polymers exclusively from OPM and, using its Pleximer technology, produce polyketone-halloysite compounds which it will sell exclusively to OPM.

“Our work with NaturalNano has yielded some of the most significant products in the history of our company,” said Scott DeFelice, president and CEO of OPM. “The affinity of our polymer-to-nano-phase fillers has been well known to us for years, though the challenge has always been finding highly reliable and dispersible nano-scale additives. The unique properties of halloysite in NaturalNano’s Pleximer product have solved this problem for us.”

“I am very excited about using our Pleximer technology in Oxford’s OXPEKK,” said Cathy Fleischer, PhD, president and CTO of NaturalNano. “We believe by combining our leading products, we can bring stronger, lighter and less expensive properties to the users of high-value polyketone polymers.”

OPM’s OXPEKK products are specified on the Boeing 787 aircraft. The Boeing 787 aircraft has been slated to contain as much as 50% advance polymer composites in its primary structure, and has been scheduled to enter service in the third quarter of 2009.

OXPEKK-DRT polymer products will initially be marketed to OPM’s core customers in the energy management, aerospace, electronics and medical markets. Existing high performance polymer users in need of additional performance will be a target market for these materials. OXPEKK-DRT materials can be either injection molded or extruded, enabling a broad range of applications.

October 22, 2008: The development of concepts, technologies and devices in nanophotonics during the next few years is envisaged in Emerging Nanophotonics Roadmap [PDF document]. This document, released within the framework of the Photonics21 strategic research agenda, has been promoted by the EU Network of Excellence on nanophotonics (PhOREMOST), composed by 34 partners and over 300 researchers. Prof. Gonçal Badenes, group leader at ICFO/The Institute of Photonic Sciences (Barcelona, Spain), is the chairman of the taskforce that produced this first attempt to map the rapidly evolving field of nanophotonics.

Nanophotonics harvest new functions and properties of nanostructures and sub-wavelength phenomena, with applications in information and communication technologies, environment, transport, security, life sciences, etc. The nanometer and molecular scale of materials involved offers advantages like a higher integration and the expectation of less electrical noise. The roadmap is intended to complement other similar documents and to be a living publication that gets updated and revised regularly. All the topics included in the roadmap have a high potential impact.

In the Concepts section of the roadmap themes are treated such as microcavitites, plasmonics, non-linear optical effects in nanostructures, optical trapping and sorting, metamaterials and random lasers. The Technologies section deals with self-assembly of colloidal structures, nanoimprint lithography as well as functionalization, infiltration methods and organic-inorganic hybridization. A final section on Devices addresses nanophotonic developments of photovoltaics, components for the automobile industry, hybrid waveguides and amplifiers as well as plasmonics-based sensors.


This figure provides an indication of the maturity of technologies in the field. For example, in the case of visible range metamaterials, much of the concept development research has already been done while the technological challenges remain formidable, suggesting that much technology development in this field is needed.

October 16, 2008: Samsung Electronics is demonstrating the world’s first carbon nanotube-based color active matrix electrophoretic display (EPD) e-paper, codeveloped with Unidym Inc., a majority-owned subsidiary of Arrowhead Research Corp., at the International Meeting on Information Display (iMiD) at KINTEX, Ilsan, Korea (Oct. 13-17). The new color e-paper device is a 14.3 inch format display and uses a carbon nanotube (CNT) transparent electrode developed by Unidym.

“In May of this year Samsung demonstrated the world’s first 2.3 inch black and white active matrix EPD made with carbon nanotubes, and now they have demonstrated the first color large scale EPD e-paper device, in an A4 format,” said Arthur L. Swift,Unidym’s president and CEO. “This accomplishment marks a strong beginning to the second year of our joint development agreement to drive technology leadership between our companies in incorporating our carbon nanotube transparent electrodes into current display technologies.”

“This impressive accomplishment has been enabled by our continued improvement in important properties of our CNT films,” stated Paul Drzaic, CTO of Unidym. “To serve the various needs of the electronic display industry, our CNT materials need to demonstrate a number of key attributes: conductivity comparable to the incumbent ITO technology, uniformity over large areas in films, and compatibility with different display technologies and fabrication processes. This achievement between Samsung and Unidym demonstrates the applicability of Unidym’s CNT films in electronic displays.”

EPDs offer inherent advantages over traditional flat-panel displays due to their low power consumption and bright light readability, making them well suited for handheld and mobile applications. Since they can be produced on thin, flexible substrates, EPDs also are ideally suited for use in e-paper applications. Unlike conventional flat-panel displays, EPDs rely on reflected light, and can retain text or images without constant refreshing, thereby dramatically reducing power consumption.


First color carbon nanotube-based electrophoretic display.

By V. Gektin and Margaret Stern, Sun Microsystems; and Lyndon Larson, Dorab Bhagwagar, and Jesus Marin, Dow Corning Corporation azumi Nakayoshi , Dow Corning Toray Co., Ltd.
As power levels and heat generation increase in high-performance CPUs and other semiconductor devices, the thermal performance of commonly used packaging components is becoming a limiting factor. Many such devices are mounted in flip chip packages, in which the die is underfilled on the active side and in direct contact with a thermal interface material (TIM), with a metal or ceramic lid attached on the opposite side. The lid serves as physical protection for the die as well as heat spreader and package stiffener, while the TIM helps to dissipate excess heat.

Electronics-grade silicones have a long history serving in thermal management applications, with the first thermally conductive silicone encapsulant dating back to around 1970.1 Thermally conductive silicone adhesives developed for automotive applications have been in commercial use since the early 1980s. 1 Silicone materials are frequently a choice for the polymer matrix in TIM formulations because of their flexibility and long-term stability. Able to achieve excellent wet-out for void-free contact with substrates, they have been found to contribute to greater reliability in flip chip designs, retaining their physical properties better over time than organic materials exposed to the same conditions. 1 Cured silicone is chemically stable and inherently moisture resistant, with a wide functional span between the glass transition and degradation temperatures.

With power levels steadily rising in new and emerging device designs, manufacturers are seeking improved thermal properties to ensure performance and reliability. A silver-filled silicone material specifically for TIM 1 applications (the die/lid interface) was designed to meet this challenge. Conventional silver-filled epoxies are considered to have good electrical and thermal properties, along with robust adhesion to different substrates, but their high modulus raises concerns over reliability. The newly-developed TIM adhesive combines the potentially high thermal performance of silver-filled materials, with the lower modulus and higher reliability of a silicone matrix.

To confirm the new formulation’s suitability and consistency in a manufacturing environment, while ensuring performance and reliability in the package, extensive physical testing was conducted on thermal and mechanical properties, with particular focus on adhesive bond strength and its dependence on lid material and surface finish. The material exhibited excellent stability in thermal cycling tests as well as long-term heat aging, as shown in Figures 1 and 2.

To supplement physical measurements, several non-destructive test methods were also used to locate voids or potential delamination. The ability to accurately identify defects, whether present at the time of device manufacture or after accelerated testing, was critical in monitoring the production process and confirming coverage and adhesion.

Real-time X-ray and scanning acoustic microscopy (SAM) were used extensively for non-destructive evaluation (NDE) of flip chip packages. In an X-ray shadowgraph, which is absorption driven, areas of low density such as voids appear brightest, while high-density materials such as copper appear darker. X-rays cannot be used to distinguish a delaminated interface, however.

In SAM, which functions by acoustic impedance, the near-total acoustic reflection at an air gap encountered in a void or delamination site produces a dark area in the through-transmission mode (TT or Thru-Scan) and a bright area in the reflected or C-scan mode. SAM produces the best results with crystalline materials that are homogeneous on the acoustic wavelength scale. Imaging software is available for both X-ray and SAM techniques to automatically calculate void areas over the silicon die that can be implemented in manufacturing.

To resolve potential ambiguities that can result from SAM imaging, thermal mapping (measuring the temperatures across the die area) is also an effective technique for detecting delamination at the time of manufacture or after accelerated failure testing. By taking measurements of the local chip temperature at a specified number of locations across the die and comparing results with an established model of a successful package, researchers were able to correlate aberrations with physical effects such as delamination or voiding. (Figure 3.)

A well-adhered part demonstrates higher temperatures at the center of the die, with cooler temperatures prevailing toward the perimeter. In contrast, delamination is observed by the thermal hot spots at the periphery, with cooler temperatures recorded toward the center. Cross-sections evaluated by scanning electron microscopy (SEM) were used to confirm the thermal mapping technique, corroborating evidence that the model is an effective method of predicting good adhesion and subsequent thermal behavior.2

The development and testing process for this new formulation illustrated that new interface materials selected for desirable mechanical and thermal properties may pose challenges to non-destructive package evaluation needed for product screening and reliability testing, as the limitations of any single method prevent unambiguous detection of voids and delamination. Results from both NDE and destructive analysis confirmed that this silver-filled silicone TIM1 material performs well after 260°C solder reflow, HAST, and thermal cycling. It also demonstrated robust adhesion and stability to nickel coated copper and AlSiC lids.

In developing and testing new materials for high-power chip designs, a combination of evaluation methods is presently the only way to confirm performance and processability, with NDE techniques such as real-time X-ray, SAM, and thermal mapping proving to be useful tools.
In the future, NDE techniques such as CT scanning or X-ray laminography may be needed to more accurately track package defects, particularly if the evaluation must be conducted on a functioning manufacturing line.

References:

1. M. Stefan and R. Reinders: “Silicone Thermal Interface Materials For High-Power
Automotive Applications;” Power Systems Design China; Sep/Oct, 2007; p.56.

2. M. Stern, B. Melanson, et al: “Evaluation Of and Inspection Metrology for Lid Attach
for Advanced Thermal Packaging Materials;” IPACK2007-33629; July, 2007;
Proceedings of ASME InterPACK 2007).

Vadim Gektin, Ph.D., P.E., staff engineer, and Margaret Stern, Ph. D., senior staff engineer may be contacted at Sun Microsystems, Inc. [email protected] [email protected] ; Lyndon Larson, application engineer, Dorab Bhagwagar, Ph.D., senior development specialist, and Jesus Marin, account manager may be contacted at [email protected]; Kazumi Nakayoshi Group Leader Conductives & Adhesive Development, may be contacted at Dow Corning Toray Co., Ltd.

By Paul A. Magill, Ph.D., Nextreme Thermal Solutions, Inc.
Electrical latency issues are set to become the limiting factor in obtaining higher processor speeds as the line sizes of the devices themselves continue to shrink. The electronics industry is moving to 3D packaging structures which will shorten the electrical path length, thereby allowing for higher transmission speeds. Of course, as this clears the way for faster processors, it also means that thermal management solutions for these 3D structures will also need to be developed. Cooling solutions will likely need to be integrated in a seamless manner into the existing packaging infrastructure.

Flip chip, a method for interconnecting semiconductor devices to external circuitry, makes use of solder bump arrays that have been deposited onto the chip pads. The flip chip bumping process is one such process that could be investigated for integrating thermal management. In fact, these solder bump structures are sometimes considered for passive removal of heat. They also offer an opportunity to integrate active thermal functionality due to their close proximity to the heat source using thin-film thermoelectric technology. Here we propose to integrate thermally active thin-film material directly into a flip-chip solder bump, in essence, creating a thermally active solder bump.

Core to this new thermal management paradigm is the development of the thermal copper pillar bump, also referred to as the “thermal bump.” The thermal bump is a thermoelectric structure made using a thin-film material that is embedded into flip-chip interconnects (for this discussion, copper pillar solder bumps) for use in electronic packaging. Thin-film thermoelectric materials may be grown using a metalorganic chemical vapor deposition (MOCVD) reactor in layers ranging from fractions of a nanometer to several microns in thickness. The thermal bump makes use of the Peltier effect. For each bump, thermoelectric cooling occurs when a DC current is passed through the bump. The thermal bump pulls heat from one side of the device and transfers it to the other as current is passed through the material.

Figure 1: 100&#181m high thermal bumps arrayed during the manufacturing process

The thermal bump is a method for integrating active thermal management functionality at the chip level in the same manner that transistors, resistors, and capacitors are integrated in conventional circuit designs today. Unlike conventional solder bumps that provide an electrical path and a mechanical connection to the package, thermal bumps act as solid-state heat pumps and add thermal management functionality locally on the surface of a semiconductor chip or other electrical component.

The use of thermal bumps for cooling of 3D electronics offers many advantages in terms of size, efficiency, and power-pumping capability. The bump adds as little as 100100&#181m of thickness to a heat spreader, enabling unobtrusive integration close to the heat source. Thermal bumps have been shown to achieve a temperature differential of 60°C between the top and bottom headers, and have demonstrated power pumping capabilities exceeding 150 W/cm2. This makes thermal bumps ideally suited for applications involving high heat-flux flows. The size advantage of the thermal bump further enhances the integration of thermal management capabilities at the wafer, die, or package levels.

Thermal Bumps in 3D Cooling Applications
Combining thermal bumps with a 3D chip stack structure will lead to thermal management solutions that are also 3D by nature. Figure 2 illustrates the thermal management concept. By extending the only currently available option of passive back-side cooling to also include back and front-side, as well as lateral heat removal in an active manner, thermal management of the 3D stack may be significantly enhanced.

Figure 2: 3D thermal management

Back-side Cooling
Back-side cooling can be enhanced by the introduction of thermal bumps either into the heatsink to form an active heatsink or into the heat spreader. Figure 3 illustrates this approach. Here, discrete devices are used to mitigate hot spots generated on the front side of a die. The following example demonstrates the feasibility of hot spot cooling using integrated thermoelectrics.

Figure 3:Back-side cooling.

For this example the hotspot is on the active side of the die while the thermoelectric device is attached to the copper heat spreader. In future implementations it could be envisioned that the thermoelectric material would be embedded on the back side of the die at the through-silicon-via (TSV). The heat spreader is flipped onto the backside of the die so that the thermoelectric device is located near the backside of the die, behind the first-level thermal interface material, or TIM1.

In this specific example, the entire chip was dissipating 62 W, with 2 W generated by the hot spot, resulting in a hot-spot heat flux of 1,250 W/cm2. The baseline temperature in the area of the hot spot without the TEC is about 111&degC. In this example, the integrated thin-film cooler reduced the hot spot temperature by up to 14&degC.

Lateral Cooling
Figure 4 illustrates the concept and implementation in practice for lateral heat removal. Here, the current flows from left to right, but the heat flows from the center of the module outwards.

Figure 4:Lateral cooling.

For a 3D chip stack, this lateral heat removal concept can be combined with an interposer through which the heat can be removed. Here, the thermoelectric material is underneath the substrate and the heat is pulled from the center segment to the side. Therefore, the center of the platform will be cool and the sides will be hotter as shown. With this approach, heat is dissipated laterally to the walls.

Active-side Cooling
The last approach shown is for active-side cooling. In Figure 5, an artist’s rendition depicts the active side of a microprocessor. The smaller structures represent conventional copper pillar bumps next to the larger thermal bump. There could be as few as 10 -20 or as many as 600 -1200 thermal bumps strategically placed on the chip but only in the vicinity of the hot spots. By doing so, it is not necessary to use a large amount of thermoelectric material