Category Archives: Materials and Equipment

KLA-Tencor Corporation (NASDAQ:  KLAC) and Lam Research Corp. (NASDAQ:  LRCX) today announced that they have agreed to terminate their proposed merger agreement. The parties decided to it was not in the best interests of their respective stakeholders to continue pursuing the merger after the U.S. Department of Justice advised KLA-Tencor and Lam Research that it would not continue with a consent decree that the parties had been negotiating. No termination fees will be payable by either the Company or Lam Research in connection with the termination of the Merger Agreement.

“Although we are disappointed with this outcome, KLA-Tencor’s performance over the past several quarters demonstrates the Company is executing our strategies at a high level and creating compelling value for the industry and for our stockholders,” commented Rick Wallace, President and Chief Executive Officer of KLA-Tencor.

“Today our customer engagement and market leadership is strong and KLA-Tencor is delivering superior financial results. Growth and earnings momentum is expected to continue as we go forward, fueled by new products in the marketplace today, and with many more products in the pipeline,” continued Mr. Wallace. “Additionally, our collaboration over the past year with Lam Research and with our customers has affirmed the value of closer cooperation between process and process control for new, enabling solutions. For that reason, we plan to explore collaboration opportunities with Lam Research around programs identified as beneficial to our customers.”

After the initial announcement of the proposed merger, which was expected to close mid-year 2016, analysts voiced concern over whether the deal would be approved. Robert Maire of Semiconductor Advisors wrote: “We think this is going to be the obvious biggest issue after the failed AMAT & TEL merger.  We think there will likely be opposition in the semi industry but probably less so than we heard the screaming related to AMAT/TEL.”

Today, SEMI announced an exceptional lineup of keynotes at SEMICON Japan’s “SuperTHEATER” focusing on innovation and insights into the future of the electronics supply chain. SEMICON Japan 2016, the largest exhibition in Japan for electronics manufacturing, will take place at Tokyo Big Sight in Tokyo on December 14-16. Registration for the exhibition and programs is now open.

Japan’s semiconductor fab equipment capital expenditure (front-end facilities, both new and used including discretes and LED) is forecast to increase 12 percent (to US$5.0 billion) in 2017, according to the August SEMI World Fab Forecast report.

On December 14, keynotes will focus on the future:

  • Semiconductor Executive Forum – “The Creation of New Business Opportunities” keynotes:
    • Toshiba: Yasuo Naruke, corporate senior executive VP, on “Toshiba Storage Business Strategy; Utilizing Big Data to Win Productivity”
    • TSMC: Jack Sun, VP of R&D and CTO, on “New Frontiers of Semiconductor Innovation”
    • Murata Manufacturing: Hiroshi Iwatsubo, executive VP, on “Business Strategy and Technology Trends”
  • Opening Keynotes – “Into the Future” keynotes:
    • IBM Research:  Dario Gil, VP, Science and Solutions, on “The Cognitive Era and the New Frontiers of Information Technology”
    • University of Tsukuba: Yoichi Ochiai, media artist and assistant professor, Digital Nature Group, on “The Age of Enchantment”

The SEMI Market Forum, also on December 14, with the theme “Outlook and Growth Opportunities in the Electronics Manufacturing Supply Chain” will offer presentations from IHS Markit, VLSI Research Inc., and SEMI.

Highlights on December 15 include Industrial IoT Forum, Autonomous & Connected Car Forum, and U.S. Commercial Service IT Forum. The Technology Trend Forum on December 16 focuses on “The Tokyo 2020 Olympics: Innovation for All.” In addition, SEMICON Japan features forums on Manufacturing Innovation and IoT Innovation.

Attendees at SEMICON Japan will explore the key technologies and business models necessary to grow in the coming years. The SuperTHEATER offers nine keynote forums, all with simultaneous English-Japanese translation, with global top executives.

Platinum sponsors of SEMICON Japan include Disco Corporation, Screen Semiconductor Solutions Co., Ltd. and Tokyo Electron Limited. Gold sponsors include: Advantest Corporation, Applied Materials, Inc., ASE Group, Daihen Corporation, Ebara Corporation, Fasford Technology Co., Ltd., Hitachi High-Technologies Corporation, JSR Corporation, Lam Research Corporation, Nikon Corporation, Tokyo Seimitsu Co., Ltd. and VAT Ltd.

For more information and to register for SEMICON Japan, visit www.semiconjapan.org/en/

Silicon Labs (NASDAQ: SLAB) today announced the acquisition of Micrium, a supplier of real-time operating system (RTOS) software for the Internet of Things (IoT). This strategic acquisition helps simplify IoT design for all developers by combining a commercial-grade embedded RTOS with Silicon Labs’ IoT expertise and solutions. Micrium’s RTOS and software tools will continue to be available to all silicon partners worldwide, giving customers a wide range of options, even when using non-Silicon Labs hardware. Micrium will continue to fully support existing as well as new customers.

Founded in 1999, Micrium has consistently held a leadership position in embedded software components. The company’s flagship µC/OS RTOS family is recognized for reliability, performance, dependability, impeccable source code and extensive documentation.

“With an installed base of millions of devices, Micrium’s RTOS software has established itself as one of the most reliable and trusted platforms over the last 10 years,” said Jean-Michel Orsat, Chief Technology Officer, ICT Standards and Connectivity Solutions at Somfy. “Micrium has been a rock-solid RTOS solution partner for Somfy, and we look forward to using Micrium’s RTOS software family for years to come, delivering the reliability and performance we need for our IoT applications.”

Micrium’s widely deployed RTOS software has been ported to more than 50 microcontroller architectures and has a global footprint with more than 250,000 downloads across all embedded vertical markets, with solutions certified to meet safety-critical standards for medical electronics, avionics, communications, consumer electronics and industrial control.

“By combining forces with Silicon Labs, the Micrium team will drive advances in embedded connectivity for the IoT while giving customers a flexible choice of hardware platforms, wireless stacks and development tools based on the industry’s foremost embedded RTOS,” said Jean J. Labrosse, Founder, CEO and President of Micrium. “We will continue to provide our customers with an exceptional level of support, which is a Micrium hallmark.”

The combination of Micrium’s RTOS and Silicon Labs’ multiprotocol SoCs, wireless modules, wireless stacks and Simplicity Studio development tools gives customers a faster, easier on-ramp from connected devices to the cloud with end-to-end solutions for embedded IoT design.

“IoT products are increasingly defined by software. Explosive growth of memory/processor capabilities in low-end embedded products is driving a greater need for RTOS software in connected device applications,” said Daniel Cooley, Senior Vice President and General Manager of Silicon Labs’ IoT products. “The acquisition of Micrium means that connected device makers will have easier access to a proven embedded RTOS geared toward multiprotocol silicon, software and solutions from Silicon Labs.”

Synopsys, Inc. (Nasdaq:  SNPS) today announced that TSMC is recognizing Synopsys with three “2016 Partner of the Year” awards for Interface IP and joint development of 7-nanometer (nm) mobile and HPC design platforms. Synopsys and TSMC have been collaborating for more than 16 years, most recently to accelerate the adoption of FinFET technology for optimum power, performance and area for the 7-nm process. This is the 6th consecutive year Synopsys has received both IP and electronic design automation (EDA) accolades from TSMC.

“TSMC and Synopsys share a common goal to provide an extensive portfolio of proven IP and design tools supporting TSMC’s latest process technologies,” said Glenn Dukes, vice president of strategic alliances and professional services at Synopsys. “Our strong engineering collaboration with TSMC on its 7-nanometer FinFET process results in a proven path that designers can adopt to help achieve their time-to-market goals.”

“Through OIP collaboration, TSMC and Synopsys continue to provide our mutual customers with certified design implementation tools and high-quality IP optimized for TSMC’s leading process technologies,” said Suk Lee, TSMC senior director of the Design Infrastructure Marketing Division. “With its DesignWare IP and Galaxy Design Platform, Synopsys helps companies achieve their design goals and quickly ramp into volume production.”

Synopsys, Inc. (Nasdaq:  SNPS) today announced a collaboration with TSMC to complete the certification for its 16-nanometer (nm) FinFET Compact (16FFC) process for a suite of Synopsys’ digital, custom and signoff tools from the Galaxy Design Platform. A key result of the certification is that Synopsys’ Custom Compiler solution is supported with TSMC’s 16FFC Process Design Kits (PDKs) through the iPDK standard. With multiple production designs for TSMC’s 16FFC process already underway, the tool certifications enable mutual customers to lower costs and increase reliability with TSMC’s FinFET technology.

The rapid adoption of FinFET technology and increasing functionality for automotive design applications is resulting in higher current densities and, therefore, more wires susceptible to electromigration (EM) effects, such as voids and short circuits. Additionally, the thermal profile of FinFET technology affects the temperature of surrounding metal interconnects, known as self-heating effect (SHE), which affects the possibility of EM failures over time. To address these challenges, TSMC enhances circuit simulation models that assess the impact of SHE on device reliability mechanisms, such as hot-carrier injection (HCI) and bias-temperature instability (BTI). Synopsys supports the new models with the latest versions of its popular HSPICE®, CustomSim™ and FineSim® circuit simulators. The enhanced reliability simulation solution enables designers to model circuit performance degradation over time – a key step toward improving long-term automotive design reliability.

To support TSMC’s 16FFC process, a suite of Synopsys’ digital, custom and signoff tools from the Galaxy platform are validated to handle enhanced design rules and reliability requirements for targeted applications, such as mobile, Internet of Things (IoT) and automotive. The certified tools deliver routing rules, physical verification runsets, signoff-accurate extraction technology files, statistical timing analysis that correlates with SPICE and interoperable process design kits (iPDKs) for the 16FFC process.

“The jointly developed enhancements for automotive design reliability and tool certification for TSMC’s 16FFC process are another significant milestone of the long-term collaboration between Synopsys and TSMC,” said Bijan Kiani, vice president of product marketing of the Design Group at Synopsys. “The latest enhancements and certification for custom, digital and signoff flows are enabling our mutual customers to deliver lower cost and higher reliability for their innovative designs in many application areas such as automotive, IoT and mobile.”

“Through our multi-year collaboration with Synopsys, we are now jointly delivering significant enhancements to improve design reliability for key applications including automotive ADAS and infotainment,” said Suk Lee, senior director of TSMC’s Design Infrastructure Marketing Division. “In addition, tool certification for TSMC’s 16FFC process signals to our mutual designer community that the Galaxy Design Platform tools are ready to be used with our 16FFC process for the development of their next-generation projects.”

Key Synopsys tools certified by TSMC for their 16FFC process include:

  • IC Compiler IITM place and route solution
  • IC Validator signoff physical verification
  • StarRC™ extraction tool
  • PrimeTime® timing signoff solution
  • Custom Compiler custom design solution
  • PrimeRail and CustomSim reliability analysis
  • NanoTime custom timing analysis
  • HSPICE, CustomSim and FineSim simulation

TSMC’s UBM-free fan-in WLCSP


September 21, 2016

BY DR. PHIL GARROU, Contributing Editor

At the 2016 ECTC Conference, TSMC discussed their UFI (UBM-Free Integration) Fan-In WLCSP technology which they claim enables large die fine pitch packages.

Development of low-cost WLCSP for large die with high I/O count is desired for broadening its applications. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5×5 mm2 with ball pitch smaller than 350 μm.

TSMC has discovered that by controlling the maximum strain location and optimizing materials, chip warpage and the stress between silicon and the PCB can be reduced which improves both component and board-level reliabilities of WLCSP packages. Packages as large as 10.3×10.3 mm2 with both 400 and 350 μm ball pitches have been developed.

Screen Shot 2017-04-21 at 9.21.34 AM

UBM is used as an interfacial layer between the metal pad of the integrated circuit and the solder ball. The formation of UBM/ solder intermetallic compounds (IMC) limits the board level reliability of the package due to the poor mechanical robustness of IMCs. When the die size is increased, stress increases which promotes cracking at the UBM/solder ball interface.

TSMC claims their UFI WLCSP fabrication cost is lower than conventional WLCSPs due to the elimination of the UBM. Removal of the UBM also reduces the thickness of the package by 30%. Figure 1 compares the structures of a standard WLCSP vs the TSMC UFI WLCSP. In the UFI WLCSP, the solder balls are directly mounted to the Cu RDL followed by the polymeric PL (protection layer which secure the balls.

Very similar removal of UBM and subsequent thickening of the copper pad has been reported before by Amkor in 2010 [1].

TSMC simulation results showed the solder joint fatigue life decreases with increasing die sizes for both UFI and the conventional WLCSP. Predicted solder ball fatigue life was found to increases with decreasing die thickness. The authors suggest that decreasing the die thickness not only reduces the thermal expansion difference between the die and the PCB, but also causes the die to bend more under thermal loading. In addition, simulation results imply that solder joint creep strain for solder mask defined (SMD) structures is 72% higher than for non-solder mask defined (NSMD) structures because of its reduced flexible solder joint height and the constraint of the solder mask. Thus they concluded that it is better to use NSMD type of PCB for UFI WLCSP. The use of NSMD structures to increase reliability has been known since the work of Bell Labs Ejim [2].

The UFI WLCSP passes all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution, respectively. 10mm UFI WLCSP have passed component-level reliability tests such as TCB1000, uHAST96 and HTS1000, and board- level reliability tests of TCG500 and drop tests.
To demonstrate the possibility of higher interconnect density, they fabricated UFI- WLCSP with multiple RDL layers. The package with two RDL layers had die size of 10.3 x 10.3 mm2 and ball pitch of 350 μm (Figure 2). Again such structures passed all component level reliability testing.

References

1. http://imapsource.org/doi/abs/10.4071/2010DPC- tha32?journalCode=apap
2. TI Ejim et. al., “Reliability performance and failure mode of high I/O thermally enhanced ball grid array packages” Electronics Manufacturing
Technology Symposium, 1998, p.323 – 332.

Solid State Technology announced today that its premier semiconductor manufacturing conference and networking event, The ConFab, will be held at the iconic Hotel del Coronado in San Diego on May 14-17, 2017. A 30% increase in attendance in 2016 with a similar uplift expected in 2017, makes the venue an ideal meeting location as The ConFab continues to expand.

    

For more than 12 years, The ConFab, an invitation-only executive conference, has been the destination for key industry influencers and decision-makers to connect and collaborate on critical issues.

“The semiconductor industry is maturing, yet opportunities abound,” said Pete Singer, Editor-in-Chief of Solid State Technology and Conference Chair of The ConFab. “The Internet of Things (IoT) is exploding, which will result in a demand for “things” such as sensors and actuators, as well as cloud computing. 5G is also coming and will be the key technology for access to the cloud.”

The ConFab is the best place to seek a deeper understanding on these and other important issues, offering a unique blend of market insights, technology forecasts and strategic assessments of the challenges and opportunities facing semiconductor manufacturers. “In changing times, it’s critical for people to get together in a relaxed setting, learn what’s new, connect with old friends, make new acquaintances and find new business opportunities,” Singer added.

Dave Mount

David Mount

Solid State Technology is also pleased to announce the addition of David J. Mount to The ConFab team as marketing and business development manager. Mount has a rich history in the semiconductor manufacturing equipment business and will be instrumental in guiding continued growth, and expanding into new high growth areas.

Mainstream semiconductor technology will remain the central focus of The ConFab, and the conference will be expanded with additional speakers, panelists, and VIP attendees that will participate from other fast growing and emerging areas. These include biomedical, automotive, IoT, MEMS, LEDs, displays, thin film batteries, photonics and advanced packaging. From both the device maker and the equipment supplier perspective, The ConFab 2017 is a must-attend networking conference for business leaders.

The ConFab conference program is guided by a stellar Advisory Board, with high level representatives from GLOBALFOUNDRIES, Texas Instruments, TSMC, Cisco, Samsung, Intel, Lam Research, KLA-Tencor, ASE, NVIDIA, the Fab Owners Association and elsewhere.

Details on the invitation-only conference are at: www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For details on attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].

Toshiba America Electronic Components, Inc. (TAEC) has expanded its family of 24nm single-level cell (SLC) NAND flash memory solutions. The new 16 gigabit (Gb) BENAND is housed in an industry-standard 48-pin TSOP package, and offers a combination of high read/write performance, effective write endurance (using 8-bit BCH error correction code), and extended temperature operation. This makes it suitable for a wide variety of commercial and industrial applications.

The new addition rounds out Toshiba’s broad SLC product lineup, allowing designers to take advantage of the price/performance of advanced 24nm NAND flash SLC technology at densities from 1Gb to 128Gb. Based on a 4x4Gb die, 16Gb BENAND operates from a power supply of 2.7V to 3.3V with a temperature range of -40°C to 85°C. Many industrial applications have a long life expectancy. Toshiba designed BENAND with this in mind. With the ability to replace older generations of discrete SLC NAND, BENAND extends the product life of everything from telecom applications and LCD TVs to robots and printers – while also potentially reducing BOM costs.

According to Brian Kumagai, director of business development for TAEC, “SLC NAND is still very much an integral part of the overall NAND market, and leading-edge 24nm devices play a key role in enabling replacement of the older NAND devices that are still being used today.”

Toshiba’s 24nm BENAND requires no ECC from the host controller. This enables it to be used with host controllers that do not have 8-bit ECC capability.  Many legacy designs still use older processors that do not have 8-bit ECC capability, making BENAND a viable option for companies looking to design in a cutting-edge NAND solution with existing hardware. To ensure easy migration, BENAND’s features such as page/block size, spare area size, commands, interface and package remain the same as legacy 4xnm SLC NAND.

Toshiba’s continuing commitment to supporting 24nm SLC NAND flash provides industrial designers with the confidence of knowing that they have chosen the correct technology for their applications requiring production longevity. This support eliminates concerns about redesigning to a newer generation.

By Zvi Or-Bach, President & CEO, MonolithIC 3D Inc.

As we have predicted two and a half years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.

Our March 2014 blog Moore’s Law has stopped at 28nm has recently been re-confirmed. At the time we wrote: “From this point on we will still be able to double the amount of transistors in a single device but not at lower cost. And, for most applications, the cost will actually go up.” This reconfirmation can be found in the following IBS cost analysis table slide, presented at the early Sept FD-SOI event in Shanghai.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

As reported by EE Times – Chip Process War Heats Up, and quoting Handel Jones of IBS “28nm node is likely to be the biggest process of all through 2025”.

IBS prediction was seconded by “Samsung executive showed a foil saying it believes 28nm will have the lowest cost per transistor of any node.” The following chart was presented by Samsung at the recent SEMICON West (2016).

Zvi 2

And even Intel has given up on its “every two years” but still claims it can keep reducing transistor cost. Yet Intel’s underwhelming successes as a foundry suggests otherwise. We have discussed it in a blog titled Intel — The Litmus Test, and it was essentially repeated by SemiWiki’s Apple will NEVER use Intel Custom Foundry!

This discussion seems academic now, as the actual engineering costs of devices in advanced nodes have shown themselves to be too expensive for much of the industry. Consequently, and as predicted, the industry is bifurcating, with a few products pursuing scaling to 7nm while the majority of designs use 28nm or older nodes.

The following chart derived from TSMC quarterly earnings reports was published last week by Ed Sperling in the blog Stepping Back From Scaling:

Zvi 3

Yes, the 50-year march of Moore’s Law has ended, and the industry is now facing a new reality.

This is good news for innovation, as a diversity of choices helps support new ideas and new technologies such as 3D NAND, FDSOI, MEMS and others. These technologies will enable new markets and products such as the emerging market of IoT.

A good opportunity to learn more about these new scaling technologies is the IEEE S3S ’16, to be held in the Hyatt Regency San Francisco Airport, October 10th thru 13th, 2016. It starts with 3D and FDSOI tutorials, the emerging technologies for the IC future. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D, and three leading researchers from an imec, MIT, and Korea university collaboration will present their work on advanced monolithic 3D integration technologies. Many other authors will discuss their work on monolithic 3DIC and its ecosystem, in addition to tracks focused on SOI, sub-VT and dedicated sessions on IoT.

As part of an initiative to optimize service to the growing global polymer processing market, Nordson Corporation (Nasdaq:NDSN) today announced it plans to combine its existing screw and barrel operations in Youngstown, Ohio; New Castle, Pennsylvania; and Pulaski, Virginia into a single expanded manufacturing center of excellence in Austintown, Ohio.

“We expect this initiative to drive efficiencies in manufacturing processes, decrease lead times, enhance customer service, improve competitiveness and accelerate growth,” said John Keane, Nordson Corporate Senior Vice President. “Our plan is for Austintown to join similar regional hubs for our screw and barrel products in Thailand and Germany. No other single supplier will be able to provide the polymer industry with such localized service on a global scale.”

Nordson expects the transition to an existing facility in Austintown to be completed over the next 18 months, subject to the conclusion of customary negotiations with local and state officials. The transition will occur in stages to minimize any potential impact to current customers. Planned investments in the facility over the period include upgraded bi-metallic processing and machining systems to improve product quality, precision and throughout.

The majority of positions in the existing Youngstown, New Castle and Pulaski facilities will transfer to the Austintown facility. Total employment in Austintown is expected to be approximately 260. Nordson will be actively recruiting for any positions not being filled by current employees.