Category Archives: Materials and Equipment

BY DR. PHIL GARROU, Contributing Editor

At the ECTC conference in May, in the “Advances in Fan Out Packaging” session, Matt Lueck of RTI International discussed the results of their joint program with X-Celeprint.

A common aspect to all fan-out packaging is the requirement to physically assemble devices into dispersed arrays, often called reconfigured wafers, which provides the real estate needed to fan-out. Devices made in sub-mm chip sizes can impose cost and performance challenges to FO-WLP using serial pick-and place assembly technologies. RTI and X-Celeprint joined forces to develop a fan out package for sub mm IC using the X-Celeprint massively parallel assembly technology called micro transfer-printing, which is well-suited for handling very thin and fragile devices.

In their micro transfer-printing technology a polymer layer is first applied to the substrate before the assembly process, and the devices are assembled in a face-up configuration. Following the formation of the reconfigured substrates, conventional redistribution layer (RDL) and solder ball processing was performed. Two different photo-imageable spin on dielectrics, HD4100 PI and Intervia 8023 epoxy, were used as the RDL dielectrics. The fan-out package contains no molding compound and is made using standard wafer-level packaging tools.

There are potential benefits from fan-out packaging strat- egies that do not require molding compound. The process described here does not suffer from the “die drift” that occurs during compression molded fan-out packaging which often requires special adaptive alignment techniques. It also does not suffer from the wafer and package warpage that can occur in molding compound based fan-out packages.

Micro-transfer printing was used to assemble reconfigured wafers of devices (80um x 40um chips with a redistribution metal and six contact pads), onto 200mm wafers. After assembly, they undergo a standard wafer level redistribution and bumping process. The final fan-out package pitch on the 200 mm wafer is 1.4mm x 1.0mm with six 250 μm solder bumps. The fan-out packages were assembled and reflowed onto FR4 test boards.

The Figure shows (A) the chiplet source wafer after partial removal of chiplets with the elastomer stamp; (B) a completed fan out package before solder ball placement; (C) close-up of the interconnect to the chi pads; (D) Final FO-WLP. Initial yields are reported to be 97%.

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Two PCB test vehicles populated with 60 die each were built for thermal cycle testing. The board level thermal cycle testing was run under -40°C to 125°C. None of the die showed more than 0.2 ohm change in average resistance.

200mm fabs reawakening


July 13, 2016

By David Lammers, Contributing Editor

Buoyed by strong investments in China, 200mm wafer production is seeing a re-awakening, with overall 200mm capacity expected to match its previous 2006 peak level by 2019 (Figure 1).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Figure 1. By 2019, 200mm fab capacity should be close to the previous peak seen in 2006, according to SEMI. Several new 200mm fabs are expected to open in China. (Source: SEMICON West presentation by Christian Dieseldorff).

Speaking at a SEMI/Gartner market symposium at SEMICON West, SEMI senior analyst Christian Dieseldorff said over the next few years “we don’t see 200mm fabs closing, in fact we see new ones beginning operation. To me, that is just amazing.”

The numbers back up the rebound. Excluding LEDs, the installed capacity of 200mm fabs will reach about 5.3 million wafers per month (wspm) in 2018, almost matching the 2007 peak of 5.6 million wspm. As shown in Figure 1, By 2019 as new 200mm fabs start up in China, 200mm wafer production will surge beyond the previous 2007 peak, a surprising achievement for a wafer generation that began more than 25 years ago. Figure 2 shows how capacity, which held steady for years, is now on the increase.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Figure 2. 200mm fab capacity, which remained relatively constant for years, is now increasing.

Case in point: On the opening day of Semicon West, Beijing Yangdong Micro announced a new OLED 200mm fab that will be opening in the second half of 2018 to make OLED drivers, according to Dieseldorff.

Over the past few years, Japan-based companies have closed 10 200mm fabs, mostly outdated logic facilities, while expanding production of discrete power and analog ICs on 200mm wafers. But with China opening several new 200mm fabs and the expansions of existing 200mm fabs worldwide, SEMI sees an additional 274,000 wafer starts per month of 200mm production over the 2015-2018 period, adding expansions and additional fabs, and subtracting closed facilities.

“One message from our research is that we believe the existing 200mm fabs are full. Companies have done what they can to expand and move tools around, and that is coming to an end,” he said. SEMI reckons that 19 new 200mm fabs have been built since 2010, at least six of them in China.

SEMI’s Christian Dieseldorff.

SEMI’s Christian Dieseldorff.

Dieseldorff touched on a vexing challenge to the 200mm expansion: the availability of 200mm equipment. “People have problems getting 200mm equipment, used and even new. The (200mm) market is not well understood by some companies,” he said. With a shortage of used 200mm equipment likely to continue, the major equipment companies are building new 200mm tools, part of what Dieseldorff described as an “awakening” of 200mm manufacturing.

 

China is serious

Sam Wang, a research vice president at Gartner who focuses on the foundry sector, voiced several concerns related to 200mm production at the SEMI/Gartner symposium. While SMIC (which has a mix of 200mm and 300mm fabs) has seen consistently healthy annual growth, the five second-tier Chinese foundries – — Shanghai Huahong Grace, CSMC, HuaLi, XMC, and ASMC — saw declining revenues year-over-year in 2015. Overall, China-based foundries accounted for just 7.8 percent of total foundry capacity last year, and the overall growth rate by Chinese foundries “is way below the expectations of the Chinese government,” Wang said.

The challenge, he said, is for China’s foundries which rely largely on legacy production to grow revenues in a competitive market. And things are not getting any easier. While production of has shown overall strength in units, Wang cautioned that price pressures are growing for many of the ICs made on 200mm wafers. Fingerprint sensor ICs, for example, have dropped in price by 30 percent recently. Moreover, “the installation of legacy nodes in 300mm fabs by large foundries has caused concern to foundries who depend solely on 200 mm.”

But Wang emphasized China’s determination to expand its semiconductor production. “China is really serious. Believe it,” he said.

New markets, new demand

The smart phone revolution has energized 200mm production, adding to a growing appetite for MEMS sensors, analog, and power ICs. Going forward, the Internet of Things, new medical devices, and flexible and wearable products may drive new demand, speakers said at the symposium.

Jason Marsh, director of technology for the government and industry-backed NextFlex R&D alliance based in San Jose, Calif., said many companies see “real potential” in making products which have “an unobtrusive form factor that doesn’t alter the physical environment.” He cited one application: a monitoring device worn by hospital patients that would reduce the occurrence of bed sores. These types of devices can be made with “comparatively yesteryear (semiconductor) technology” but require new packaging and system-level expertise.

Legacy devices made on 200mm wafers could get a boost from the increasing ability to combine several chips made with different technologies into fan out chip scale packages (FO CSPs). Bill Chen, a senior advisor at ASE Group, showed several examples of FO CSPs which combine legacy ICs with processors made on leading-edge nodes. “When we started this wafer-level development around 2000 we thought it would be a niche. But now about 30 percent of the ICs used in smart phones are in wafer-level CSPs. It just took a lot of time for the market forces to come along.”

More coverage from this year’s SEMICON West can be found here.

Rudolph Technologies, Inc. (NYSE: RTEC) today unveiled its new patented Clearfind technology, which can detect organic defects that are difficult or impossible to see with conventional white-light imaging techniques. Organic contaminants are often the root cause of field failures, which occur after the material has been exposed to operating conditions for extended periods. Rudolph has been actively collaborating with several key customers to fully understand their inspection challenges and how the new technology addresses them, and plans to incorporate Clearfind technology in its upcoming defect inspection systems for advanced packaging applications.

“As advanced packaging processes become more complex, process windows are shrinking and manufacturers are seeking better methods for control and inspection that balance the need for high throughput against the ‘escape’ of true defects and the ‘false positive’ detection of nuisance defects,” said Mike Goodrich, vice president and general manager of Rudolph’s Process Control Group. “Organic defects, in particular, have become more troublesome as die interconnects shrink and there is less surface area for good adhesion. Clearfind technology will help our customers see these defects earlier in the process, permitting faster action to mitigate the root cause and reducing the amount of product in jeopardy.”

Goodrich continued, “Using laser illumination we are able to clearly identify residue defects that typical white-light optics would miss. In addition to optimizing the wavelength of the illumination to enhance detection, we have specifically designed the mechanics of the system to accommodate the high warpage found in advanced packaging applications.”

Clearfind technology highlights organic residues on bumps and bond pads or at the bottoms of vias so that they are easy to detect. On metals, it eliminates the high-contrast graininess seen under conventional illumination, resulting in an obvious defect signal against a featureless background. This same graininess in conventional imaging can also cause false positives, which are especially costly at this stage of the process where the sunk cost of unnecessarily rejected good product is high. Finally, Clearfind technology readily detects shorts and opens in metal lines when inspected with an underlying organic layer. Rudolph believes these capabilities will significantly increase its customer’s ability to detect process and manufacturing related issues earlier in the process resulting in significant yield, which equates to millions of dollars in savings, especially for processes utilizing known-good die. Rudolph’s customers see this as a critical technology to improve quality for their customers in order to avoid the high costs of replacement and penalties.

For more information about the new Clearfind technology, please visit Rudolph at SEMICON West, booth 6543, in the North Hall.

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Applied Materials, Inc. today announced its next-generation e-beam inspection system is delivering the highest resolution and image quality at the fastest throughput to leading foundry, logic, DRAM and 3D NAND customers as they move to advanced nodes.

The Applied PROVision– system is the industry’s most advanced e-beam inspection tool, incorporating innovations based on more than 20 years of leading expertise in e-beam technology for review and metrology. It is the only e-beam hotspot inspection tool offering down to 1nm resolution, allowing customers to detect the most challenging “killer” defects that other technologies cannot find, and to monitor process marginality to rapidly resolve ramp issues and achieve higher yields.

“The PROVision system is the latest addition to our e-beam portfolio, and is a key part of Applied’s growth strategy,” said Bob Perlmutter, vice president and general manager of Applied’s Imaging and Process Control Group. “Our differentiated e-beam column technology is the best in the industry and when coupled with our customers’ new inspection methodologies, enables the PROVision system to go beyond R&D use and into production environments.”

The PROVision system is gaining momentum with already more than a dozen shipments, including repeat orders from a leading foundry and a major memory manufacturer. Additional systems are scheduled for shipment to existing and new customers in the second half of 2016.

“The PROVision system’s unique combination of high resolution and massive sampling has helped accelerate time to solution and time to market for our advanced nodes,” said Dr. Oh-Jang Kwon, SK hynix R&D EBI Group.

Offering 3x faster throughput over existing e-beam hotspot inspection tools, the PROVision system ensures accurate process characterization, prediction and detection of performance- and yield-limiting defects throughout the fab product life cycle. The PROVision system complements Applied’s e-beam metrology and review products as well as the optical patterned wafer inspection product line.

071116 Applied PROVision system

The health of the semiconductor industry is increasingly tied to the health of the worldwide economy. Rarely can there be strong semiconductor market growth without at least “good” worldwide economic growth to support it. Consequently, IC Insights expects annual global semiconductor market growth rates to continue to closely track the performance of worldwide GDP growth (Figure 1).  In its upcoming Mid-Year Update to The McClean Report 2016 (to be released at the end of July), IC Insights forecasts 2016 global GDP growth of only 2.3%, which is below the 2.5% level that is considered to be the global recession threshold.

Figure 1

Figure 1

In many areas of the world, local economies have slowed.  China, which is the leading market for personal computers, digital TVs, smartphones, new commercial aircraft, and automobiles, is forecast to continue to lose economic momentum in 2016.  Its GDP is forecast to increase 6.6% this year, which continues a slide in that country’s annual GDP growth rate that started in 2010 when growth rates exceeded 10%.

IC Insights believes that the worldwide economy will be negatively impacted, at least over the next year or two, by the Brexit vote this past June.  At this point, since the U.K. is unlikely to officially be able to leave the European Union (EU) for a couple of years, the biggest negative effect on economic growth is the uncertainty of the entire situation.  Some of the uncertainty created by the vote includes:

•    Whether the U.K. will actually leave the EU.  Since the Brexit vote is not legally binding, and still needs to be approved by the U.K. government, there is uncertainty if its departure from the EU will actually happen.

•    Whether the U.K. will come apart itself.  There are rumblings about Scotland breaking away from being a part of the U.K. in order for it to remain as part of the EU.

•    What trade deals will be made by the U.K. if it does leave the EU?  As part of its exit from the EU, the U.K. will need to establish numerous new trade deals with the EU.  There is tremendous uncertainty regarding whether these deals would have a positive or negative effect on the U.K. economy.

•    Will other countries follow the U.K. and depart from the EU?  Anxiety persists over whether the EU will fall apart as other countries attempt their own exit.  Some countries mentioned as possibly following the U.K. out of the EU include the Netherlands (Nexit), France (Frexit), Italy, Austria, and Sweden (Swexit).

The other major “culprit” dragging down semiconductor industry growth this year is the very weak DRAM market.  At $45.0 billion, the DRAM market was the largest single product category in the semiconductor industry in 2015.  IC Insights forecasts that the DRAM market will register a 19% drop of $8.5 billion this year to $36.5 billion.  The DRAM market alone is forecast to shave three percentage points off of total semiconductor market growth this year. Semiconductor market growth excluding DRAM is forecast to be +2%.

Most of the DRAM market decline expected for this year is due to a rapid decline in DRAM pricing over the past 18 months.  For 2016, the average price for a DRAM device is forecast to drop to $2.55, a steep 16% decline as compared to 2015’s DRAM ASP of $3.03. Further trends and analysis relating to semiconductor market forecasts through 2020 will be covered in the 250-plus-page Mid-Year Update to the 2016 edition of The McClean Report.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced new capabilities on the EVG ComBond automated high-vacuum wafer bonding platform specifically designed to support high-volume manufacturing (HVM) of advanced MEMS devices. These capabilities include a new vacuum bond alignment module that provides sub-micron face-to-face alignment accuracy essential for wafer-level MEMS packaging, and a new bake module that performs critical process steps to achieve outstanding bond quality and performance of encapsulated MEMS devices.

The addition of these two new modules–coupled with existing capabilities on the highly configurable EVG ComBond platform such as room-temperature covalent bonding of engineered substrates–enables customers to meet the wafer bonding requirements for both current and emerging types of MEMS devices. Examples include gyroscopes, microbolometers, and advanced sensors for autonomous cars, virtual reality headsets and other applications.

“When EV Group introduced the EVG ComBond platform, we set a new standard in high-vacuum wafer bonding by building the product around a modular, highly customizable cluster design concept. This has enabled us to continually expand the capabilities of the platform over time, with applications ranging from advanced engineered substrates, power devices and solar cells to high-performance logic and ‘Beyond CMOS’ devices,” stated Paul Lindner, executive technology director,
EV Group. “With the addition of new vacuum alignment and bake modules, those wafer bonding capabilities have been expanded yet again to address the volume manufacturing needs for high-end MEMS devices.”

Challenges of scaling MEMS wafer bonding into production

Many MEMS devices have extremely small moving parts, which must be protected from the external environment. Wafer-level capping can seal a wafer’s worth of MEMS devices in one operation, and these capped devices can then be packaged into much simpler and lower-cost packages. Metal-based aligned wafer bonding is the preferred approach to MEMS wafer bonding, but is challenging to implement due to the high process temperatures involved as well as the presence of oxides that form on the bonding metal layers. As MEMS die and feature sizes decrease, achieving tighter wafer alignment accuracy also becomes increasingly important.

At the same time, vacuum encapsulation is increasingly needed for certain MEMS devices in order to reduce power consumption caused by parasitic drag, reduce convection heat transfer, or prevent oxide corrosion. Maintaining the required vacuum level for the entire wafer bonding process has been a key challenge for ramping these devices into high-volume production.

The EVG ComBond platform provides a complete end-to-end high-vacuum environment (10-8 mbar range) throughout all wafer handling, pre-bonding and bonding processes. This modular configuration significantly improves serviceability, as modules can be swapped out without breaking the vacuum level within the cluster or modules and interrupting tool operation.

New MEMS wafer bonding capabilities

New to the EVG ComBond platform is the vacuum alignment module (VAM) with wafer clamping, which enables sub-micron face-to-face alignment accuracy based on EVG’s proprietary SmartView alignment process, as well as backside and IR alignment, in a high-vacuum environment. Also new is the programmable dehydration bake and getter activation module, which accelerates the removal of sticking gas molecules prior to bonding the substrates–resulting in improved bond quality as well as reduced gas pressure in device cavities.

In addition, the EVG ComBond platform features an optional ComBond Activation Module (CAM), which enables covalent and oxide-free wafer bonding processes at room temperature or low temperatures. Integrated into the ComBond platform, the CAM allows low-temperature bonding of metals, such as aluminum, that re-oxidize quickly in ambient environments–enabling customers to reduce production costs and achieve higher wafer-bonding throughputs.

The EVG ComBond platform with the new alignment and programmable dehydration bake and getter activation modules is currently available and can be demonstrated at EVG’s headquarters.

Media, analysts and potential customers interested in learning more about EVG’s suite of wafer bonding solutions, including the EVG ComBond platform, are invited to visit the company’s booth #1017 in the South Hall of the Moscone Convention Center in San Francisco, Calif., at the SEMICON West show on July 12-14.

A research team at Clarkson University reports an interesting conclusion that could have major impacts on the future of nano-manufacturing. Their analysis for a model of the process of random sequential adsorption (RSA) shows that even a small imprecision in the position of the lattice landing sites can dramatically affect the density of the permanently formed deposit.

With the advent of nanotechnology, not only can we deposit tiny particles, but the target surfaces or substrates can be tailored to control the resulting structures.

This article addresses the precision that must exist in the pattern of the target surface, in order to achieve high perfection and high coverage in the pattern of deposited particles. To do this, it compares RSA on three types of surfaces: a continuous (non-patterned) lattice, a precisely patterned surface, and a surface with small imprecisions in the pattern. The researchers find that very small imprecisions can make RSA proceed as if the surface is continuous. The consequence is that the deposition process is less efficient, and the ultimate coverage is much lower. In the process of RSA, a continuous surface is covered slowly with a larger fraction of the area remaining uncovered than a precisely lattice-patterned surface. In the past when surfaces on which microscopic particles were deposited were naturally flat (continuous) or had a lattice-structure, the importance of small imprecisions had not been recognized.

The researchers explain their analysis this week in the Journal of Chemical Physics, from AIP Publishing.

Vladimir Privman at Clarkson University has been involved in studying aspects of such systems since 2007; however this study, conducted with graduate student Han Yan, was the first to consider the imprecision in the surface lattice-site localization, rather than in the particle size uniformity.

Initially suggested by computer modeling, their results were later derived by analytical model considerations which are novel for the research field of RSA.

“The greatest difficulty was to understand and accept the initial numerical finding that suggested results that seemed counterintuitive,” Privman explained. “Once accepted, we could actually confirm the initial findings, as well as generalize and systematize them by analytical arguments.”

Pre-patterned substrates have been studied for applications ranging from electronics to optics, to sensors, and to directed crystal growth. The reported results suggest that efforts at precise fixed positioning and object-sizing in nano-manufacturing might be counterproductive if done as part of forming structures by RSA, under practically irreversible conditions. A certain degree of relaxation, to allow objects to “wiggle their way” into matching positions, may actually be more effective in improving both the density and rate of formation of the desired dense structures, Privman said.

This work has implications that the team is preparing to explore.

“Now that we have realized that not only particle non-uniformity, but also substrate-pattern imprecision have substantial effects on the dynamics of the RSA process, we will begin studying various systems and patterning geometries, expanding beyond our original model,” Privman said.

What do you use to handle thin wafers and thin reconstituted wafers?  Increasingly miniaturized electronic devices require decreased profile heights, reduced foot-prints and ultimately, the perpetual thinning of wafers.  Initially, working with thin wafers typically required temporary bonding of the wafer to a carrier and use of a temporary coating layer for wafer protection.

For fan-out wafer-level packaging and 3D packaging, thin wafer handling is critical; the wafer must not warp, bend or shift during any wafer-processing steps.  These wafer processing steps may involve different temperature ranges and exposure to a variety of chemicals depending on the processing steps such as etching, metallization, CMP, PVD, RDL in embedded, fan-out, and 3D wafer-level packaging.

AI Technology, Inc. (AIT) manufactures a series of temporary bonding materials for processing temperatures up to 150 Cº. They are well accepted for grinding, dicing, etching, and deposition.  AIT customers prefer AIT bonding materials over conventional wax materials specifically because AIT’s products feature ease of use and quick removal, especially for very delicate compound wafers and photonics.

For higher temperature processing, AI Technology, Inc. (AIT) developed high temperature wafer processing adhesives (WPA) that can withstand processing temperature up to 330ºC. Also important is the chemical resistance of these WPA materials to acids and bases during the etching processes.  The thermal and chemical stability allows these adhesive to maintain its chemical integrity allowing the thin wafer be separated from the wafer handler/carrier by heat-sliding or by laser de-bonding equipment.  The WPA adhesive layer is designed to absorb UV breaking chemical bonds at the interface allowing for ease of separation.  After separation, the WPA adhesive layer can be removed by peeling with minimum stress or solvent cleaning.

Besides supplying these WPA products in spin coating liquid, AI Technology, Inc. (AIT) also provides WPA as a thin film. This unique and innovative WPA-film minimizes processing time and total waste produced compared to a typical spin-coating process allowing higher through-put.  In high volume manufacturing, some fan-out packaging involves reconstituted panels with larger dimensions compared to the traditional circular and small wafer size. For these high volume manufacturing panels, adhesive film in sheet format may provide the most efficient productivity.  Typically heat-laminated onto a wafer first and followed by vacuum lamination of the wafer onto the carrier, AIT’s WPA thin film processing conditions and debonding techniques resemble the spin coating process used in WPA products.

AI Technology, Inc. (AIT) understands that different types of wafers, Si, GaAs, GaN, InP, glass, and sapphire are used in different applications and, depending on wafer processing conditions, demand highly specialized tools and equipment.  AIT is committed to working closely with our customers and equipment suppliers to satisfy customer needs.

By Paula Doe, SEMI

Emerging opportunities for advanced packaging solutions for heterogeneous integration include a lot more than logic, memory and sensors. There’s also the challenges of packaging integrated photonics, flexible electronics, and high-voltage, high-temperature wide-bandgap power devices. Speakers from the National Network for Manufacturing Innovation Institutes targeting these new growth markets will update the SEMICON West 2016 audience on their efforts to cut the time and cost of moving from R&D to volume production for U.S. companies by supporting development of key technologies, U.S.-based facilities for fabrication and packaging, and education of the workforce.

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Integrating silicon with optics

The new American Institute for Manufacturing Integrated Photonics (AIM Photonics) is ramping up its program to spur development of U.S. technology and manufacturing capability for integrated photonics, for next-generation high performance computing, telecommunications, and sensors. In the packaging space, first steps will be a university-industry effort to develop passive fiber-to-silicon assembly technology and automated test equipment, with a manufacturing facility targeted for 2017.

“We’re focusing on packaging, assembly and test since it accounts for most of the cost of integrated photonics,” says CEO Michael Liehr, who will update on the plans to facilitate U.S. manufacturing in this emerging sector in the Packaging Photonics session at SEMICON West on July 12.

Attaching an optical fiber of 120µm diameter to a waveguide of only several thousand angstroms remains a major challenge, typically requiring active alignment.  Volume production will need a passive alignment solution, which will require some combination of major improvement in precision of current placement tools (such as with image recognition) with some way to make the coupling more fault tolerant ─ such as by using an interposer to bridge the gap. Tool makers will need standard package interfaces to make common, not custom equipment. The institute will also work on the packaging issues of integrating the laser with the waveguides and other optical features on silicon.

“Key elements are also missing for test,” Liehr notes. “The in-line part is missing. No one has put together a commercially available system that includes the prober, the optical detection, and the coupler needed.”  The institute is putting together a university and industry team to develop solutions, and then will equip a facility to do the test, assembly and packaging of these photonic integrated circuits.

AIM Photonics also targets a Process Design Kit (PDK) design kit by the end of the year for its multi-project photonic wafers run in its front-end fab. Besides data center and telecommunications applications of integrated photonics, AIM Photonics is working with companies on phased arrays and optical sensors for healthcare and defense applications. The organization is a public-private venture, funded by the U.S. Department of Defense, the States of New York, Massachusetts, California, Arizona, and university and industry members.

Integrating silicon die into flexible, conformable electronics systems

Another emerging “packaging” opportunity is integrating silicon intelligence into  flexible, stretchable products. “People have been talking for decades now about a purely printed solution, but printed transistors do not have enough mobility for the needed performance, and in a switching application will burn out in about a day” notes Jason Marsh, Director of Technology at NextFlex, the Manufacturing Innovation Institute for Flexible, Hybrid Electronics, who will talk about this effort at the SEMICON program on flexible packaging July 14. “But there is real demand for flexible, conformable products for medical wearable and implantable devices and for IoT edge devices.”  The collaborative program aims to develop the manufacturing technology to enable these products, by integrating silicon die into flexible, stretchable environments.

This will require the development of new processes for bridging directly from ~100µm-scale printed electronic circuits to 50µm-scale PCB artwork to much finer die-level bond-pad pitch, eliminating the usual intervening steps ─ of wirebond/flip chip, package, interposer, circuit board, connector ─ all at low temperature and with good signal integrity. Potential approaches could include flip chip with an anisotropic conductor connection, or alternatively, printing the traces directly on bigger pond pads. The institute aims to develop the basic building blocks of the technology and put together a U.S. supply chain that companies can then use to develop and manufacture their own products. NextFlex is building a facility in San Jose for the technology, which members can use to develop prototypes and build their pilot products.

Building this new manufacturing supply chain means re-thinking the traditional food chain of circuit board, packaging and assembly. “We may need to do things in different order, with die attach to the substrate before circuitization, and may need big arrays on big substrates, with new process tools to handle them,” suggests Marsh. “Package and assembly suppliers will need to understand more of the full end-to-end process, with assembly companies understanding packaging, and packaging companies understanding interposers.” The project aims to help bring these suppliers together, and also to help develop the necessary technical expertise in the workforce in the U.S. “The goal is to accelerate the speed of development from some 5-6 years to 1-2 years,” says Marsh.

The program is funded by $75 million from the U.S. government, and $96 million from the City of San Jose, and other corporate, academic, and government partners.

Building a U.S. ecosystem for wide bandgap power semiconductor manufacturing

PowerAmerica, the Next Generation Power Electronics Manufacturing Innovation Institute, aims to build the U.S. ecosystem for manufacturing wide bandgap power semiconductors, by supporting R&D, production facilities, and workforce development to accelerate the adoption of these smaller, lighter and more energy efficient power systems, and to make it easier for new and small U.S. companies to develop products.

“It’s about driving down cost and validating the reliability of SiC and GaN for demanding power electronics applications. The physics are clear. Wide bandgap semiconductors can offer very high-power densities and higher performance with a lower cost bill of materials. We are rapidly approaching the tipping point where market demand and production volume will bring the price of wide bandgap devices down to match silicon in $/Amp,” says John Muth, PowerAmerica’s deputy director, who will update on the effort in the power packaging program at SEMICON West on July 12.

Taking full advantage of the physical properties of wide bandgap semiconductors for high performance will require highly optimized packages that can handle high voltages while minimizing inductance and efficiently remove heat, with more reliable materials for interconnections, die attach, and baseplate/substrates, and better cooling solutions. One result of the packaging projects to date are the low inductance, high performance power modules recently announced by Wolfspeed.

PowerAmerica activities across the supply chain range from the 6-inch SiC foundry at X-Fab in Lubbock, Texas, now being used by five members, to products under development by end users across in transportation, renewable energy, motor drives, data centers, and the power grid, at members such as ABB, Agile Switch, Atom Power, John Deere, Navitas, Lockheed-Martin, and Toshiba.

The institute has recently also started to invite unsolicited proposals that solve a technical problem to help grow and strengthen the supply chain or to accelerate adoption of SiC or GaN into new products. All projects have 1:1 cost sharing, and require a clear path to market. Other efforts include aggressive demonstrations of wide bandgap semiconductor performance by universities, industry-led road mapping activities, and curriculum development at member universities, and tutorials and short courses to bring industry engineers quickly up to speed in GaN and SiC technology.

The five-year $146 million program is funded by $70 million from DOE and another $76 million from cost matching from its members and the state of North Carolina.

To learn more about SEMICON West 2016, visit the Schedule-at-a-Glance and learn about the eight forums.

Correction: The first draft of this article stated in error that Jason Marsh’s talk would take place on July 12. Jason Marsh will speak on flexible packaging at SEMICON West on July 14.

Amkor Technology Inc., a provider of semiconductor packaging and test services, today announced it has received the Supplier of the Year award from Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated, for its performance in 2015. Qualcomm Technologies’ Supplier of the Year award recognizes a key supplier that demonstrates the highest on-time delivery, quality and customer service performance throughout the calendar year. Qualcomm Technologies recognized Amkor for its significant contributions in providing packaging and test support for premium-tier mobile communications products.

“We are honored to receive Qualcomm Technologies’ Supplier of the Year award,” said Steve Kelley, Amkor’s president and chief executive officer. “Amkor is fully committed to providing the advanced packaging and test services and superior customer experience that meet the stringent requirements set by Qualcomm Technologies. This award is recognition of the close collaboration between our two companies and the outstanding commitment shown by our teams worldwide.”

“Qualcomm Technologies congratulates Amkor on winning the 2015 Supplier of the Year award,” said Roawen Chen, senior vice president of global operations, Qualcomm Technologies, Inc. “This award acknowledges Amkor’s performance improvements in all major areas, including on-time delivery, quality, customer service and strategic business support. Amkor is an important supplier and was instrumental to our success in the premium tier of the mobile communications ecosystem. We look forward to Amkor becoming a more important supplier in our supply chain strategy.”