Category Archives: Materials and Equipment

Amkor Technology, Inc. today announced plans to expand its assembly and test factory located in China’s Shanghai Waigaoqiao Free Trade Zone. With this project, Amkor expects to increase its manufacturing facilities in China by 45 percent to nearly 60,000 square meters of cleanroom space.

“Demand for assembly and test services is booming in China, particularly for advanced products employing wafer-level, die stacking and package stacking technology,” said Steve Kelley, Amkor’s president and chief executive officer. “Our Shanghai operation is Amkor’s second-largest factory by revenue, and offers the most advanced OSAT technologies in China for both local and international customers. This investment reflects the long term strength of our mobile communications business, and the increasingly important role of the Chinese market in the global semiconductor supply chain.”

Amkor plans to invest around $60 million for construction of the new facilities, which is scheduled to be completed by the summer of 2016.

Amkor is a provider of semiconductor packaging and test services to semiconductor companies and electronics OEMs.

By Pete Singer, Editor-in-Chief

As packaging technology continues to advance to maintain the ever-increasing demand for faster, higher capacity, and lower power devices, wafer bumping plays an important role in enabling these capabilities. Bumps can be placed almost anywhere on the die, giving chip makers the ability to put more and more I/O points on an individual die compared to previous methods.

Inspecting bumps is becoming more challenging. The number of I/O points continues to increase. “As chip makers and OSATs need to put more bumps on an individual die, the geometries are being driven smaller and smaller just like transistor technology,” notes Mike Goodrich, vice president and general manager of Rudolph’s Inspection Business Unit.

Materials are also changing. The industry is experiencing a transition from solder bump to Cu pillar, just as it moved from an evaporated bump to a plated process, according to a new report from TechSearch International. While the transition to copper pillar is underway, SnAg remains the Pb-free solution of choice.

Laser triangulation technology in conjunction with specially designed optics and analytical algorithms is used on bump inspection systems to provide high-quality measurements of micro-bump critical dimensions at full production speeds.

“Manufacturers need to make sure all the bumps are at the same height. If you have one bump that’s too tall or too short, you start to run into connection issues that result in poor yield or a failed device,” says Goodrich. “Our systems measure bump height to make sure coplanarity is uniform across an individual die,” he added, referring to Rudolph Technologies’ Wafer Scanner Inspection Series. Combined with Discover Enterprise, Rudolph Technologies’ yield and defect management software, the tools provide yield management for 3D/2D bump and RDL metrology, bump and RDL defect detection, and macro defect inspection throughout post-fab processes.

The tools can be used in either a characterization mode, where the dimensions of every bump on every wafer is analyzed, or in a high volume manufacturing mode, where the norm is to do a sampling scenario to monitor for process excursions.

One of the biggest challenges is handling vast amounts of data. “An individual die can have several thousand bumps, which results in millions of bumps on a wafer,” Goodrich said. “The amount of data generated becomes pretty unwieldy, really fast. Being able to manage that data and turn it into information and make decisions is extremely important. We are working with customers to implement that into their process flow.”

Utilizing laser triangulation technology, the Wafer Scanner enables 3D inspection of bumps and RDL of different sizes at high speed. An optional ultra high resolution sensor enables inspection of micro bumps and RDL heights as low as 1µm. Film frame handling capability allows inspection of thin and diced wafers and features a quick-change wafer platform to switch between film frame and whole wafers.

Inspection Smooths a Bumpy Road photo

By Pete Singer, Editor-in-Chief

The expansion of fan-out is finally coming, says Rich Rogoff, Vice President and General Manager, Lithography Systems Group at Rudolph Technologies.

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging.

It was originally introduced by Infineon in the fall of 2007. Called eWLB, or embedded wafer-level ball grid array technology, it enables all operations to be performed highly parallel at wafer level. In August of 2008, STMicroelectronics, STATS ChipPAC, and Infineon signed an agreement to jointly develop the next-generation eWLB, based on Infineon’s first-generation technology.

Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.

STATS ChipPAC’s eWLB high volume manufacturing process, for example, today includes automated wafer reconstitution (including wafer-level molding), redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 200mm and 300mm diameters can be supported.

According to a recent report from Yole Développement, the fan-out WLP (FOWLP) market will reach almost $200M in 2015, with 30% CAGR in the coming years. Yole analysts say FOWLP started volume commercialization in 2009/2010 and started promisingly, with an initial push by Intel Mobile. However, it was limited to a narrow range of applications, essentially single die packages for cell phone baseband chips. In 2012 big fabless wireless/mobile players started slowly volume production after qualifying the technology.

It faced strong competition from other packaging technologies, such as wafer-level chip scale packaging (WLCSP) in 2013/2014. Intel Mobile also backed off from the technology, and the main manufacturers reduced their prices in 2014, creating a transition phase with low market growth.

Strong growth is now expected, hoped in part by the arrival of 2nd generation FOWLP. “Benefiting from the delay in introducing 3D through-silicon via (TSV) architectures, FOWLP is currently seen as the best fit for the highly demanding mobile/wireless market and is attractive for other markets focusing on high performance and small size”, explains Jérôme Azemar, Technology & Market Analyst, Advanced Packaging & Manufacturing, Yole Développement.

Rudolph’s Rogoff believes it will be implemented in a wafer form for the next year or two, but will ultimately transition to a panel-based approach. “The big question for the industry is are they going to move to panels?” Rogoff asked. “From a lithography perspective, the tools are ready today. As the demand goes up, there will be a push also for a switch,” he said. “Development of panels has already started and will continue to increase in activity over the next year.”

In an article in Solid State Technology published in 2014, titled “A square peg in a round hole: The economics of panel-based lithography for advanced packaging,” Rogoff said moving from round wafers to rectangular panels (“panel-ization”) saves corner space, delivering a roughly 10% improvement in surface utilization. The larger size of the substrate and the improved fit between the mask and substrate reduce the transfer overhead by a factor of 5. The potential reduction in throughput resulting from an increase in the number of alignment points is more than offset by the improvements in throughput. Compared to a 1X stepper on wafers, panel-based processes can reduce lithography cost per die by as much as 40%.

One of the advantage of Rudolph Technologies’ JetStep Panel System (JetStep S3500) is that it can handle such rectangular panels. Both the panel and wafer 2X reduction steppers offer many advantages — based in part on Azores’ 6700 platform which was developed for LCDs — including the largest printable field-of-view, programmable aperture blades and large on-tool reticle library, large depth-of-focus along with autofocus to accommodate 3D structures in advanced packaging, very large working distance, and warped substrate handling (+/- 6mm). The wafer system (JetStep W2300) features programmable wafer edge protection, enabling a variable edge exclusion zone of 0.5-5 mm. The systems also feature a large (17mm) working distance between the lens and the substrate, which helps avoid a common maintenance issue on 1X systems.

Rogoff said the ability to handle warped wafers is increasingly important. “We’ll always be putting the best focus point in the middle of our depth of focus range. If there’s any variation due to substrate warp, we can go up a little and down a little and we’re still going to be in focus,” he said.

The large working distance helps eliminate problems with thick resists, which can outgas and potentially contaminate the lens. “We’re so far away — and we also have some purging in the area – we don’t have that issue. The less you have to take the machine down to clean it, the better,” he said.

When it comes to fan-out, the challenge is being able to manage the overlay performance over a large field area. “Our competitors like to say it can’t be done, yet we prove it can,” Rogoff said. “The larger the field is, the more die you get in it, so the more variations you’re likely to see. With our ability to correct for intrafield parameters, we can extract out that variation so what’s left is just random noise.”

If the random noise gets too high, another solution Rudolph can provide is a combination of stepper modeling capability with inspection. “You can measure the die placement on a high speed inspection tool, throw that data into the modeling software and spit out the stepping model for the stepper,” Rogoff explained. “This is something we’re continuing to develop. The first round is available and as the fan-out technology gets more complex, we’re continuing to expand on that.”

By Jeff Dorsch, Contributing Editor

The used and refurbished semiconductor equipment market can be a hazardous business for buyers. The watchword always is: Caveat emptor – let the buyer beware.

There are many reputable companies in the used equipment business, of course. Intel, Texas Instruments, and other big chipmakers put their surplus production equipment on the market, typically on an “as-is” basis.

Some used-equipment vendors and brokers also offer their wares as they are, without any guarantees or warranties. The chip-making gear may be faulty; it could lack a software license from the original equipment manufacturer, which has occasionally been a legal issue.

Many purveyors of used equipment are also involved in refurbishing pre-owned equipment, and some even develop their own equipment, given their experience in buying, maintaining, updating, and selling equipment.

“It’s an interesting year. The industry has been very busy,” says Byron Exarcos, CEO of ClassOne Equipment, which is based in Atlanta and has operations around the world in key markets. “There definitely is a lack of supply, versus demand. It has driven pricing up.

”It’s become very difficult to find equipment, especially 200-millimeter equipment,” he adds. “There’s a very tight supply and high demand, which invariably increases prices.”

Dave Pawlak, ClassOne’s vice president of purchasing, says the supply-and-demand situation has lately improved. The market is seeing “a slowdown” after a torrid period of activity, he adds. “Tools are becoming available. We’re starting to see a turn. The prices are coming down,” Pawlak observes.

Driving the demand for 200mm tools are manufacturers of microelectromechanical system devices and sensors, according to Exarcos. Light-emitting diodes are typically manufactured on 150mm wafer fabrication lines.

“They may have been using 3-inch, 4-inch tools,” he says of these manufacturers. “Eight-inch tools – they’re the leading edge.”

While Intel and Samsung Electronics are fabricating their most advanced chips on 300mm fab lines, those integrated device manufacturers (both of who are in the foundry business) are “keeping their 200mm tools,” Exarcos says. “They’re getting busy with them.”

The ClassOne Group now has an operation in Kalispell, Montana, which was the home of Semitool, an equipment manufacturer acquired in 2009 by Applied Materials. ClassOne Technology, founded in 2013, makes new wet-chemical process tools, including electroplating systems, for companies making LEDs, MEMS, photonics, power devices, radio-frequency devices, and other components. These companies may turn out 5,000 to 10,000 wafer starts per month, according to Exarcos, not on the level of volume production for the big IDMs.

In February, ClassOne Technology announced the acquisition of two product lines, a spin-rinse-dryer and a spray solvent tool, from Microprocess Technologies. Those products became the company’s Trident SRD and Trident SST lines.

Exarcos concludes, “It is critical to work with the right company.”

The related field of spare parts for semiconductor equipment was rocked in the 1990s by the case of Semiconductor Spares, Inc., which conspired with insiders at Applied Materials, Lam Research, and Varian Associates (the semiconductor equipment business of which was bought by Applied in 2011) to steal drawings of parts, enabling SSI to undercut those vendors on pricing. David W. Biehl, the company’s owner and president, pleaded guilty to a variety of charges in the case and was sentenced in U.S. District Court to 31 months in prison and ordered to pay $100,000 in restitution.

Once more – Caveat emptor.

IRT Nanoelec, an R&D consortium focused on Information and Communication Technologies (ICT) using micro- and nanoelectronics, and its partners CEA-Leti, STMicroelectronics and Mentor Graphics have realized an innovative 3D chip called “3DNoC” to demonstrate the use of 3D stacking technology in scalable, complex digital systems-on-chip (SoCs).

The 3DNoC chip is based on a 2D die that can be used in a stand-alone applicative mode, and also in a 3D stack with several dice, to multiply the processing performance of the system. The project’s complete demonstration platform shows both the simulated and measured thermal effects in the 3D chip using a new Mentor Graphics Calibre thermal-analysis prototype.

“The technology developed for this realization can be easily used and transferred to address mixed-technology applications, such as imagers and RF transceivers, or complex digital processing, such as high-performance computing and programmable devices,” said Severine Cheramy, IRT 3D program director. “In parallel with these results, we are working on developments that address more fine-pitch 3D technology than those used in the 3DNoC demonstrator and solutions for thermal dissipation, temporary bonding and stress issues.”

3D-stacking technology is a promising solution to improve both performance and density integration without requiring transition to the next technology node. It allows the integration of different technologies and simplifies the use of small-sized dice to improve modularity and increase yield. In a complex and traditional 2D SoC, the technology node is defined by the most complex function, and reuse methodology is done at the IP level. A 3D system blends several technologies and reuse methodology can be performed at the elementary die, the “chiplet.”

The 3DNoC chip was defined and designed by Leti, with the direct support of STMicroelectronics, using a specific add-on 3D design kit and a set of 3D sign-off verification tools provided by Mentor Graphics. CMOS technology, 3D technology and packaging were realized by ST and Leti, with a “via-middle option” in 65nm CMOS technology. The test and demonstration platform is a joint development among the three partners.

Proving the viability of 3D stacking

IRT Nanoelec provides a multi-skill environment – including technology development, innovative processing architecture, and specific design tools in a global system- methodology approach – for the development of pioneer 3D demonstrators to prove the viability of 3D stacking in a wide range of applications. Although the 3DNoC chip addresses baseband processing, all technology and design bricks are reusable across a range of other applications.

3DNoC is the first worldwide realization of a 3D-scalable processor chip. It goes beyond prior state-of-the-art as a 3D asynchronous communication network that can exploit the maximum performance of vertical links and offer an aggregate 3D network link bandwidth of 450 MByte/s. The strategy, which is based on increasing the performance of a system by stacking several identical dice in the same footprint, is very similar to HMC or HBM memories. In the case of DRAM, byte capacity is multiplied by the number of elementary dice stacked; the 3DNoC circuit multiplies processing performance. 

The Technology

Several identical 65nm CMOS digital dice can be bonded using a face-to-back technology to build a stack of processing elements, using 10µm-diameter through-silicon via (TSV) and 20µm-diameter µpillars and µbumps. In the IRT Nanoelec demonstration, two dice are stacked.

At the elementary die level, provisions were made to allow the stacking of up to four dice: the number of power connections is dimensioned in this way, while the number of signals is constant regardless of the number of stacked dice. Area occupied by the 2,000 TSVs represents about 1 percent of the whole die area (72 mm2) and wafers are thinned to 80µm for TSV revelation at the backside.

3DNoC is mounted in a 581-ball, 0.3mm-pitch BGA package using a stacking-last approach, i.e. the bottom die is bonded on the substrate and after the top one on the bottom.

Targeting digital baseband processing

The digital modules embedded in 3DNoC are computing-intensive IPs, processor cores and programmable DMA engines connected to the NoC routers using a dedicated interface compatible with a packet-switching mechanism.

The global architecture was partitioned in a scalable way to address several modes, depending on the number of antennae used for transmitting-and-receiving levels. The modular elementary die was sized to fit the processing performance required to support the single antenna mode and, by stacking two or four dice, more complex multiple antenna modes are supported. As an example, the 3DNoC chip developed in this project can support up to two antennae for both TX and RX.

Network on Chip (NoC)

For many years, network-on-chip (NoC) has played a key role in 2D complex SoCs, thanks to its ability to efficiently manage data exchanges between many IPs. The fact that packet switching communication is well decoupled to computing IPs makes the extension of the interconnection capabilities to the third dimension easy and natural. The elementary die of the 3DNoC integrates four 3D routers to ensure vertical communication.

Redundancy and fault-tolerance are used in the 3DNoC circuit at both communication and processing levels. Using asynchronous logic for router implementation allows implementing robust 3D communication interfaces without any delay assumption, and makes dynamic voltage and frequency scaling (DVFS) for power optimization easier, relative to processing requirements and thermal constraints. Specific analysis and sizing tools developed by Mentor Graphics for power and thermal aspects were very helpful to architects in the 3D floor plan of the 3DNoC chip. More specifically, the Calibre 3DSTACK tool has been used for final sign-off verification of the 3D assembly of the two dice.

Several modules have been designed to ensure 3D signal integrity between the different tiers: micro-buffers, ESD protection, 3D link redundancy and data coding. A complete design-for-test methodology has been set up to perform a hierarchical test of each module, tier and stack before and after stacking based on the Mentor Graphics Tessent test tool suite including test pattern generation

SEMI this week announced the SEMICON West 2015 test and packaging program agendas. In addition to over 650 exhibitors, SEMICON West will feature more than 180 total hours of programs — including free technical, applications and business events as well as exclusive programs. Discounted registration for SEMICON West 2015 ends June 5.

Exclusive programs include the three-day Semiconductor Technology Symposium (STS), a comprehensive technology and business conference, addressing the key issues driving the future of semiconductor manufacturing and markets. This year, STS programs on Packaging and Test include:

  • The Very Big Picture, the Future of Semiconductor Packaging Technology (July 14) — with speakers from 3MTS, AMD, Oracle, and more; plus a panel discussion on “Value vs. Cost”
  • Packaging: Digital Health and Semiconductor Technology (July 14) — with speakers from Cisco, Medicustek, GE Global Research Center, Medtronic, and more
  • Test Vision 2020: The Road to the Future of Test  (July 15-16) — with keynote from Kaivan Karimi, VP at Atmel, Inc. plus speakers Brad Shaffer of IHS and Thomas Burger of AMS. Sessions include: Wireless Test in the IoT Era; Unique Test Flows for New Cost Challenges; and Advanced Packaging, Advanced Test Challenges. Panel sessions will discuss “How Secure is your Test Data, Really?” and “What Does RF Test Look like in Five Years? Future Solutions for Lowering the Cost of Transceiver Tests”

In addition, two packaging and test sessions will be offered as part of the TechXPOT program on the exhibition floor (free to exposition attendees):

  • Automating Semiconductor Test Productivity (July 14) — a panel of experts from the semiconductor test community, including representatives from TI, STMicro and ASE,  will discuss challenges and opportunities for automating test operations to maximize productivity
  • Auto Utopia: Gearing up Semiconductor to Turns Dreams to Reality (July 15) — with speakers from ASE, Gartner, PRIME Research, ASE Singapore, and more (session partner: MEPTEC)

Other key segments at SEMICON West 2015 include:

  • Global Business Outlook
  • Semiconductor Fabrication, Equipment and Materials
  • The Internet of Things
  • MEMS
  • Flexible Hybrid Electronics
  • Sustainable Manufacturing
  • Next-Generation Products

SEMICON West (www.semiconwest.org) continues to feature a full set of complimentary programs, including keynote addresses, executive panels, technical and business sessions.  The Tuesday Keynote Panel features imec, Qualcomm, and Stanford University tackling the issue of “Scaling the Walls of sub-14nm Manufacturing.” Doug Davis, senior VP and GM, IoT Group at Intel, will present the Wednesday Keynote.

To view a SEMICON West 2015 “schedule at-a-glance,” click here.  Discounted pricing is available through June 5.  Early-bird pricing for the Semiconductor Technology Symposium (STS), Test Vision 2020, and Sustainable Manufacturing Forum (SMF) also applies through June 5.  Register now to save: www.semiconwest.org/Participate/RegisterNow

NXP Semiconductors and Stora Enso have entered into joint development of intelligent packaging solutions. The development will focus on integrating RFID (Radio frequency identification) into packages for consumer engagement and supply chain purposes. The collaboration will also focus on brand protection and the development of tamper evidence applications. These solutions will benefit both consumers and brand owners.

By using NXP RFID technology such as near field communication (NFC) and ultra-high frequency (UHF), Stora Enso smart packages can be easily tracked and traced through the entire supply chain providing full end-to-end transparency. The integrated technology is also able to detect if the smart package has been tampered with en route to the consumer and, once in the hands of the consumer, can provide additional information and interaction through (the tap of) an NFC-enabled smart phone. This visibility and insight is critical for brands and major manufacturers to ensure their products are being shipped and handled correctly. For consumers the benefits are two-fold; the smart packaging can verify the authenticity of the product and also provide care, usage and other important information via the NFC-enabled tag.

“The co-operation with NXP offers substantial business opportunities for Stora Enso. We have already worked on several concept cases with customers and partners within intelligent packaging. The co-operation with NXP will enable us to bring this development closer to market and provide faster scalability in intelligent paper and board solutions,” says Karl-Henrik Sundström, CEO, Stora Enso.

“Our RFID technology in combination with Stora Enso’s packaging solutions creates additional value to both consumers and brand owners by providing information and insights along the complete supply chain,” said Ruediger Stroh EVP & GM Security & Connectivity, NXP Semiconductors. “The ability of the RFID tag to detect when a package has been compromised and also provide additional product information via NFC truly enables a unique, smart, engaging brand experience and is another example of how security can be broadly implemented to protect our everyday lives.”

Semiconductor test equipment supplier Advantest Corporation announced today that it has developed a technology utilizing short-pulse terahertz waves for analysis of electrical circuits. The technology has 2 major applications – analysis of the transmission characteristics (S parameters) of devices using the sub-terahertz band (100GHz~1THz), and characterization and location of failures in chip circuits (TDT/TDR). The new technology overcomes the technical obstacles and prohibitive cost of existing technologies, and will contribute significantly to the development and wider adoption of these leading-edge devices.

Sub-terahertz transmission characteristics analysis technology

The popularity of smartphones and other mobile devices has driven enormous increases in wireless communications traffic, which now threatens to overwhelm the capacity of currently assigned frequencies. Hence, worldwide R&D efforts have begun to focus on the sub-terahertz band, a higher frequency range which has not been used for wireless communications to date.

In high-frequency device development, it is crucial to evaluate the frequency characteristics of the overall system, including active device gain and input and output impedance, as well as the board and connectors. Part of this process is measurement of the reflection and transmission characteristics of the amplitude and phase of signals emitted, known as S-parameters or scattering parameters. However, existing network analyzers can only measure frequency ranges up to 100GHz wide at one time, so when the signal characteristics of broader ranges must be evaluated, engineers have to repeatedly change the configuration of their equipment and measure again. This causes extra work, longer measurement times, and discontinuities in measured data. Measurement costs also rise proportionately to these drawbacks.

Advantest’s new technology promises to reduce these burdens significantly. It employs femtosecond optical pulsed laser as a signal source, enabling one-pass measurement of S-parameters up to 1.5THz with a broadband optical/electrical switching probe. The benefits of these efficiency gains will accrue to users in terms of time, labor, and cost savings.

High spatial resolution chip wiring quality analysis technology

Although continued shrinks of semiconductor circuits have facilitated generations of smaller, faster consumer electronics, Moore’s law is in danger of hitting a technological wall. To circumvent the physical limits of miniaturization, chipmakers are developing 3D semiconductors with multiple layers of circuits in a single package. However, wiring failure analysis is a major challenge in 3D chip development. With multiple boards stacked on top of each other, it is difficult to identify where wiring failures (open circuits, short-circuits, impedance mismatching) have occurred with X-ray inspection and other existing technologies. Generally, oscilloscope TDR (time domain reflectometry) and/or TDT (time domain transmissometry) is used to pinpoint these failures, but at these tiny geometries, extremely high spatial resolution is a must.

Because Advantest’s new technology uses a femtosecond optical pulsed laser as a signal source, it achieves superior spatial resolution of less than 5μm and a maximum measurement range of 300mm. With a successful track record of usage in the company’s terahertz spectroscopic and imaging systems, Advantest’s femtosecond optical pulsed laser boasts extremely high resolution. Moreover, the new technology provides a mapping function which can pinpoint the location of wiring failures on the device’s CAD data, making it an optimal tool for finding flaws in extremely complex, high-density circuits.

Advantest is planning to commercialize the new technology within its fiscal year 2015 (by the end of March, 2016).

Semiconductor Research Corporation (SRC) announced today that Ken Hansen has been appointed SRC’s new President and Chief Executive Officer (CEO), effective June 1.

Hansen’s professional experience includes serving as Vice President and Chief Technology Officer (CTO) at Freescale Semiconductor since 2009. Hansen replaces retiring SRC President and CEO Larry Sumney who guided the organization for more than 30 years since its inception in 1982. SRC’s many accolades over the years include being the recipient of the National Medal of Technology in 2007.

“SRC under Larry Sumney’s leadership has made an indelible impact on the advancement of technology during the past three decades, and we congratulate Larry on his retirement and salute him for his contributions to the semiconductor industry,” said Mike Mayberry, Intel Corporate Vice President and Director of Components Research who is SRC Board Chairman. “We also welcome Ken Hansen to his new role guiding SRC, and we look forward to Ken’s leadership helping SRC reach new heights in an era where basic research and development is as critical as ever.”

Prior to his CTO role at Freescale, Hansen led research and development teams for more than 30 years in multiple senior technology and management positions at Freescale and Motorola. Hansen holds Bachelor and Master of Science degrees in Electrical Engineering from the University of Illinois where he has been recognized as an ECE (Department of Electrical and Computer Engineering) Distinguished Alumni.

In his new role at SRC, Hansen intends to build on the consortium’s mission of driving focused industry research to both advance state-of-the-art technology and continue to create a pipeline of qualified professionals who will serve as next-generation leaders for the industry.

“SRC also has an opportunity to strengthen its core by recruiting new members to gain more leverage to fund industry wide solutions for some of the challenging technology roadblocks that are ahead of us,” said Hansen.

“The model that SRC has developed is unmatched in the industry and has proven to be extremely significant. The industry would not be where it is today without the contributions of SRC under the leadership and vision of Larry Sumney,” Hansen continued.

Meanwhile, Sumney’s decorated career began in 1962 at the Naval Research Laboratory. He later directed various other research programs at Naval Electronics Systems Command and the Office of the Undersecretary of Defense — including the Department of Defense’s major technology initiative, Very High Speed ICs (VHSIC) —before agreeing to lead SRC following its formation by the Semiconductor Industry Association.

Under his leadership, SRC has also formed wholly owned subsidiaries managing the Nanoelectronics Research Initiative (NRI), the Semiconductor Technology Advanced Research network (STARnet) and the SRC Education Alliance, among other programs. Sumney received a Bachelor of Physics from Washington and Jefferson (W&J) College, which recognized him with the 2012 Alumni Achievement Award, and a Master of Engineering Administration from George Washington University.

“I have enjoyed a front row seat in the development of today’s technology-based economy and advancement of humanity through the semiconductor industry,” said Sumney. “I am completely confident that SRC is well positioned and will continue to flourish, to seed breakthrough innovation and help provide the people and ideas to keep the U.S. semiconductor industry competitive and prosperous in years to come.”

Additional industry leaders with strong ties to SRC commended Sumney for his service over the years while supporting Hansen’s appointment.

“Over more than 30 years, Larry Sumney’s visionary leadership of SRC has steered one of the world’s most transformative industries through times of tremendous growth and innovation,” said John Kelly, Senior Vice President, Solutions Portfolio and Research for IBM.  “I’ll personally miss working with Larry, but also have tremendous respect for and confidence in Ken Hansen, and we look forward to collaborating with him to drive the next generation of research in this vital industry.”

“Larry’s leadership and vision are key reasons why SRC’s research has played a fundamental role behind many of the most significant semiconductor innovations of the last three decades,” said Lisa Su, AMD president and CEO and a former SRC student. “Ken’s broad industry experience makes him ideally suited to lead the next phase of the SRC, as the organization continues to expand its capabilities and provide the basic research and development foundation needed to further accelerate innovation across the industry.”

Microchip Technology Incorporated, a provider of microcontroller, mixed-signal, analog and Flash-IP solutions, and Micrel, Incorporated today announced that Microchip has signed a definitive agreement to acquire Micrel for $14.00 per share.  Micrel shareholders may elect to receive the purchase price in either cash or shares of Microchip common stock.  The acquisition price represents a total equity value of about $839 million, and a total enterprise value of about $744 million, after excluding Micrel’s cash and investments on its balance sheet of approximately $95 million.

“We are pleased to have Micrel become part of the Microchip team. Micrel’s portfolio of Linear and Power Management products, LAN solutions and Timing and Communications products, as well as their strong position in the Industrial, Automotive and Communications markets, complement many of Microchip’s initiatives in these areas.”

“We believe that this acquisition provides the best vehicle for us to realize significant value for Micrel’s shareholders and is a fantastic outcome for our employees and customers, as well as the opportunity to scale up to the much stronger sales and manufacturing platforms of Microchip,” said Ray Zinn, President and CEO of Micrel.

Concurrent with this announcement, Microchip announced that its Board of Directors has authorized an increase in the existing share repurchase program to 20.0 million shares of common stock from the approximately 2.5 million shares remaining under the prior authorization.  Under this program, in the next several months, Microchip intends to repurchase the approximate number of shares it issues in the Micrel acquisition, which is expected to result in the transaction having the accretive effects of a cash transaction from a financial perspective.  The acquisition is expected to be mildly dilutive to Microchip’s non GAAP earnings per share immediately after the close, but is expected to be accretive in the first full quarter after completion of the repurchase of the number of shares issued in the transaction.

As previously announced by Micrel, the Micrel Board of Directors created a Transaction Committee entirely comprised of independent directors on January 20, 2015 to consider a range of strategic alternatives, including a potential sale of Micrel. The process leading up to the merger agreement with Microchip was overseen by the Transaction Committee which unanimously recommended the approval of the merger agreement to Micrel’s Board of Directors.

The acquisition has been unanimously approved by the Boards of Directors of each company and is expected to close early in the third quarter of calendar 2015.

All of Micrel’s directors and certain executive officers have signed voting agreements with Microchip under which they must vote in favor of the merger.