Category Archives: Materials and Equipment

Interconnecting transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, are where the future limitations in performance, power, latency and cost reside.

BY BILL CHEN, ASE US, Sunnyvale, CA; BILL BOTTOMS, 3MT Solutions, Santa Clara, CA, DAVE ARMSTRONG, Advantest, Fort Collins, CO; and ATSUNOBU ISOBAYASHI, Toshiba Kangawa, Japan.

Heterogeneous Integration refers to the integration of separately manufactured components into a higher level assembly that in the aggregate provides enhanced functionality and improved operating characteristics.

In this definition components should be taken to mean any unit whether individual die, MEMS device, passive component and assembled package or sub‐system that are integrated into a single package. The operating characteristics should also be taken in its broadest meaning including characteristics such as system level cost-of-ownership.

The mission of the ITRS Heterogeneous Integration Focus Team is to provide guidance to industry, academia and government to identify key technical challenges with sufficient lead time that they do not become roadblocks preventing the continued progress in electronics that is essential to the future growth of the industry and the realization of the promise of continued positive impact on mankind. The approach is to identify the require- ments for heterogeneous integration in the electronics industry through 2030, determine the difficult challenges that must be overcome to meet these requirements and, where possible, identify potential solutions.

Background

The environment is rapidly changing and will require revolutionary changes after 50 years where the change was largely evolutionary. The major factors driving the need for change are:

  • We are approaching the end of Moore’s Law scaling.
  • The emergence of 2.5D and 3D integration techniques
  • The emerging world of Internet of Everything will cause explosive growth in the need for connectivity.
  • Mobile devices such as smartphones and tablets are growing rapidly in number and in data communications requirements, driving explosive growth in capacity of the global communications network.
  • Migration of data, logic and applications to the cloud drives demand for reduction in latency while accommodating this network capacity growth.

Satisfying these emerging demands cannot be accomplished with the current electronics technology and these demands are driving a new and different integration approach. The requirements for power, latency, bandwidth/bandwidth density and cost can only be accomplished by a revolutionary change in the global communications network, with all the components in that network and everything attached to it. Ensuring the reliability of this “future network” in an environment where transistors wear out, will also require innovation in how we design and test the network and its components.

The transistors ‘power consumption in today’s network account for less than 10 percent of total power, total latency and total cost. It is the interconnection of these transistors and other components in the IC, in the package, on the printed circuit board and at the system and global network level, where the future limitations in performance, power, latency and cost reside. Overcoming these limitations will require heterogeneous integration of different materials, different devices (logic, memory, sensors, RF, analog, etc.) and different technologies (electronics, photonics, plasmonics, MEMS and sensors). New materials, manufacturing equipment and processes will be required to accomplish this integration and overcome these limitations.

Difficult challenges

The top‐level difficult challenges will be the reduction of power per function, cost per function and latency while continuing the improvements in performance, physical density and reliability. Historically, scaling of transistors has been the primary contributor to meeting required system level improvements. Heterogeneous integration must provide solutions to the non‐transistor infrastructure that replace the shortfall from the historical pace of progress we have enjoyed from scaling CMOS. Packaging and test have found it difficult to scale their performance or cost per function to keep pace with transistors and many difficult challenges must be met to maintain the historical pace of progress.

In order to identify the difficult challenges we have selected seven application areas that will drive critical future requirements to focus our work. These areas are:

  • Mobile products
  • Big data systems and interconnect
  • The cloud
  • Biomedical products
  • Green technology
  • Internet of Things
  • Automotive components and systems

An initial list of difficult challenges for Heterogeneous Integration for these application areas is presented in three categories; (1) on‐chip interconnect, (2) assembly and packaging and (3) test. These are analyzed in line with the roadmapping process and will be used to define the top 10 challenges that have the potential to be “show stoppers” for the seven application areas identified above.

On-chip interconnect difficult challenges

The continued decrease in feature size, increase in transistor count and expansion into 3D structures are presenting many difficult challenges. While challenges in continuous scaling are discussed in the “More Moore” section, the difficult challenges of interconnect technology in devices with 3D structures are listed here. Note that this assumes a 3D structure with TSV, optical interconnects and passive devices in interposer substrates.

ESD (Electrostatic Discharge): Plasma damage on transistors by TSV etching especially on via last scheme. Low damage TSV etch process and the layout of protection diodes are the key factors.

CPI (Chip Package Interaction) Reliability [Process]: Low fracture toughness of ULK (Ultra Low‐k) dielectrics cause failures such as delamination. Material development of ULK with higher modulus and hardness are the key factors.

CPI (Chip Package Interaction) Reliability [Design]: A layout optimization is a key for the device using Cu/ULK structure.

Stress management in TSV [Via Last]: Yield and reliability in Mx layers where TSV land is a concern.

Stress management in TSV [Via Middle]: Stress deformation by copper extrusion in TSV and a KOZ (Keep Out Zone) in transistor layout are the issues.

Thermal management [Hot Spot]: Heat dissipation in TSV is an issue. An effective homogenization of hot spot heat either by material or layout optimization are the key factors.

Thermal management [Warpage]: Thermal expansion management of each interconnect layer is necessary in thinner Si substrate with TSV.

Passive Device Integration [Performance]: Higher Q, in other words, thicker metal lines and lower tan dielectrics is a key for achieving lower power and lower noise circuits.

Passive Device Integration [Cost]: Higher film and higher are required for higher density and lower footprint layout.

Implementation of Optical Interconnects: Optical interconnects for signaling, clock distribution, and I/O requires development of a number of optical components such as light sources, photo detectors, modulators, filters and waveguides. On‐chip optical interconnects replacing global inter- connects requires the breakthrough to overcome the cost issue.

Assembly and packaging difficult challenges

Today assembly and packaging are often the limiting factors in performance, size, latency, power and cost. Although much progress has been made with the introduction of new packaging architectures and processes, with innovations in wafer level packaging and system in package for example, a significantly higher rate of progress is required. The complexity of the challenge is increasing due to unique demands of heterogeneous integration. This includes integration of diverse materials and diverse circuit fabric types into a single SiP architecture and the use of the 3rd dimension.

Difficult packaging challenges by circuit fabric

  • Logic: Unpredictable hot spot locations, high thermal density, high frequency, unpredictable work load, limited by data bandwidth and data bottle‐necks. High bandwidth data access will require new solutions to physical density of bandwidth.
  • Memory: Thermal density depends on memory type and thermal density differences drive changes in package architecture and materials, thinned device fault models, test & redundancy repair techniques. Packaging must support low latency, high bandwidth large (>1Tb) memory in a hierar- chical architecture in a single package and/or SiP).
  • MEMS: There is a virtually unlimited set of requirements. Issues to be addressed include hermetic vs. non‐hermetic, variable functional density, plumbing, stress control, and cost effective test solutions.
  • Photonics: Extreme sensitivity to thermal changes, O to E and E to O, optical signal connections, new materials, new assembly techniques, new alignment and test techniques.
  • Plasmonics: Requirements are yet to be determined, but they will be different from other circuit type. Issues to be addressed include acousto‐ magneto effects and nonlinear plasmonics.
  • Microfluidics: Sealing, thermal management and flow control must be incorporated into the package.

Most if not all of these will require new materials and new equipment for assembly and test to meet the 15 year Roadmap requirements.

Difficult packaging challenges by material

Semiconductors: Today the vast majority of semiconductor components are silicon based. In the future both organic and compound semiconductors will be used with a variety of thermal, mechanical and electrical properties; each with unique mechanical, thermal and electrical requirements.

Conductors: Cu has replaced Au and Al in many applications but this is not good enough for future needs. Metal matrix composites and ballistic conductors will be required. Inserting some of these new materials will require new assembly, contacting and joining techniques.

Dielectrics: New high k dielectrics and low k dielectrics will be required. Fracture toughness and interfacial adhesion will be the key parameters. Packaging must provide protection for these fragile materials.

Molding compound: Improved thermal conductivity, thinner layers and lower CTE are key requirements.

Adhesives: Die attach materials, flexible conductors, residue free materials needed o not exist today.

Biocompatible materials: For applications in the healthcare and medical domain (e.g. body patches, implants, smart catheters, electroceuticals), semiconductor‐based devices have to be biocompatible. This involves the integration of new (flexible) materials to comply with specific packaging (form factor) requirements.

Difficult challenges for the testing of heterogeneous devices

The difficulties in testing heterogeneous devices can be broadly separated into three categories: Test Quality Assurance, Test Infrastructure, and Test Design Collaboration.

Test quality assurance needs to comprehend and place achievable quality and reliability metrics for each individual component prior to integration, in order to meet the heterogeneous system quality and reliability targets. Assembly and test flows will become inter- twined and interdependent. They need to be constructed in a manner that maintains a cost effective yield loss versus component cost balance and proper component fault isolation and quantification. The industry will be required to integrate components that cannot guarantee KGD without insurmountable cost penalties and this will require integrator visible and accessible repair mechanisms.

Test infrastructure hardware needs to comprehend multiple configurations of the same device to enable test point insertion at partially assembled and fully assembled states. This includes but is not limited to different component heights, asymmetric component locations, and exposed metal contacts (including ESD challenges). Test infrastructure software needs to enable storing and using volume test data for multiple components that may or may not have been generated within the final integrators data domains but are critical for the final heterogeneous system functionality and quality. It also needs to enable methods for highly granular component tracking for subsequent joint supplier and integrator failure analysis and debug.

Test design collaboration is one of the biggest challenges that the industry will need to overcome. It will be a requirement for heterogeneous highly integrated highly functional systems to have test features co‐designed across component boundaries that have more test coverage and debug capability than simple boundary scans. The challenge
of breaking up what was once the responsibility of a wholly contained design for test team across multiple independent entities each trying to protect IP, is only magnified by the additional requirement that the jointly developed test solutions will need to be standardized across multiple competing heterogeneous integrators. Industry wide collaboration on and adherence to test standards will be required in order to maintain cost and time effective design cycles for highly desired components that traditionally has only been required for cross component boundary communication protocols.

The roadmapping process

The objective of ITRS 2.0 for heterogeneous integration is to focus on a limited number of key challenges (10) that have the greatest potential to be “show stoppers,” while leaving other challenges identified and listed but without focus on detailed technical challenges and potential solutions. In this process collaboration with other Focus Teams and Technical Working Groups will be a critical resource. While we will need collaboration with other groups both inside and outside the ITRS some of the collaborations are critical for HI to address its mission. FIGURE 1 shows the major internal collaborations in three categories.

FIGURE 1. Collaboration priorities.

FIGURE 1. Collaboration priorities.

We expect to review these key challenges and our list of other challenges on a yearly basis and make changes so that our focus keeps up with changes in the key challenges. This will ensure that our efforts remain focused on the pre‐competitive technologies that have the greatest future value to our audience. There are four phases in the process detailed below.

1. Identify challenges for application areas: The process would involve collaboration with other focus teams, technical TWGs and other roadmapping groups casting a wide net to identify all gaps and challenges associated with the seven selected application areas as modified from time to time. This list of challenges will be large (perhaps hundreds) and they will be scored by the HI team by difficulty and criticality.

2. Define potential solutions: Using the scoring in phase (1) a number (30‐40) will be selected to identify potential solutions. The remainder will be archived for the next cycle of this process. This work will be coordinated with the same collabo- ration process defined above. These potential solutions will be scored by probable success and cost.

3. Down select to only the 10 most critical challenges: The potential solutions with the lowest probability of success and highest cost will have the potential to be “show stopping” roadblocks. These will be selected using the scoring above and the focus issues for the HI roadmap. The results of this selection process will be commu- nicated to the relevant collaboration partners for their comments.

4. Develop a roadmap of potential solutions for “show stoppers”: The roadmap developed for the “show stopping” roadblocks shall include analysis of the blocking issue and identification of a number of potential solutions. The collaboration shall include detail work with other units of the ITRS, other roadmapping activity such as the Jisso Roadmap, iNEMI Roadmap, Communications Technology Roadmap from MIT. We are continuing to work with the global technical community: industry, research institutes and academia, including the IEEE CPMT Society.

The blocking issues will be specifically investigated by the leading experts within the ITRS structure, academia, industry, government and research organizations to ensure a broad based understanding. Potential solutions will be identified through a similar collaboration process and evaluated through a series of focused workshops similar to the process used by the ERD iTWG. This process is a workshop where there is one proponents and one critic presenting to the group. This is followed by a discussion and a voting process which may have several iterations to reach a consensus.

The cross Focus Team/TWG collaboration will use a procedure of iteration to converge on an understanding of the challenges and potential solutions that is self‐ consistent across the ITRS structure. An example is illustrated in FIGURE 2.

FIGURE 2. Iterative collaboration process

FIGURE 2. Iterative collaboration process

It is critically important that our time horizon include the full 15 years of the ITRS. The work to anticipate the true roadblocks for heterogeneous integration, define potential solutions and implement a successful solution may require the full 15 years. Among the tables we will include 5 year check points of the major challenges for the key issues of cost, power, latency and bandwidth. In order for this table to be useful we will face the challenge of identifying the specific metric or metrics to be used for each application driver as we prepare the Heterogeneous Integration roadmap chapter for 2015 and beyond.

BILL CHEN is a senior technical advisor for ASE US, Sunnyvale, CA; BILL BOTTOMS is President and CEO of 3MT Solutions, Santa Clara, CA, DAVE ARMSTRONG is director of business development at Advantest, Fort Collins, CO; and ATSUNOBU ISOBAYASHI works in the Toshiba’s Center for Semiconductor Research & Development, Kangawa, Japan.

North America-based manufacturers of semiconductor equipment posted $1.37 billion in orders worldwide in March 2015 (three-month average basis) and a book-to-bill ratio of 1.10, according to the March EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in March 2015 was $1.37 billion. The bookings figure is 4.6 percent higher than the final February 2015 level of $1.31 billion, and is 5.9 percent higher than the March 2014 order level of $1.30 billion.

The three-month average of worldwide billings in March 2015 was $1.25 billion. The billings figure is 2.4 percent lower than the final February 2015 level of $1.28 billion, and is 1.9 percent higher than the March 2014 billings level of $1.23 billion.

““Three-month average bookings reported by North American-based semiconductor manufacturing equipment providers reflected sequential and year-over-year momentum in the first quarter of 2015,”” said SEMI president and CEO Denny McGuirk. “This marks the third consecutive month that bookings exceeded billing and the ratio remained above parity.””

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

Billings
(3-mo. avg)

Bookings
(3-mo. avg)

Book-to-Bill
October 2014 

$1,184.2

$1,102.3

0.93
November 2014 

$1,189.4

$1,216.8

1.02
December 2014 

$1,395.9

$1,381.5

0.99
January 2015 

$1,279.1

$1,325.6

1.04
February 2015 (final)

$1,280.1

$1,313.7

1.03
March 2015 (prelim)

$1,249.1

$1,374.4

1.10

Source: SEMI, April 2015

IC Insights will release its April Update to the 2015 McClean Report later this month. The Update includes the final 2014 company sales rankings for the top 50 semiconductor and top 50 IC companies, and the leading IC foundries. Also included are 2014 IC company sales rankings for various IC product segments (e.g., DRAM, MPU, etc.).

In 2014, there were only two Japanese companies—Toshiba and Renesas—that were among the top 10 semiconductor suppliers (Figure 1). Assuming the NXP/Freescale merger is completed later this year, IC Insights forecasts that Toshiba will be the lone Japanese company left in the top 10 ranking. Anyone who has been involved in the semiconductor industry for a reasonable amount of time realizes this is a major shift and a big departure for a country that once was feared and revered when it came to its semiconductor sales presence in the global market.

Fig 1

Fig 1

Figure 1 traces the top 10 semiconductor companies dating back to 1990, when Japanese semiconductor manufacturers wielded their greatest influence on the global stage and held six of the top 10 positions.  The six Japanese companies that were counted among the top 10 semiconductor suppliers in 1990 is a number that has not been matched by any country or region since (although the U.S. had five suppliers in the top 10 in 2014). The number of Japanese companies ranked in the top 10 in semiconductor sales slipped to four in 1995, fell to three companies in 2000 and 2006, and then to only two companies in 2014.

Figure 1 also shows that, in total, the top 10 semiconductor sales leaders are making a marketshare comeback. After reaching a marketshare low of 45 percent in 2006, the top 10 semiconductor sales leaders held a 53 percent share of the total semiconductor market in 2014.  Although the top 10 share in 2014 was eight points higher than in 2006, it was still six points below the 59 percent share they held in 1990.  As fewer suppliers are able to achieve the economies of scale needed to successfully invest and compete in the semiconductor industry, it is expected that the top 10 share of the worldwide semiconductor market will continue to slowly increase over the next few years.

On June 18, the SEMI Packaging Tech Seminar will take place in Vila do Conde, Portugal. Organized by SEMI Europe (www.semi.org/eu/), the event will be hosted by NANIUM S.A., Europe’s leading Outsourced Semiconductor Assembly and Test (OSAT). More than 100 industry professionals are expected at the event, which is dedicated to packaging, assembly, and test, with a focus on large format Fan-Out Packaging. In addition, European back-end organizations with manufacturing in Europe will have an opportunity to present corporate capabilities.

The morning session will showcase the European packaging, assembly and test industry.  Rozalia Beica of Yole Développement will present a market overview of the sector in Europe. Twelve SEMI members with manufacturing centers in Europe or European Equipment and Manufacturing companies with activities in packaging, assembly and test, will present.

The afternoon session will highlight large format Fan-Out Packaging, going beyond mainstream 200 and 300mm round wafer level packaging. Fan-Out Packaging technologies have gained momentum in recent years, with major OSATs, and even the largest wafer foundries, proposing Fan-Out Packaging solutions as part of their technology portfolio. Jan Vardaman (TechSearch International) will deliver the keynote presentation “The Movement to Large Array Packaging: Opportunities and Options.” The session will also feature presentations from research and technology organizations and equipment and materials companies, who will share viewpoints and recent achievements regarding the production of round rebuilt panels greater than 300mm and rectangular rebuilt panels. Speakers will include representatives from Fraunhofer IZM, Rudolph Technologies, SPTS, and SUSS MicroTec.

The presentations will be followed by several networking opportunities, including a Fab Tour of the   NANIUM S.A. Wafer-Level Packaging (WLP) manufacturing floor, plus a guided tour and networking dinner in the ancient downtown of Porto. Throughout the day, event sponsors will promote their packaging activities at a dedicated tabletop exhibition area.

“Europe is the home of a full back-end supply chain, including internationally renowned equipment and materials companies, research institutes, service providers and numerous packaging, assembly and test manufacturing companies,” stated Heinz Kundert, president of SEMI Europe. “By inviting our members to this Packaging Tech Seminar, we are aiming to enhance the growth of the European Packaging industry by proposing a platform for the development of business and collaborative opportunities.”

Armando Tavares, president of NANIUM’s Executive Board commented, “We have been a member of SEMI for many years, and are very pleased that we were selected as event hosts for the second time. Our industry ensures the competitiveness of sectors that are crucial for Europe, such as Automotive, Aerospace and Banking.  The EU’s 10/100/20 vision would greatly benefit from investing across the whole semiconductor supply chain, where Packaging, Assembly and Test is playing a more crucial and value-adding role than ever before.”

On June 19, attendees will have the additional opportunity to participate in the ESPAT (European Semiconductor Packaging Assembly and Test) Industry Interest Group meeting. SEMI will participate in this meeting, dedicated to advancing the interests of the European Packaging Industry and with the eventual goal of creating a SEMI-SIG (Special Interest Group).

SEMI Tech Seminars are open to everyone and free of charge for SEMI members.

Registration is now open; please visit www.semi.org/eu/node/8971 to learn more and to register. For additional information, contact Yann Guillou, SEMI Europe Grenoble Office ([email protected]).  For information about sponsoring the event, please contact Jérôme Boutant: [email protected].

Consider these eight issues where the packaging team should be closely involved with the circuit design team.

BY JOHN T. MACKAY, Semi-Pac, Inc., Sunnyvale, CA

Today’s integrated circuit designs are driven by size, performance, cost, reliability, and time- to-market. In order to optimize these design drivers, the requirements of the entire system should be considered at the beginning of the design cycle—from the end system product down to the chips and their packages. Failure to include packaging in this holistic view can result in missing market windows or getting to market with a product that is more costly and problematic to build than an optimized product.

Chip design

As a starting consideration, chip packaging strategies should be developed prior to chip design completion. System timing budgets, power management, and thermal behavior can be defined at the beginning of the design cycle, eliminating the sometimes impossible constraints that are given to the package engineering team at the end of the design. In many instances chip designs end up being unnecessarily difficult to manufacture, have higher than necessary assembly costs and have reduced manufacturing yields because the chip design team used minimum design rules when looser rules could have been used.

Examples of these are using minimum pad-to-pad spacing when the pads could have been spread out or using unnecessary minimum metal to pad clearance (FIGURE 1). These hard taught lessons are well understood by the large chip manufacturers, yet often resurface with newer companies and design teams that have not experienced these lessons. Using design rule minimums puts unnecessary pressure on the manufacturing process resulting in lower overall manufacturing yields.

Packaging 1

FIGURE 1. In this image, the bonding pads are grouped in tight clusters rather than evenly distributed across the edge of the chip. This makes it harder to bond to the pads and requires more-precise equipment to do the bonding, thus unnecessarily increasing the assembly cost and potentially impacting device reliability.

Packaging

Semiconductor packaging has often been seen as a necessary evil, with most chip designers relying on existing packages rather than package customization for optimal performance. Wafer level and chipscale packaging methods have further perpetuated the belief that the package is less important and can be eliminated, saving cost and improving performance. The real fact is that the semiconductor package provides six essential functions: power in, heat out, signal I/O, environmental protection, fan-out/compatibility to surface mounting (SMD), and managing reliability. These functions do not disappear with the implementation of chipscale packaging, they only transfer over to the printed circuit board (PCB) designer. Passing the buck does not solve the problem since the PCB designers and their tools are not usually expected to provide optimal consideration to the essential semiconductor die requirements.

Packages

Packaging technology has considerably evolved over the past 40 years. The evolution has kept pace with Moore’s Law increasing density while at the same time reducing cost and size. Hermetic pin grid arrays (PGAs) and side-brazed packages have mostly been replaced by the lead-frame-based plastic quad flat packs (QFP). Following those developments, laminate based ball grid arrays (BGA), quad flat pack no leads (QFN), chip scale and flip-chip direct attach became the dominate choice for packages.

The next generation of packages will employ through-silicon vias to allow 3D packaging with chip-on-chip or chip-on-interposer stacking. Such approaches promise to solve many of the packaging problems and usher in a new era. The reality is that each package type has its benefits and drawbacks and no package type ever seems to be completely extinct. The designer needs to have an in-depth understand of all of the packaging options to determine how each die design might benefit or suffer drawbacks from the use of any particular package type. If the designer does not have this expertise, it is wise to call in a packaging team that possesses this expertise.

Miniaturization

The push to put more and more electronics into a smaller space can inadvertently lead to unnec- essary packaging complications. The ever increasing push to produce thinner packages is a compromise against reliability and manufacturability. Putting unpackaged die on the board definitely saves space and can produce thinner assemblies such as smart card applications. This chip-on-board (COB) approach often has problems since the die are difficult to bond because of their tight proximity to other components or have unnecessarily long bond wires or wires at acute angles that can cause shorts as PCB designers attempt to accommodate both board manufacturing line and space realities with wire bond requirements.

Additionally, the use of minimum PCB design rules can complicate the assembly process since the PCB etch-process variations must be accommodated. Picking the right PCB manufacturer is important too as laminate substrate manufacturers and standard PCB shops are most often seen as equals by many users. Often, designers will use material selections and metal systems that were designed for surface mounting but turn out to be difficult to wire bond. Picking a supplier that makes the right metallization tradeoffs and process disciplines is important in order to maximize manufacturing yields

Power

Power distribution, including decoupling capaci- tance and copper ground and power planes have been mostly a job for the PCB designer. This is a wonder to most users as to why decoupling is rarely embedded into the package as a complete unit. Cost or package size limitations are typically the reasons cited as to why this isn’t done. The reality is that semiconductor component suppliers usually don’t know the system requirements, power fluctuation tolerance and switching noise mitigation in any particular installation. Therefore power management is left to the system designer at the board level.

Thermal Management

Miniaturization results in less volume and heat spreading to dissipate heat. Often, there is no room or project funds available for heat sinks. Managing junction temperature has always been the job of the packaging engineer who must balance operating and ambient temperatures and packaging heat flow.

Once again, it is important to develop a thermal strategy early in the design cycle that includes die specifics, die attachment material specification, heat spreading die attachment pad, thermal balls on BGA and direct thermal pad attachment during surface mount.

Signal input/output

Managing signal integrity has always been the primary concern of the packaging engineer. Minimizing parasitics, crosstalk, impedance mismatch, transmission line effects and signal atten- uation are all challenges that must be addressed. The package must handle the input/output signal requirements at the desired operating frequencies without a significant decrease in signal integrity. All packages have signal characteristics specific to the materials and package designs.

Performance

There are a number of factors that impact perfor- mance including: on-chip drivers, impedance matching, crosstalk, power supply shielding, noise and PCB materials to name a few. The performance goals must be defined at the beginning of the design cycle and tradeoffs made throughout the design process.

Environmental protection

The designer must also be aware that packaging choices have an impact on protecting the die from environmental contamination and/or damage. Next- generation chip-scale packaging (CSP) and flip chip technologies can expose the die to contami- nation. While the fab, packaging and manufacturing engineers are responsible for coming up with solutions that protect the die, the design engineer needs to understand the impact that these packaging technologies have on manufacturing yields and long-term reliability.

Involve your packaging team

Hopefully, these points have provided some insights on how packaging impacts many aspects of design and should not be relegated to just picking the right package at the end of the chip design. It is important that your packaging team be involved in the design process from initial specification through the final design review.

In today’s fast moving markets, market windows are shrinking so time to market is often the important differentiator between success and failure. Not involving your packaging team early in the design cycle can result in costly rework cycles at the end of the project, having manufacturing issues that delay the product introduction or, even worse, having impossible problems to solve that could have been eliminated had packaging been considered at the beginning of the design cycle.

System design incorporates many different design disciplines. Most designers are proficient in their domain specialty and not all domains. An important byproduct of these cross-functional teams is the spreading of design knowledge throughout the teams, resulting in more robust and cost effective designs.

Pibond Oy, a specialty chemical manufacturer of advanced semiconductor solutions, today introduced its new product line of liquid spin-on metal oxide hardmask materials. Targeting 10nm node semiconductor processing, 3D NAND, power ICs as well as MEMS applications, this technology enables advanced device manufacturing through reduced cost of ownership (COO) and simplified processing.

With the ever-increasing demand for increased functionality in applications from personal computing to mobile to cloud storage to wearables, the semiconductor industry is targeting smaller and smaller nodes and in so doing has lived up to Gordon Moore’sprediction. However, the limits of current lithography processes and the uncertainty surrounding next generation approaches, compounded by their costs, have cast doubt on whether Moore’s law has finally run “out of steam.”

Pibond’s materials are designed to bridge this gap, providing continuity for existing high-end fabs, while maintaining compatibility for future technology roadmaps. These novel polymers represent the next generation of liquid spin-on hard mask products and are suitable for advanced lithographic patterning, 2.5/3D-IC packaging, as well as MEMS processing.

Pibond’s SAP 100 product line is based on patent pending organo-siloxane modified spin-on metal oxide thin films that are compatible with advanced photoresist lithography and other semiconductor etch processes. The product line offers tunable optical (n&k) properties matching critical requirements of advanced lithography. Furthermore, it shows extraordinary etch resistance in plasma etching processes even at very low film thicknesses. Unlike most conventional hard masks, the Pibond SAP hard mask is applied with low cost spin-on track equipment, enabling high throughput and lowering the overall COO. Importantly, it can be applied with process equipment common in both state-of-the-art and legacy fabs, thus eliminating the need for new and potentially capital-intensive equipment. Future product releases in the SAP-100 family will be directly photopatternable further decreasing process complexity and COO.

“As process throughput and the demand for ever increasing device performance continue to challenge the semiconductor industry, we are happy to announce this new class of products based on advanced metal oxide and siloxane polymers. Capable of extending the runway for existing lithography tools and processes, thereby lowering the operating costs of current and future fabs, they are also paving the way for the future as new technologies like EUV mature,” said Jonathan Glen, Chairman of Pibond. “As the industry demands new materials to meet the needs of EUV lithography, 3D memory, power ICs, image sensors, TSV and MEMS applications, Pibond is well placed to be a driving force in this transition.”

Mentor Graphics Corporation this week announced its new Xpedition Package Integrator flow, the industry’s broadest solution for integrated circuit (IC), package, and printed circuit board (PCB) co-design and optimization. The Package Integrator solution automates planning, assembly and optimization of today’s complex multi-die packages. It incorporates a unique virtual die model concept for true IC-to-package co-optimization. In support of early marketing-level studies for a proposed new device, users can now plan, assemble and optimize complex systems with minimal source data. The new Package Integrator flow allows design teams to realize faster and more efficient physical path finding and seamless tool integration for rapid prototyping, right to the production flow.

This solution ensures that ICs, packages and PCBs are optimized with each other to reduce package substrate and PCB costs by efficient layer reduction, optimized interconnect paths, and streamlined/automated control of the design process. The Xpedition Package Integrator product also provides the industry’s first formal flow for ball grid array (BGA) ball-map planning and optimization based on an “intelligent pin” concept, defined by user rules. In addition, a groundbreaking multi-mode connectivity management system (incorporating hardware description language (HDL), spreadsheet and graphical schematic) provides cross-domain pin-mapping and system level cross-domain logical verification.

“Companies are recognizing that it will not be possible to design optimal systems in a timely fashion without the ability to co-design the IC, package, and board,” said E. Jan Vardaman, president and founder, TechSearch International, Inc. “Incorporating key parameters from thermal and electromagnetic modeling will be critical in meeting performance objectives. Automating this process is essential to meet development and product launch schedules in our fast moving market segments. Mentor’s Xpedition Package Integrator tool is a breakthrough in the design process.”

The Xpedition Package Integrator flow leverages other Mentor Graphics tools such as the HyperLynx signal and power integrity product, FloTHERM computational fluid dynamics (CFD) thermal modeling tools, and the Valor NPI substrate fabrication checking tool. To complete the Mentor Graphics co-design solution, Nimbic was acquired in 2014. The Nimbic technology provides Maxwell-accurate, 3D full-wave electromagnetic (EM) high-performance simulation solutions that accurately calculate complex electromagnetic fields for chip-package-board simulation.

“The Xpedition Package Integrator design flow, especially the unique virtual die model, gives package and board design experts really meaningful guidance and tools for their parts of the system design efforts,” said Herb Reiter, president of eda2asic and Director of 3D-IC Programs at Si2. “This flow also allows quick and structured feedback to the IC designers and enables true die-package-board co-design and optimization towards best possible performance versus power ratios for your next system design.”

“Mentor Graphics recognizes the increasing complexity in electrical systems design and manufacturing, particularly for IC, package and board co-design,” stated A.J. Incorvaia, vice president and general manager of Mentor Graphics Systems Design Division. “Our new Xpedition Package Integrator flow will enable systems designers to achieve optimum productivity by saving time and costs while improving the overall quality and performance of advanced systems.”

Entrepix, Inc., a provider of chemical mechanical polishing (CMP) equipment and process services, today announced that it has expanded its foundry operations in Phoenix, Arizona by installing 300mm chemical mechanical planarization (CMP) processing. The new offering expands on the company’s existing 200mm and below foundry operations, allowing Entrepix to offer CMP R&D and volume production for all wafer sizes up to 300mm.

To achieve this capability, Entrepix added AMAT Reflexion and Ebara F-REX 300 CMP polishing platforms in its Class 100 cleanroom. Both systems are available for various applications, including various dielectrics, metals and substrates. Additionally, the systems can be used for screening or comparing consumable sets (pads, slurries, pad conditioners and cleaning chemistries) across both platforms.

“Our foundry operations offer our customers a capability that is unique in the industry,” said Tim Tobin, CEO of Entrepix. “Our CMP consumable customers can benefit from creating independent, non-biased performance data for their products.”

The Entrepix foundry provides complete CMP solutions for customers at any level of development or production. This flexible manufacturing model improves financial performance by optimizing internal efficiencies and reducing time to revenue.

Entrepix Inc. serves the semiconductor and related industries as a provider of chemical mechanical polishing (CMP) production, integration and optimization services to IDMs, OEMs, MEMS, nanotechnology and CMP consumables suppliers. The company renews technology for existing and emerging CMP users by refurbishing semiconductor equipment or adapting the equipment for use in novel applications, such as airbag sensors and photovoltaics.

SEMI, the global industry association for companies that supply manufacturing technology and materials to the world’s chip makers, today reported that worldwide sales of semiconductor manufacturing equipment totaled $37.50 billion in 2014, representing a year-over-year increase of 18 percent. 2014 total equipment bookings were 8 percent higher than in 2013. The data are available in the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) Report, now available from SEMI.

Compiled from data submitted by members of SEMI and the Semiconductor Equipment Association of Japan (SEAJ), the Worldwide SEMS Report is a summary of the monthly billings and bookings figures for the global semiconductor equipment industry. The report, which includes data for seven major semiconductor producing regions and 24 product categories, shows worldwide billings totaled $37.50 billion in 2014, compared to $31.79 billion in sales posted in 2013. Categories cover wafer processing, assembly and packaging, test, and other front-end equipment. Other front-end includes mask/reticle manufacturing, wafer manufacturing, and fab facilities equipment.

Spending rates increased for all the regions tracked in the WWSEMS report, except for Taiwan. Even with the annual decrease, Taiwan remained the largest market for new semiconductor equipment for the third year in a row with $9.41 billion in equipment sales. The North American market held onto the second place with $8.16 billion in sales; South Korea maintained its third position with total sales of $6.84 billion. China moved up in the rankings, surpassing Japan with $4.37 billion in sales.

The global assembly and packaging segment increased 33 percent; total test equipment sales increased 31 percent; other front end equipment segment increased 15 percent; and the wafer processing equipment market segment increased 15 percent.

Semiconductor Capital Equipment Market by World Region (2013-2014)

(Dollar in U.S. billions; Percentage Year-over-Year)

2014

2013

% Change
Taiwan

9.41

10.57

-11%
North America

8.16

5.27

55%
South Korea

6.84

5.22

31%
China

4.37

3.37

30%
Japan

4.18

3.38

24%
Europe

2.38

1.91

25%
Rest of World

2.15

2.07

4%
Total

37.50

31.79

18%

Source: SEMI/SEAJ March 2015
Note: Figures may not add due to rounding.

Intel Corporation today announced that 19 companies will receive the 2014 Intel Preferred Quality Supplier (PQS) award that recognizes commitment to performance excellence and continuous improvement. These companies achieve PQS status by demonstrating industry-leading commitment across all key performance focus areas: quality, cost, availability, technology, customer service, labor and ethics systems, and environmental sustainability.

In addition to the PQS award, Intel recognized two suppliers with the Supplier Achievement Award, which is a focused recognition for extraordinary accomplishments in one or more key performance areas. This year’s winners were acknowledged for exceptional results delivering leading-edge technology solutions and excellence in product availability to meet Intel’s evolving needs as an industry leader. The 2014 PQS and Achievement winners will be honored at a ceremony tonight in Santa Clara, California.

“Intel is excited to acknowledge our Preferred Quality Suppliers for their outstanding performance in 2014 to deliver industry-leading technology with world-class cost, velocity and sustainability,” said Robert Bruck, vice president and general manager of Global Supply Management at Intel. “The innovation and cooperation of these suppliers remains one of the crucial factors in enabling Intel to extend our industry-leading silicon, packaging and test technologies, to enhance value to our customers.”

“2014 was a really pivotal year when our efforts to ramp new technologies and innovative products culminated in achieving positive momentum across all product categories,” added Jacklyn Sturm, vice president, Technology and Manufacturing Group and general manager of Global Supply Management at Intel. “ We could not have done this without Intel’s Preferred Quality Supplier Award winners working alongside us, tackling complex technical and supply chain challenges with market speed, with innovative solutions and sometimes, just exceptionally hard, flawless execution. Thank you for your unfaltering support toward your customer’s success.”

The PQS award is part of Intel’s Supplier Continuous Quality Improvement (SCQI) program that encourages suppliers to innovate and continually improve. To qualify for PQS status, suppliers must exceed high expectations and uncompromising performance goals while scoring at least 80 percent on an integrated report card that assesses performance throughout the year. Suppliers must also achieve 80 percent or greater on a challenging continuous improvement plan and demonstrate solid quality and business systems.

The PQS winners provide Intel with the following products or services:

  • Amkor Technology Inc.*: wafer probe, wafer bump, assembly, final testing services
  • Applied Materials Inc*: wafer fab capital equipment, mask capital equipment, fab automation software and services
  • ASML*: semiconductor lithography equipment
  • Daifuku*: automated material handling systems
  • Entegris Inc.*: contamination control, critical materials handling and advanced process materials
  • Fujifilm Electronic Materials*: process and formulated chemicals, developers, slurry, precursors and resist
  • Fujimi Corporation*: chemical mechanical planarization and silicon polishing slurries
  • Mitsubishi Gas Chemical Company Inc.*: high purity peroxide and custom back end cleans
  • ModusLink Global Solutions Inc.*: channel box CPU for Penang, Shanghai, Miami and finished goods warehouse distribution for Miami
  • Murata Machinery Ltd.*: automated material handling systems, hoist vehicles and stockers
  • Nikon Corporation*: semiconductor lithography systems for technology development and high volume manufacturing
  • Shin Etsu Handotai Co. Ltd.*: silicon wafers
  • Shinko Electric Industries Co., Ltd.*: plastic laminated packages and heat spreaders
  • Siliconware Precision Industries Co. Ltd.*: semiconductor assembly and test services
  • Siltronic AG*: polished and epitaxial silicon wafers
  • Taiyo Yuden Co. Ltd.*: ceramic capacitors, inductors, and filters
  • Tokyo Electron Limited*: coater/developer, dry etch systems, wet etch systems, thermal processing systems, deposition systems and test systems
  • Tokyo Ohka Kogyo Co. Ltd*: high purity photo resists, developers, cleaning solutions and supporting chemistries
  • Veolia North America*: waste management services

The Supplier Achievement Award winners are:

  • ASM International*: front end equipment manufacturer (recognizing extraordinary results in leading-edge technology solutions)
  • GE Water and Process Technologies*: UPW & wastewater recycle/reuse equipment and services (recognizing extraordinary results in product availability)