Category Archives: Materials and Equipment

Kandou Bus has announced the Glasswing family of chip interconnects targeted for in-package chip-to-chip links. Kandou introduced Chord Signaling in February 2014 and outlined how signals can be correlated across more than two wires to achieve higher bandwidth and lower power with excellent signal integrity and low latency. The Glasswing architecture optimizes Chord Signaling to address the unique challenges of both substrate and interposer in-package solutions.

For the first time in history, the cost to manufacture a transitor in the most advanced silicon process has increased compared to the previous generation. As a result, system architects are looking for more cost effective ways to partition and package silicon devices for optimal performance. Integrating several chips into a shared package can be attractive, but only if the in-package communication between chips allows for extremely high bandwidth and very low power.

“Architectures that combine multiple chips into a single package are not new,” said Kandou Founder and CEO Amin Shokrollahi, “but increasing bandwidth and improving signal integrity while maintaining very low power in an affordable package is a daunting task. Glasswing delivers on the promise of 2.5D integration by providing a cost-effective solution that offers unprecendented, in-package, chip-to-chip bandwidth at very low power.”

Glasswing Architecture and Applications

The core of Kandou’s Glasswing technology is a chordal code that delivers five bits over six correlated wires within each clock cycle. Through a simple yet elegant comparator network, signals are received and translated into bits resulting in much higher overall link throughput.

Depending on the application the link can run at up to 25 GBaud and deliver up to 20.8 Gbps per wire at less than 0.5pJ/bit in a 28nm logic process. These benefits are ideal for very short links (less than 10mm) such as the connnection inside a package between a DRAM stack and a controller, the link to an out-boarded high speed SerDes, or the coherency buses of a partitioned multi-core processor. The link can also work over channels up to 25mm in length with slightly more power.

To fully realize the benefits of the Glasswing architecture, Kandou has developed optimized circuits and architectures for all parts of the transmission chain including serializers, drivers, receivers, CDR units, skew mitigators, equalizers, deserializers and test circuits.

Kandou’s Glasswing product development is underway for the first instantiation of the PHY optimized for in-package links between processor cores. A comprehensive 28nm PHY evaluation package will be available Q3 2015.

Rice University scientists who want to gain an edge in energy production and storage report they have found it in molybdenum disulfide.

The Rice lab of chemist James Tour has turned molybdenum disulfide’s two-dimensional form into a nanoporous film that can catalyze the production of hydrogen or be used for energy storage.

The versatile chemical compound classified as a dichalcogenide is inert along its flat sides, but previous studies determined the material’s edges are highly efficient catalysts for hydrogen evolution reaction (HER), a process used in fuel cells to pull hydrogen from water.

Tour and his colleagues have found a cost-effective way to create flexible films of the material that maximize the amount of exposed edge and have potential for a variety of energy-oriented applications.

Molybdenum disulfide isn’t quite as flat as graphene, the atom-thick form of pure carbon, because it contains both molybdenum and sulfur atoms. When viewed from above, it looks like graphene, with rows of ordered hexagons. But seen from the side, three distinct layers are revealed, with sulfur atoms in their own planes above and below the molybdenum.

This crystal structure creates a more robust edge, and the more edge, the better for catalytic reactions or storage, Tour said.

“So much of chemistry occurs at the edges of materials,” he said. “A two-dimensional material is like a sheet of paper: a large plain with very little edge. But our material is highly porous. What we see in the images are short, 5- to 6-nanometer planes and a lot of edge, as though the material had bore holes drilled all the way through.”

The new film was created by Tour and lead authors Yang Yang, a postdoctoral researcher; Huilong Fei, a graduate student; and their colleagues. It catalyzes the separation of hydrogen from water when exposed to a current. “Its performance as a HER generator is as good as any molybdenum disulfide structure that has ever been seen, and it’s really easy to make,” Tour said.

While other researchers have proposed arrays of molybdenum disulfide sheets standing on edge, the Rice group took a different approach. First, they grew a porous molybdenum oxide film onto a molybdenum substrate through room-temperature anodization, an electrochemical process with many uses but traditionally employed to thicken natural oxide layers on metals.

The film was then exposed to sulfur vapor at 300 degrees Celsius (572 degrees Fahrenheit) for one hour. This converted the material to molybdenum disulfide without damage to its nano-porous sponge-like structure, they reported.

The films can also serve as supercapacitors, which store energy quickly as static charge and release it in a burst. Though they don’t store as much energy as an electrochemical battery, they have long lifespans and are in wide use because they can deliver far more power than a battery. The Rice lab built supercapacitors with the films; in tests, they retained 90 percent of their capacity after 10,000 charge-discharge cycles and 83 percent after 20,000 cycles.

“We see anodization as a route to materials for multiple platforms in the next generation of alternative energy devices,” Tour said. “These could be fuel cells, supercapacitors and batteries. And we’ve demonstrated two of those three are possible with this new material.”

Co-authors of the paper are Rice graduate students Gedeng Ruan and Changsheng Xiang. Tour is the T.T. and W.F. Chao Chair in Chemistry as well as a professor of materials science and nanoengineering and of computer science.

The Peter M. and Ruth L. Nicholas Postdoctoral Fellowship of Rice’s Smalley Institute for Nanoscale Science and Technology and the Air Force Office of Scientific Research Multidisciplinary University Research program supported the research.

At this week’s VISION 2014 exhibition, imec presents a backside-illuminated (BSI) CMOS image sensor chip featuring a new anti-reflective coating (ARC) optimized for UV light. Targeting imaging solutions in new markets such as life sciences, the achievement is an important addition to imec’s customized 200mm CMOS fab. This 200mm process line enables imec to offer design, prototyping and low volume manufacturing of custom specialty chip solutions such as highly specialized CMOS image sensors.

Known for its superior enhanced light sensitivity compared with image sensors using front side illumination (FSI), BSI sensors are top candidates to further improve the performance of CMOS image sensors. Widely spread today in consumer applications such as smart phones, BSI imagers are expected to enter the higher-end application space of e.g. industrial inspection.

BSI imagers have a clear advantage when it comes to fill factor for the pixel area, angular response, and the complete avoidance of absorption or scattering losses in the metal interconnect layers.  The cost for these light gathering improvement are the extra process complexity for the backside fabrication and possible electrical and optical losses at the new backside silicon interface. Therefore the engineering of the backside layers and interfaces is key to develop high performance BSI devices.

Imec is tackling these challenges to exploit the benefits of BSI imagers for highly specialized customized imagers for space applications, high speed cameras, semiconductor inspection and medical applications. To minimize reflection losses and maximize transmission of light to the sensor, specific anti-reflective coatings (ARC) are developed for various applications targeting different regions of the light spectrum. The coatings are applied at wafer level as part of the BSI process flow.

Imec has already developed an ARC for visible light range (400nm-800nm) with >70% QE over the entire spectral range. Imec’s new ARC, targeting the UV range, shows excellent performance at near UV wavelengths, with Quantum Efficiency (Q.E.) values above 50 percent over the entire spectral range from 260nm to 400nm wavelength.

“This is an important milestone for imec’s customized 200mm CMOS process line, demonstrating our expertise and capability to design, prototype and manufacture high-end CMOS image sensors,” said Rudi Cartuyvels, senior vice president, Smart Systems & Energy Technologies at imec. “The development widens our portfolio towards new markets, offering solutions for both visible and UV imaging in semiconductor equipment applications, such as advance lithography and wafer and mask inspection.”

SiTime Corporation, a MEMS and analog semiconductor company, today announced that it has signed a definitive agreement under which MegaChips Corporation, a top 25 fabless semiconductor company based in Japan, will acquire SiTime for $200 million in cash. This transaction combines two complementary fabless semiconductor companies that provide solutions for the growing wearables, mobile and Internet of Things markets.

“SiTime’s founders, Markus Lutz and Dr. Aaron Partridge, started the company with a vision of developing game-changing MEMS and analog technology to revolutionize the $5 billion timing industry,” said Rajesh Vashist, CEO of SiTime. “Through innovation, passion and focus, we’ve successfully delivered on this vision. Today, SiTime is the overwhelming leader – we have 1000 customers, 250 million units shipped, major design wins in all electronics segments, and a roadmap that extends SiTime’s MEMS technology to all timing markets.”

“Every SiTime employee is excited to be part of MegaChips as we share a common entrepreneurial culture,” continued Vashist. “MegaChips’ financial strength and scale, with SiTime’s innovation and passion, will rapidly accelerate the adoption of MEMS timing solutions.”

While the world of electronics has delivered many innovations, the clock function, which is the heartbeat in all electronics, still uses 75-year-old quartz technology. SiTime’s MEMS timing solutions replace dated quartz products in the telecom, networking, computing, storage and consumer markets, with the benefits of higher performance, smaller size, and lower power and cost.

“MegaChips has an aggressive growth strategy with a vision to become one of the top ten fabless semiconductor companies through both organic growth and strategic acquisitions,” said Akira Takata, President and CEO of MegaChips Corporation. “MEMS components are fuelling the growth of the semiconductor industry. Through the acquisition of SiTime, MegaChips becomes a leader in MEMS. SiTime will help us expand our portfolio and diversify our customer base. SiTime technology is the perfect match for MegaChips’ solutions that target Wearables, Mobile and IoT markets such as “frizz”, our ultra-low-power smart phone Sensor Hub LSI and BlueChip Wireless, a sub-GHz RF LSI.”

“As a founding investor in SiTime, Bosch recognized early on the tremendous vision and innovation behind SiTime’s approach to MEMS timing,” said Dr. Volkmar Denner, Chairman, Board of Management of Robert Bosch GmbH. “We have closely followed their success from a Silicon Valley startup to a revenue-generating company that sells to some of the world’s largest electronics companies. We are pleased that MegaChips is acquiring SiTime and we expect a bright future for the combined companies.”

“We are delighted by this merger. MegaChips and SiTime are very complementary companies with similar innovative and entrepreneurial cultures, and a unified vision that can transform the electronics industry,” said Joe Horowitz, Managing General Partner at Jafco Ventures and a SiTime Board Member. “By leveraging SiTime’s proprietary technologies and highly differentiated products, I have no doubt this combination is just at its opening act with a great future ahead.”

“Over the past ten years, SiTime has built an extraordinary technology platform and a family of products that is in high demand at leading customers,” said Brooke Seawell, a Venture Partner at New Enterprise Associates and a founding investor and Board Member at SiTime. “With MegaChips’ operational and global scale, SiTime’s future is bright. The combined company will accelerate the adoption of MEMS timing solutions and will become a leading supplier to the electronics industry.”

Upon closing, scheduled for November 2014 pending regulatory approvals and customary closing conditions, SiTime will retain its name and operate as a wholly owned subsidiary of MegaChips. During this transaction, Needham & Company, LLC served as the exclusive financial advisor to SiTime.

MegaChips Corporation was established in 1990 as a fabless company dedicated to ASICs and system LSIs with the goal of integrating LSIs and systems knowledge and solutions.

Element Six this week announced the development of a new thermal grade of diamond grown by chemical vapor deposition (CVD), DIAFILM TM130. DIAFILM TM130 has a thermal conductivity in excess of 1300 W/mK and is available in both metallized and un-metallized wafers form.  Similar to Element Six’s material grades in its DIAFILM TM range, TM130 offers full isotropic heat spreading in both planar and through plane directions. Element Six now provides a total of five material grades spanning five levels of performance ranging from 1000 W/mK to 2000 W/mK.

“CVD diamond is the most thermally conductive material at room temperature, far surpassing the thermal conductivity of copper. With this new offering, we’re continuing to build our extensive portfolio of thermal grade materials to meet the needs of those in the microelectronics and electronics packaging industry,” said Director of Element Six Technologies, Adrian Wilson. “Recognizing a ‘one-size fits all’ approach is not effective, we’re committed to providing a full range of options and specifications to effectively address thermal management challenges, including specific requirements for surface flatness, low roughness and metallization.”

CVD diamond is uniquely suited for advanced thermal management in applications such as advanced packaging, due to its exceptional combination of properties including high thermal conductivity, mechanical strength, electrical insulation, low weight and chemical inertness. In this role, CVD diamond enables system size reductions, improved reliability and the opportunity to design higher power systems within an existing module footprint.

With a focus on customizability, Element Six’s solid thermal products are available up to three millimeters thick and in diameters up to 140 millimeters that can be laser cut to any required size. Furthermore, metallization solutions enable die bonding with low thermal barrier resistance, consistent with industry standard soldering and brazing.

At the IMAPS 47th International Symposium on Microelectronics, Element Six will present on “Advanced Thermal Dissipation in GaN-on-Diamond Transistors,” developed in conjunction with the University of Notre Dame, on Wednesday, Oct. 15 at 8 a.m. PT. This presentation will discuss the thermal barriers that stand in the way of achieving the intrinsic performance potential of gallium nitride (GaN) semiconductors. In reviewing challenges, the presentation will share details about a recent solution which replaces GaN’s entire host substrate—such as silicon (Si) or silicon carbide (SiC)—with a synthetic diamond substrate, resulting in a more than 40 percent reduction of peak device temperature.

IRLYNX and CEA-Leti today announced they have launched a technology-development partnership for a new CMOS-based infrared technology that will allow a new type of smart and connected detectors in buildings and cities.

The strategic partnership with Leti’s Silicon Development Division and the Optics and Photonics Division will develop a solid technology platform that allows IRLYNX to provide an unrivalled solution in the field of human-activity detection and characterization. These products will be able to count people, distinguish humans, get positions and determine posture. This new, low-cost technology will help IRLYNX bring to the market new sensors targeting various applications in energy saving, safety and security and human/object interactions.

The collaboration is based on the development of specific microelectronic steps above CMOS IC and on the hosting of IRLYNX R&D’s activities inside Leti’s clean-room facilities.

Partially funded through the Easytech program of the IRT Nanoelec research institute, the partnership blends Leti’s expertise in advanced materials and photonics technologies developments. IRLYNX is focusing for its part on a specific IC design, a customized optic integration and the “on-die” data processing of such human-sensing-activity module.

“Through this strong partnership with CEA-Leti, we continue to deploy our strategic plan as expected. The capacities and how-know of Leti in advanced-technologies development are really an advantage for IRLYNX. With this agreement and Leti’s support, we are shortening our time to market,” said Sébastien Fabre, IRLYNX CEO.

“The collaboration with IRLYNX highlights Leti’s mission to support startup initiatives and emphasizes our expertise in IR imaging devices and technologies,” said Bruno Mourey, vice president of Leti’s Optics and Photonics Division. “IRLYNX is a very good match for Leti, because the IRLYNX team has an innovative IC design, clear optic-integration goals and a persuasive business plan.”

With its recent first round of funding, which raised 1M€, IRLYNX will be able to deliver first products in the third quarter of 2015.

Texas Instruments today announced it has shipped more than 22 billion units of copper wire bonding technology from its internal assembly sites and is now in production for major high reliability applications including automotive and industrial.  The majority of TI’s existing analog and CMOS silicon technology nodes have been qualified with copper, and all new TI technologies and packages are being developed with copper wire bond.  Along with its quality, reliability and cost benefits, copper wire offers equal or better manufacturability compared to gold.  It also delivers 40 percent higher electrical conductivity to give customers a boost in overall product performance with a number of TI’s analog and embedded processing parts.

“TI has pioneered development of copper wire bonding for high volume production across a broad portfolio of products, factories and technologies,” said Jan Vardaman, president and founder of TechSearch International, Inc.  “TI was one of the first manufacturers to recognize the many advantages copper wire technology offers a customer.  For example, it provides more thermal stability than gold and has superior mechanical properties to increase bond strength.”

TI is currently shipping about two billion units of copper wire bond technology each quarter.  This includes production for key automotive segments such as safety (e.g., anti-lock brake systems, power steering, stability control), infotainment, body and comfort, and powertrain.  Enabling copper wire bond technology for automotive applications requires significant development to automotive standards and strict manufacturing discipline. TI’s extensive manufacturability and reliability testing meets automotive industry qualification requirements and includes thorough process corner development, production quality and reliability monitoring, and manufacturing controls.

TI began shipping copper wire in its products in 2008.  Today, all of TI’s assembly and test (A/T) sites are running copper wire bonding on all TI package types, including BGA, QFN, QFP, TSSOP, SOIC, PDIP and others.  Copper is at 71 percent of TI’s total wire usage and TI is in production with:

  • Minimum 30/60 microns staggered bond pad pitch
  • Up to 1000 wires in BGA packages
  • Multi-chip stacked die with die to die wire bonding
  • Minimum 0.8mil copper wire diameter

“Having multiple wire bond capabilities that support a wide range of silicon technologies and product applications is a great benefit to our customers,” said Devan Iyer, director of Semiconductor Packaging in TI’s Technology & Manufacturing Group.  “TI’s flexible manufacturing strategy also improves customer delivery and performance for products using copper wire bond.  We have a clear capacity advantage, both internally and with qualified subcontractors, that enable us to meet all levels of customer demand.”

A novel metal gate integration scheme to achieve precise threshold voltage (VT) control for multiple VTs is described. 

BY NAOMI YOSHIDA, KEPING HAN, MATTHEW BEACH, XINLIANG LU, RAYMOND HUNG, HAO CHEN, WEI TANG, YU LEI, JING ZHOU, MIAO JIN, KUN XU, ANUP PHATAK, SHIYU SUN, SAJJAD HASSAN, SRINIVAS GANDIKOTA, CHORNG-PING CHANG and ADAM BRAND, Applied Materials, Santa Clara, CA 

At very small process geometries, precise control of electrical conductivity is difficult to maintain. The industry requires a viable replacement-gate FinFET architecture to continue scaling high performance CMOS [1, 2] technology and designs. Furthermore, cost-effective and precise VT control to achieve multiple VTs is essential for future ULSI fabrication to achieve optimal power consumption and performance.

In this study, using WFM full fill and combining two techniques — the novel metal composition and ion implantation into the WFM process, we successfully realized three critical aspects for the metal gate for 10 nanometer and beyond. These are: 1) precise effective work function (eWF) control over a 600 millivolt (mV) tuning range to achieve multiple VT, 2) maintaining conductivity for a sub-15 nanometer gate trench, and 3) compatibility to the self-aligned contact (SAC).

A metal oxide semiconductor capacitor (MOSCAP) was used to evaluate the impact of the metal compo- sition and beam line ion implantation on eWF. Ion implantation was performed for some of the samples after high-k dielectric and work function metal deposition on blanket wafers. High frequency capacitance voltage (HFCV) and current voltage (IV) measurements were recorded for the MOSCAP samples. A single damascene structure was used to measure sub-20 nanometer line resistance. A planar MOSFET was also used for evaluating impact on VT and variability.

Work function modulation

FIGURE 1 shows eWF with three compositions of NMOS WF metals (nWFM) compared with RF-PVD titanium aluminum (TiAl) that was used as the nWFM reference metal. Results demon- strated that the difference between the highest and lowest WF was 550 mV and is attributed to the ALD TiAl composition. Nitrogen ion implantation into the ALD TiAl enabled further WF tuning by 100-150 mV steps. This made possible a WF range from near the Si conduction band edge of 4.1 electron volts (eV) for NMOS low VT to above mid-gap 4.7 eV. The WF shift corresponded well to the different dose levels; therefore we demonstrated that ion implantation can be used to pinpoint the target WF. In addition, we found that ion implantation into ALD TiAl does not degrade the gate leakage current and effective oxide thickness (EOT) performance.

FIGURE 1. nWFM composition impact on eWF.

FIGURE 1. nWFM composition impact on eWF.

Maintaining metal gate conductance for 10nm node

According to the ITRS roadmap, a gate length of 17 nanometers is expected for the 10 nanometer technology node [3]. The problem is that after the high-k cap and etch stop depositions, the gate will have limited space left for the metal fill process [4]. One solution is to fully or mostly fill the trench with WF metal. Using an advanced ALD TiAl deposition process, we were able to fill 13 nanometer wide trenches without any gapfill voids. FIGURE 2 shows the extendible conductance of the ALD TiAl and WF fill process.

FIGURE 2. Conductance curves of various metals filling small trenches.

FIGURE 2. Conductance curves of various metals filling small trenches.

It is known that NMOS low WF metals are more prone to oxidization than high WF PMOS films such as titanium nitride (TiN) and that air exposure affects VT control [5]. In our study, degradation on the conductance curves from air exposure was also observed (FIGURE 3). The air exposed sample showed a large offset of the conductance curve to the right while maintaining the slope, i.e. differential resistivity. The TEM (FIGURE 4) shows an additional layer between the TiN barrier and ALD TiAl. Scanning transmission electron microscope- electron energy loss spectroscopy analysis confirmed high oxygen in the white interface. Thus, it is critical to have an in situ ALD TiAl process on the high k TiN cap to maintain conductivity for the 10 nanometer node.

FIGURE 3. Effect of air exposure in between TiN barrier and nWF metal on conductance below 30 nanometers.

FIGURE 3. Effect of air exposure in between TiN barrier and nWF metal on conductance below 30 nanometers.

FIGURE 4. TEM images at interface of TiN barrier and nWFM. The ex situ sample shows oxidized interface by air exposure.

FIGURE 4. TEM images at interface of TiN barrier and nWFM. The ex situ sample shows oxidized interface by air exposure.

Self-aligned contact compatibility and CMOS VT tuning

At the 22 nanometer technology node, a metal gate SAC is necessary to scale contacted gate pitch [1]. This requires a well-controlled etch back of the metal gate, with subsequent capping of the etch stop material such as silicon nitride (SiN) to prevent contact to gate shorts. Tungsten (W) has been used in volume production because it offers a robust etch back process. In our study, we demonstrated that a controlled recess etch can be achieved with the more conductive TiAl fill compared to W (FIGURE 5). In addition, after metal etch back, a SAC cap was successfully formed with a high density plasma (HDP) SiN fill and chemical mechanical planarization (CMP).

FIGURE 5. Cross-sectional TEM images show controlled etch back of ALD TiAl fill metal gate for SAC integration. The left and middle images after recess etch-back. The right image is after Cap Nitride CMP.

FIGURE 5. Cross-sectional TEM images show controlled etch back of ALD TiAl fill metal gate for SAC integration. The left and middle images after recess etch-back. The right image is after Cap Nitride CMP.

Multiple WF metals need to be integrated for CMOS VT tuning for NMOS and PMOS. In our study we examined the CMOS ALD TiAl flow for four VT tunings. From the results, we propose a new process flow: 1) after the high-k and etch stop layer deposition steps, a fully clustered barrier TiN and nWFM be deposited. Some areas can be masked by photoresist (PR) and the exposed area modified by ion implantation. 2) Etch off the first nWF layer from the PMOS areas. 3) Deposit the second WF (N-3) and barrier. 4) Perform second ion implantation to shift the WF of the third device. 5) Lastly, ALD TiAl is again etched off from the PMOS area WFM (TiN), followed by W or Al fill to fill the remaining gap. The last TiN material serves as the highest WF as well as the barrier layer for W or Al. This flow provides four VTs and metal fill with a clustered nWFM film stack.

Conclusion

Metal WF modulation for VT tuning using a new scheme tunable in the range of 600 mV was successfully demonstrated for 10 nanometer CMOS integration. Ion implantation dose control enabled continuous WF tuning for multiple VT targets. Metal gate conductance data showed the benefit of in situ processing with a TiN barrier and NMOS WF metal. Based on the results, a CMOS flow with NMOS WF-first was proposed for multi-VT tuning.

References

1. C. Auth et al., VLSI Tech. Sym. Dig., p. 131, (2012)
2. P. Packan et al., IEDM Tech. Dig., p. 659, (2009)
3. ITRS Roadmap 2011 Edition
4. N. Yoshida, et al., VLSI Tech. Sym. Dig., p. 81, (2012) 5. A. Veloso, et al., VLSI Tech. Sym. Dig., p. 33, (2012)

ARM and TSMC today announced a new multi-year agreement that will deliver ARMv8-A processor IP optimized for TSMC 10FinFET process technology. Because of the success in scaling from 20SoC to 16FinFET, ARM and TSMC have decided to collaborate again for 10FinFET. This early pathfinding work will provide valuable learning to enable physical design IP and methodologies in support of customers to tape-out 10FinFET designs as early as Q4 2015.

“ARM and TSMC are industry leaders in our respective fields and collectively ensure the availability of leading-edge solutions for ARM-based SoCs through our deep and long-term collaboration,” said Pete Hutton, executive vice president and president, product groups, ARM. “Our mutual commitment to providing industry leading solutions drives us to work together early in the development cycle to optimize both the processor and the process node. This joint optimization enables ARM silicon partners to design, tape-out and bring their products to market faster.”

TSMC will be applying the learnings from prior generations of 20SoC and 16FinFET in the ARM ecosystem to offer performance and power improvements at 10FinFET that will be better than previous nodes. The ARM ecosystem can also take advantage of TSMC’s Open Innovation Platform (OIP) which includes a set of ecosystem interfaces and collaborative components initiated and supported by TSMC.

“TSMC has continuously been the lead foundry to introduce advanced process technology for ARM-based SoCs,” said Dr. Cliff Hou, TSMC vice president of R&D. “Together with ARM, we proved out in silicon the high performance and low power of the big.LITTLE architecture as implemented in 16FinFET. Given the successful adoption of our previous collaborative efforts, it makes sense that we continue this fruitful partnership with ARM in future 64-bit cores and 10FinFET.”

The joint innovations from previous TSMC and ARM collaborations have enabled customers to accelerate their product development cycles and take advantage of leading-edge processes and IP. Recent benefits have included early access to ARM Artisan Physical IP and tape-outs of ARM Cortex-A53 and Cortex-A57 processors on 16FinFET.

Boston Semi Equipment LLC (BSE) today announced it has combined all of its automated test equipment (ATE) businesses under the Boston Semi Equipment brand name. Effective immediately, the Test Advantage Hardware and MVTS Technologies businesses will operate using the Boston Semi Equipment name. This follows the company’s announcement in July that it was integrating all sales and service for ATE, Prober and Test Handler products into the Boston Semi Equipment field sales organization.

Boston Semi Equipment has now built an organization of tester, handler and prober integration specialists to address the semiconductor industry’s need for a vendor-independent test cell solution provider. BSE can provide equipment configured to the customer’s exact requirements, deliver a complete test cell solution across all tester platforms fully utilizing the original OEM technology, and provide service and support to keep ATE at peak performance.

“We believe we have created the largest ATE-focused organization outside of the OEMs,” stated Bryan Banish, CEO of Boston Semi Equipment. “Our ATE organizations have been delivering standard ATE configurations, test services, custom equipment solutions, and service and support programs for our semiconductor ATE customers since 1994. Because we have experience on all major current generation and legacy ATE models, we can support any and all ATE-related projects to meet our customers’ test needs.”

BSE acquired Test Advantage Hardware in 2010 and has steadily expanded the company’s capabilities in current-generation ATE platforms. In June, 2014 the company also acquired MVTS Technologies (MVTS), which has extensive experience extending the life of legacy ATE, maximizing the investment of semiconductor companies in their test assets. The combined capabilities provide Boston Semi Equipment customers with an alternate source for high quality and economical ATE equipment, service, and test cell solutions. 

Boston Semi Equipment LLC is a semiconductor equipment company that has established a reputation as a reliable source for affordable back end test equipment, fab tools and service solutions for semiconductor manufacturers and OSATs worldwide.