Category Archives: Materials and Equipment

Rudolph Technologies has introduced its new SONUS Technology for measuring thick films and film stacks used in copper pillar bumps and for detecting defects, such as voids, in through silicon vias (TSVs). Copper pillar bumps are a critical component of many advanced packaging technologies and TSVs provide a means for signals to pass through multiple vertically stacked chips in three dimensional integrated circuits (3DIC). The new SONUS Technology is non-contact and non-destructive, and is designed to provide faster, less costly measurements and greater sensitivity to smaller defects than existing alternatives such as X-ray tomography and acoustic microscopy.

“SONUS Technology meets a critical need for measuring and inspecting the structures used to connect chips to each other and to the outside world,” said Tim Kryman, Rudolph’s director of metrology product management. “Copper pillar bumps and TSVs are critical interconnect technologies enabling 2.5D and 3D packaging. The mechanical integrity of the interconnect and final device performance are directly dependent on tight control of the plating processes used to create copper pillar bumps. Likewise, the quality of the TSV fill is critical to the electrical performance of stacked devices. This new technology allows us to measure individual films and film stacks with thicknesses up to 100µm, and detect voids as small as 0.5µm in TSVs with aspect ratios of 10:1 or greater.”

Kryman added, “SONUS Technology builds on the expertise we developed in acoustic metrology for our industry-standard MetaPULSE systems, which are widely used for front-end metal film metrology. By offering similar improvements in yield and time-to-profitability in high volume manufacturing (HVM), SONUS offers a compelling value proposition to advanced packaging customers.”

Both MetaPULSE and SONUS systems use a laser to initiate an acoustic disturbance at the surface of the sample. As the acoustic wave travels down through the film stack, it is partially reflected at interfaces between different materials. Although the detection schemes are different, the reflected waves are detected when they return to the surface and the elapsed time is used to calculate the thickness of each layer. In the case of SONUS Technology, two lasers are used. The first laser excites the sample and the second probes for the returning acoustics. This decouples excitation and detection allowing SONUS to continuously probe the sample resulting in a much larger film thickness range. So, where MetaPULSE can measure metal films and stacks to ~10 microns, SONUS can measure films in excess of 100 microns. In addition, SONUS Technology’s use of interferometry to characterize the surface displacement provides a rich data set that can be analyzed to not only characterize film thickness, but perform defect detection.

The primary alternatives for such measurements are X-ray based tomographic analysis and acoustic microscopy. SONUS Technology’s ability to detect voids as small as half a micrometer is approximately twice as good as current X-ray techniques, which have a spatial resolution of about 1 micrometer. Acoustic microscopy can make similar measurements, but the sample must be immersed in water, which, though not strictly destructive, does effectively preclude the return of the sample to production. SONUS is both non-contact and non-destructive and is designed for R&D and high-volume manufacturing.

In the run up to the product introduction, Rudolph worked closely with TEL NEXX to develop SONUS-based process control for pillar bump and TSV plating processes. Arthur Keigler, chief technology officer of TEL NEXX, said, “We are attracted by the opportunity SONUS Technology offers our mutual customers in the advanced packaging market. The ability to measure multi-metal film stacks for Cu pillar, and then continue to use the same tool for TSV void detection offers immediate productivity and cost benefits to manufacturing and development groups alike.”

While Rudolph is initially focused on using the technology for copper pillar bump process metrology and TSV inspection, they are also investigating other applications, ranging from detecting film delamination to metrology and process control for MEMS fabrication processes.

Oxford Instruments is hosting its third series of annual seminars for the nanotechnology industry in India in November.  “Bringing the Nanoworld Together 2014” seminars are being held in Kolkata (November 24-25th) and Delhi (November 27-28th) and will showcase cutting edge nanotechnology tools and their use in multiple fields.

image004

The first day at each venue will comprise Plenary Sessions focusing on “Emerging Materials for Nanoscale Devices – Fabrication & Characterization.” Day 2 will focus on thin film processing, materials characterisation, surface science and cryogenic environments.  A wide range of topics will be covered within each technical area. This will also present an excellent opportunity for networking between all participants, including guest speakers from prestigious Indian and international institutes, speakers from the host institutes, and technical experts from Oxford Instruments.

The thin film processing sessions will review the latest etch and deposition technological advances, including: ALD, Magnetron Sputtering, ICP PECVD, Nanoscale Etch, MEMS, MBE and more.

The materials characterisation, surface science and cryogenic environment sessions will cover multiple topics and technologies including: ultra high vacuum SPM, Cryofree low temperature solutions, XPS/ESCA, an introduction to atomic force microscopy (AFM), and applications such as nanomechanics, in-situ heating and tensile characterisation using EBSD, measuring layer thicknesses and compositions using EDS, and nanomanipulation and fabrication within the SEM/ FIB.  Andor Technology, a recently acquired business, will also be showcasing its high performance optical cameras and software which are used in both the physical and bio sciences.

Previous host Prof. Rudra Pratap, Chairperson at the Centre for Nano Science and Engineering, Indian Institute of Science, IISC Bangalore commented, “This seminar has been extremely well organized with competent speakers covering a variety of processes and tools for nanofabrication. It is great to have practitioners in these areas give talks and provide tips and solutions based on their experience – something that cannot be found in text books.”

Mark Sefton of Oxford Instruments Nanotechnology Tools commented, “We are demonstrating our commitment to our customers through providing these learning events, encouraging discussion and cross dissemination of ideas that is of benefit to all those attending. Not only do we provide high technology tools and excellent global service, but we want our customers to be empowered to use these systems to the best of their abilities, with the maximum information possible behind them.”

Ziptronix Inc. today announced that its Direct Bond Interconnect (DBI) hybrid bonding has been implemented by Fermi National Accelerator Laboratory (Fermilab) to improve the performance of high-end 3D sensor arrays, which are used for particle detection in large-scale particle physics and x-ray imaging experiments. This is an example of three-layer DBI hybrid bonding in a 3D imaging chip, using DBI wafer-to-wafer and die-to-wafer processes.

The demonstrator, a vertically integrated x-ray photon imaging chip (VIPIC) detector, was developed by a collaboration of scientists and engineers from Fermilab, Brookhaven National Laboratory and AGH University from Poland. DBI hybrid bonding technology enables versatile new designs for pixelated radiation detectors. Fermilab and Brookhaven are national laboratories funded by the U.S. Department of Energy.

“Implementing DBI hybrid bonding enables us to design sophisticated combinations of sensors and readout electronics,” said Ron Lipton, Staff Scientist, Fermilab. “By enabling vertical signals through stacked sensor, readout and processing layers, we can design large-scale arrays that are side-edge buttable with high fill factor.”

The process flow for manufacturing the VIPIC involves using wafer-to-wafer DBI hybrid bonding to bond two ASIC wafers containing through silicon vias (TSVs). The bonded wafer pair is thinned to expose the TSVs on one side, then singulated. The singulated die stacks are then bonded to an x-ray sensor wafer using die-to-wafer DBI hybrid bonding. Subsequent thinning of the other side of the bonded wafer pair allows backside connections to the 3-layer assembly.

“This is an advanced three-layer imaging chip manufactured using DBI hybrid bonding,” said Paul Enquist, CTO, Ziptronix. “Electrical data shows that this approach achieves lower noise, higher bandwidth and higher gain due to lower capacitive load when compared with parts stacked using bumping. This increases the sensitivity of the 3D image sensors, making them ideal for use in high-end applications.”

DBI hybrid bonding is a conductor/dielectric bonding technology that includes a variety of metal/oxide/nitride combinations, uses no adhesives and is CMOS foundry compatible. It allows for stronger bonds and finer-pitch interconnect over traditional thermocompression bonding since bonding occurs at both the conductive and dielectric materials, versus just the conductor. Bonding therefore takes place over the entire surface area, eliminating the need for underfill as well as significantly reducing the overall height of the structure.

GLOBALFOUNDRIES, a provider of advanced semiconductor manufacturing technology, today announced the “GLOBALFOUNDRIES Undergraduate Research Scholarship,” a new scholarship recognizing and rewarding aspiring, leadership-oriented engineering students interested in careers in the semiconductor industry.  The GLOBALFOUNDRIES Undergraduate Research Scholarship will fund undergraduate research opportunities (URO) and intern scholars through the Semiconductor Research Corporation’s (SRC) Education Alliance.

Presented at SRC’s annual TECHCON conference in Austin, Texas, the scholarship was created by GLOBALFOUNDRIES in partnership with SRC to recognize and reward science, technology and engineering students who demonstrate promise in their academic and professional efforts. The selected recipients of this scholarship will have the opportunity to interact with GLOBALFOUNDRIES researchers and access the professional resources of SRC and the SRC Education Alliance.

“Building a pipeline of highly skilled talent is essential to our business and to the competitiveness of the entire semiconductor industry,” said Suresh Venkatesan, senior vice president of technology development, GLOBALFOUNDRIES.  “SRC connects companies with the top universities, which results in exciting research and educational opportunities for the best and the brightest students. The GLOBALFOUNDRIES Undergraduate Research Scholarship gives us the opportunity to support science, technology, engineering and mathematics education and help develop the technical leaders who will continue to drive innovation in the semiconductor industry in the future.”

Until recently, SRC focused exclusively on students seeking advanced degrees, providing fellowships for them to do university research that had practical applications for corporate members of its unique consortium. The URO is SRC’s innovative program providing undergraduates with valuable research experience and mentoring. The goal of the URO is to empower bright, well-educated, and experienced scientists and engineers for which U.S. high-tech companies are seeking.

“Recognizing the critical importance of a strong pipeline of new talent for the semiconductor industry, the SRC Education Alliance through the URO Program provides financial assistance to undergraduates, allowing students and universities to recognize the connections between the materials they are learning in the classroom and the technological innovations that transform the world,” said SRC President Larry Sumney. “We are thrilled to collaborate with GLOBALFOUNDRIES as we continue to develop our URO program.”

Rising sophomores, juniors and seniors in an accredited undergraduate program majoring in the field of engineering are encouraged to apply.  Additional information about the scholarship can be obtained by visiting: www.src.org/program/srcea/uro/globalfoundries.

Every year, TECHCON brings together the brightest minds in microelectronics research to exchange news about the progress of new materials and processes created by SRC’s network of more than 100 of the top engineering universities. Students and industry leaders discuss basic research that is intended to accelerate advancements for both private and public entities.

Intel Corporation today announced two new technologies for Intel Custom Foundry customers that need cost-effective advanced packaging and test technologies.

Embedded Multi-die Interconnect Bridge (EMIB), available to 14nm foundry customers, is a breakthrough that enables a lower cost and simpler 2.5D packaging approach for very high density interconnects between heterogeneous dies on a single package. Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed. Standard flip-chip assembly is used for robust power delivery and to connect high-speed signals directly from chip to the package substrate. EMIB eliminates the need for TSVs and specialized interposer silicon that add complexity and cost.

“The EMIB technology enables new on-package functionality that may have been too costly to pursue with previous solutions,” said Babak Sabi, Intel vice president and director, Assembly and Test Technology Development.

Intel also announced the availability of its revolutionary High Density Modular Test (HDMT) platform. HDMT, a combination of hardware and software modules, is Intel’s test technology platform that targets a range of products in diverse markets including server, client, system on chip, and Internet of Things. Until now, this capability was only available internally for Intel products. Today’s announcement makes HDMT available to customers of Intel Custom Foundry.

“We developed the HDMT platform to enable rapid test development and unit-level process control. This proven capability significantly reduces costs compared to traditional test platforms. HDMT reduces time to market and improves productivity as it uses a common platform from low-volume product debug up to high-volume production,” said Sabi.

EMIB is available to foundry customers for product sampling in 2015 and HDMT is available immediately.

The global pressure sensors market was valued at $6.53 billion USD in 2013, growing at a CAGR of 6.2% from 2014 to 2020 to account for $9.36 billion USD in 2020, according to a new market report published by Transparency Market Research “Pressure Sensors Market – Global Industry Analysis, Size, Share, Growth, Trends and Forecast, 2014 – 2020.”

The pressure sensors market is primarily driven by growing demand from the automotive sector. With the increase in production of motor vehicles across the globe, the demand for automotive pressure sensors has grown substantially. In addition, government regulations mandating the use of pressure sensors in automobiles have contributed to the growth in demand for pressure sensors worldwide. With the adoption of technologies, such as Microelectromechanical systems (MEMS), the demand for pressure sensor has augmented to a large extent. The development of smart city infrastructures in the Middle East and Asia Pacific region is also influencing the overall growth of pressure sensors market.

Piezoresistive pressure sensors held the largest market revenue share accounting to $1.82 billion in 2014 and are expected to remain so during the forecast period. Demand for piezoresistive pressure sensors is attributed to their wide range of applications in automotive and medical sectors. Growing automobile production and rapid industrialization in the emerging economies of Asia-Pacific is also expected to drive the growth in pressure sensors market over the forecast period from 2014 to 2020.

The automotive segment led the pressure sensors market in 2014 accounting for $1.69 billion. The dominance of this segment is due to the rise in production of motor vehicles across the globe which has increased by 3.7% in 2013 as compared to the previous year. Consumer electronics is analyzed to be the fastest growing application segment for pressure sensors and is expected to attain a significant growth in the recent future. Consumer electronics segment is expected to grow at a CAGR of 6.9% over the forecast period from 2014 to 2020.

Geographically, Asia Pacific led the pressure sensors market in 2014 and the region is expected to continue its dominance over the forecast period. The region’s dominance is due to increasing production of motor vehicles in countries such as Japan, South Korea, China, and India. Moreover, rapid level of industrialization in this region is also contributing to the growth of pressure sensors market. North America and Europe followed Asia Pacific in the global pressure sensors market and collectively accounted for more than half of the global market revenue share.

University of California, Davis researchers sponsored by Semiconductor Research Corporation (SRC), a university-research consortium for semiconductors and related technologies, are exploring new materials and device structures to develop next-generation memory technologies.

The research promises to help data storage companies advance their technologies with predicted benefits including increased speed, lower costs, higher capacity, more reliability and improved energy efficiency compared to today’s magnetic hard disk drive and solid state random access memory (RAM) solutions.

Conducted by UC Davis’ Takamura Research Group that has extensive experience in the growth and characterization of complex oxide thin films, heterostructures and nanostructures, the research involves leveraging complex oxides to manipulate magnetic domain walls within the wires of semiconductor memory devices at nanoscale dimensions. This work utilized sophisticated facilities available through the network of Department of Energy-funded national laboratories at the Center for Nanophase Materials Sciences, Oak Ridge National Laboratory and the Advanced Light Source, Lawrence Berkeley National Laboratory.

“We were inspired by the ‘Race Track Memory’ developed at IBM and believe complex oxides have the potential to provide additional degrees of freedom that may enable more efficient and reliable manipulation of magnetic domain walls,” said Yayoi Takamura, Associate Professor, Department of Chemical Engineering and Materials Science, UC Davis.

Existing magnetic hard disk drive and solid state RAM solutions store data either based on the magnetic or electronic state of the storage medium. Hard disk drives provide a lower cost solution for ultra-dense storage, but are relatively slow and suffer reliability issues due to the movement of mechanical parts. Solid state solutions, such as Flash memory for long-term storage and DRAM for short-term storage, offer higher access speeds, but can store fewer bits per unit area and are significantly more costly per bit of data stored.

An alternative technology that may address both of these shortcomings is based on the manipulation of magnetic domain walls, regions that separate two magnetic regions. This technology, originally proposed by IBM researchers and named ‘Race Track Memory,’ is where the UC Davis work picked up.

With most previous studies focused on metallic magnetic materials and their alloys due to well-established processing steps and high Curie temperatures, challenges still remain in manipulating parameters such as the type of domain walls formed, their position within the nanowires and their controlled movement along the length of the nanowires.

The UC Davis research investigates the use of complex oxides, such as La0.67Sr0.33MnO3 (LSMO), and heterostructures with other complex oxides as candidate materials. Complex oxides are part of an exciting new class of so-called “multifunctional’ materials that exhibit multiple properties (e.g. electronic, magnetic, etc.) and may thereby enable multiple functions in a single device. For the case of LSMO, it is a half metal, exhibits colossal magnetoresistance (CMR), meaning it can dramatically change electrical resistance in the presence of a magnetic field, and undergoes a simultaneous ferromagnetic-to-paramagnetic and metal-to-insulator transition at its Curie temperature.

In addition, these properties are sensitive to external stimuli, such as applied magnetic/electric fields, light irradiation, pressure and temperature. These attributes may allow researchers to better manipulate the position and movement of the magnetic domain walls along the length of the nanowires.

“While still in the early stages, the innovative research from the UC Davis team is helping the industry gain a better fundamental understanding linking the chemical, structural, magnetic and electronic properties of next-generation memory materials,” said Bob Havemann, Director of Nanomanufacturing Sciences at the SRC.

There’s no shortage of ideas about how to use nanotechnology, but one of the major hurdles is how to manufacture some of the new products on a large scale. With support from the National Science Foundation (NSF), University of Massachusetts (UMass) Amherst chemical engineer Jim Watkins and his team are working to make nanotechnology more practical for industrial-scale manufacturing.

One of the projects they’re working on at the NSF Center for Hierarchical Manufacturing (CHM) is a roll-to-roll process for nanotechnology that is similar to what is used in traditional manufacturing. They’re also designing a process to manufacture printable coatings that improve the way solar panels absorb and direct light. They’re even investigating the use of self-assembling nanoscale products that could have applications for many industries.

“New nanotechnologies can’t impact the U.S. economy until practical methods are available for producing products, using them in high volumes, at low cost. CHM is researching the fundamental scientific and engineering barriers that impede such commercialization, and innovating new technologies to surmount those barriers,” notes Bruce Kramer, senior advisor in the NSF Engineering Directorate’s Division of Civil, Mechanical and Manufacturing Innovation (CMMI), which funded the research.

“The NSF Center for Hierarchical Manufacturing is developing platform technologies for the economical manufacture of next generation devices and systems for applications in computing, electronics, energy conversion, resource conservation and human health,” explains Khershed Cooper, a CMMI program director.

“The center creates fabrication tools that are enabling versatile and high-rate continuous processes for the manufacture of nanostructures that are systematically integrated into higher order structures using bottom-up and top-down techniques,” Cooper says. “For example, CHM is designing and building continuous, roll-to-roll nanofabrication systems that can print, in high-volume, 3-D nanostructures and multi-layer nanodevices at sub-100 nanometer resolution, and in the process, realize hybrid electronic-optical-mechanical nanosystems.”

The research was supported by NSF award #1025020, Nanoscale Science and Engineering Centers (NSEC): Center for Hierarchical Manufacturing.

Extremely thin, semi-transparent, flexible solar cells could soon become reality. At the Vienna University of Technology, Thomas Mueller, Marco Furchi and Andreas Pospischil have managed to create a semiconductor structure consisting of two ultra-thin layers, which appears to be excellently suited for photovoltaic energy conversion.

Several months ago, the team had already produced an ultra-thin layer of the photoactive crystal tungsten diselenide. Now, this semiconductor has successfully been combined with another layer made of molybdenum disulphide, creating a designer-material that may be used in future low-cost solar cells. With this advance, the researchers hope to establish a new kind of solar cell technology.

The solar cell's layer system: two semiconductor layers in the middle, connected to electrodes on either side.

The solar cell’s layer system: two semiconductor layers in the middle, connected to electrodes on either side.

Two-Dimensional Structures

Ultra-thin materials, which consist only of one or a few atomic layers are currently a hot topic in materials science today. Research on two-dimensional materials started with graphene, a material made of a single layer of carbon atoms. Like other research groups all over the world, Thomas Mueller and his team acquired the necessary know-how to handle, analyse and improve ultra-thin layers by working with graphene. This know-how has now been applied to other ultra-thin materials.

“Quite often, two-dimensional crystals have electronic properties that are completely different from those of thicker layers of the same material”, says Thomas Mueller. His team was the first to combine two different ultra-thin semiconductor layers and study their optoelectronic properties.

Two Layers with Different Functions

Tungsten diselenide is a semiconductor which consists of three atomic layers. One layer of tungsten is sandwiched between two layers of selenium atoms. “We had already been able to show that tungsten diselenide can be used to turn light into electric energy and vice versa”, says Thomas Mueller. But a solar cell made only of tungsten diselenide would require countless tiny metal electrodes tightly spaced only a few micrometers apart. If the material is combined with molybdenium disulphide, which also consists of three atomic layers, this problem is elegantly circumvented. The heterostructure can now be used to build large-area solar cells.

When light shines on a photoactive material single electrons are removed from their original position. A positively charged hole remains, where the electron used to be. Both the electron and the hole can move freely in the material, but they only contribute to the electrical current when they are kept apart so that they cannot recombine.

To prevent recombination of electrons and holes, metallic electrodes can be used, through which the charge is sucked away – or a second material is added. “The holes move inside the tungsten diselenide layer, the electrons, on the other hand, migrate into the molybednium disulphide”, says Thomas Mueller. Thus, recombination is suppressed.

This is only possible if the energies of the electrons in both layers are tuned exactly the right way. In the experiment, this can be done using electrostatic fields. Florian Libisch and Professor Joachim Burgdörfer (TU Vienna) provided computer simulations to calculate how the energy of the electrons changes in both materials and which voltage leads to an optimum yield of electrical power.

Tightly Packed Layers

“One of the greatest challenges was to stack the two materials, creating an atomically flat structure”, says Thomas Mueller. “If there are any molecules between the two layers, so that there is no direct contact, the solar cell will not work.” Eventually, this feat was accomplished by heating both layers in vacuum and stacking it in ambient atmosphere. Water between the two layers was removed by heating the layer structure once again.

Part of the incoming light passes right through the material. The rest is absorbed and converted into electric energy. The material could be used for glass fronts, letting most of the light in, but still creating electricity. As it only consists of a few atomic layers, it is extremely light weight (300 square meters weigh only one gram), and very flexible. Now the team is working on stacking more than two layers – this will reduce transparency, but increase the electrical power.

The SEMI Strategic Materials Conference, held September 30–October 1 in Santa Clara, Calif., will examine the drivers for new materials and how they impact material suppliers and the value chain they serve. The theme this year is “Materials Matter — Enabling the Future of IC Fabrication and Packaging,” delving into the market opportunities, scaling challenges, and emerging solutions to meet the sub-20nm technology node production challenges. SMC is the only conference dedicated to exploring the synergies, trends and business opportunities in advanced electronic materials. The agenda includes presentations by market analysts, leading device manufacturers, as well as equipment and material suppliers.

The increasing semiconductor content in mobile, computing, entertainment, and transportation are driving demands for higher performance and lower power consumption. The IC industry today is moving beyond scaling as the primary driver and looking to new materials and architectures.  Candidate materials span the spectrum from fabricating non-planar transistor structures to reducing interconnect RC delays.  3D interconnect and multi-chip bonding are facilitating form factors for use in phones, tablets and devices encompassing the internet of things.   In this “Age of Materials,” SMC will discuss market opportunities, scaling challenges, emerging solutions and more to meet the constantly growing demands.

Matt Nowak, senior director, Global Operations Group at Qualcomm, offers the conference’s keynote with insights on the emergence of the Digital Sixth Sense: Opportunities that will drive consumer demand over the coming decades, and the associated adoption of new IC devices and electronic materials. Tim G. Hendry, VP, Technology & Manufacturing Group at Intel, will kick off the session “Supply Chain Challenges, Interdependence for Future Growth” with his keynote, “Delivering Complexity to Beyond the Leading Edge.”

Other companies presenting include: Air Products & Chemicals, Air Liquide Electronics, Dow Chemical, Edwards Vacuum, Entegris, GLOBALFOUNDRIES, Hilltop Economics, IBM, Intel, Linx Consulting, Lux Research, Matheson, Pall Corp, SAFC Hitech, Sandisk, Stanford University, Stifel Nicolaus, TechSearch International, TriQuint Semiconductor, and VLSI Research.

For the “advanced materials”-enabled microelectronics industry, the Strategic Materials Conference is a planning, forecasting, and business development necessity. Organized by the Chemical and Gas Manufacturers Group (CGMG), a SEMI Special Interest Group comprised of leading manufacturers, producers, packagers and distributors of chemicals and gases used in the microelectronics industry, SMC has provided valuable information and networking opportunities to materials and electronics industry professionals since 1995.

For the complete agenda, additional information and to register, visit the Strategic Materials Conference webpage atwww.semi.org/smc.  For information on SEMI, visit www.semi.org.