Category Archives: Materials and Equipment

Today, KLA-Tencor Corporation announced the Teron SL650, a new reticle quality control solution for IC fabs that supports 20nm design nodes and beyond. With 193nm illumination and multiple STARlight optical technologies, the Teron SL650 provides the sensitivity and flexibility required to assess incoming reticle quality, monitor reticle degradation and detect yield- critical reticle defects, such as haze growth or contamination in patterned and open areas. In addition, the Teron SL650’s industry-leading production throughput supports the fast cycle times required to qualify the increased number of reticles associated with advanced multi- patterning techniques.

“For IC manufacturers, understanding the reticle state is a central component of patterning process control as changes in reticle quality can have a devastating impact on every wafer printed,” said Yalin Xiong, Ph.D., vice president and general manager of the Reticle Products Division (RAPID) at KLA-Tencor. “With the Teron SL650, our team has incorporated state-of-the-art reticle inspection technologies on a compact platform suitable for the IC fab, producing a reticle quality control system with advanced sensitivity, high productivity and extendibility for future nodes. By monitoring incoming reticles for critical defects and identifying progressive defects and changes to the mask pattern during production, our Teron SL650 can help chipmakers protect device yield, performance and cycle time.”

The Teron SL650 supports a mix of reticle types within the fab by using STARlightSD and STARlightMD to produce superior defect capture and comprehensive inspection coverage on single- and multi-die reticles, respectively. Chipmakers can also use the innovative STARlightMaps technology to track reticle degradation over time and identify CD, film thickness, anti-reflective coating and other variations across the reticle—changes in reticle quality that can affect the lithographic process window or pattern printing. Moreover, the Teron SL650 is EUV-compatible, enabling early collaboration with IC manufacturers on in- fab EUV reticle inspection requirements.

Multiple Teron SL650 reticle inspection systems have been installed at foundry, logic, and memory manufacturers worldwide where they are being used for incoming quality check and re-qualification of reticles used in advanced IC manufacturing. To maintain the high performance and productivity demanded by leading-edge production, the Teron SL650 systems are backed by KLA-Tencor’s global comprehensive service network.

Mentor Graphics Corp. today announced that it has acquired Nimbic, Inc., a provider of Maxwell-accurate, 3D full-wave electromagnetic (EM) simulation solutions. Nimbic’s high-performance high-end simulation capability and ability to accurately calculate complex electromagnetic fields will expand and strengthen Mentor’s chip-package-board simulation portfolio.

“Nimbic’s world-class 3D electromagnetic simulation solutions for signal integrity, power integrity, and EMI (electromagnetic interference) analysis are used by numerous leaders in the electronics industry to address their enterprise-wide challenges for chip-package-board design,” said Raul Camposano, CEO, Nimbic, Inc. “Nimbic’s recognized solutions enable the industry to cope with increasingly higher-end complexity. We see joining Mentor Graphics as a natural fit with its own leadership in PCB and package systems design, global footprint, and extensive network of enterprise customers. We view this transaction as very positive for our customers, our employees, and the industry as a whole.”

“Mentor Graphics is already the recognized leader in PCB systems design with our flagship Xpedition flow and our HyperLynx solutions for signal integrity, power integrity, DRC and thermal analysis. Nimbic’s 3D electromagnetic simulation further enhances Mentor’s portfolio to solve the increasing complexity challenges that our customers face,” said Henry Potts, vice president and general manager of the Mentor Graphics Systems Design Division. “Mentor is committed to providing simulation solutions from entry-level to advanced, including IC package and package co-design. The addition of Nimbic further extends Mentor’s leadership in systems design simulation and is a valuable addition to our offerings already provided through Xpedition.”

The 17th annual IITC will be held May 21 – 23, 2014 in conjunction with the 31st AMC at the Doubletree Hotel in San Jose, California, representing an annual series of meetings devoted to leading-edge research in the field of advanced metallization and 3D integration for ULSI IC applications. It will be preceded by a day-long workshop on “Manufacturing of Interconnect Technologies: Where are we now and where do we go from here?” today, Tuesday, May 20.

The 2014 IITC/AMC will focus on innovative developments in the critically important field of interconnections for electronic systems, presenting papers on all aspects of interconnects for device, circuit board and system-level applications. Topics include both fundamental and applied research, as well as issues related to introduction of enabling technologies into manufacturing. This year’s conference intends to provide a forum for open discussions ranging from basic science to industrial application, targeting material scientists, process and integration engineers and PhD students active in the areas of semiconductor processing, advanced materials, equipment development, and interconnect systems.

CLICK HERE TO LAUNCH SLIDESHOW

Further details are available at the conference website: http://www.ieee.org/conference/iitc

BASF today inaugurated a new Electronic Materials Sampling and Development facility in Hillsboro, Oregon. The new facility is a strategic step towards establishing a North American footprint to supply materials for semiconductor manufacturing applications related to the electronics industry.

The new facility will manufacture prototype materials, offer research and development (R&D) support for the development of new products and technologies and will provide higher flexibility for customer sampling, reduce supply chain complexity and enable “just-in-time-delivery” of samples. The center is one of four other BASF global facilities established to extend BASF’s position as the leading supplier into consumer electronics and the semiconductor industries.

“The new sampling and development center allows us to work closely with our customer base, creating innovation through chemistry to help grow the electronics materials industry while strengthening our partnerships with key tech hubs,” said Lothar Laupichler, Senior Vice President, Electronics Materials, BASF SE.

BASF is a supplier of electronic materials, offering a specialized portfolio of high purity and quality process chemicals as well as dedicated solutions for a range of applications for the electronics industry.

University of California, Berkeley researchers sponsored by Semiconductor Research Corporation (SRC) are pursuing a novel approach to 3D device integration that promises to lead to advanced mobile devices and wearable electronics featuring increased functionality in more low-profile packages.

The research focuses on integrating extra layers of transistors on a vertically integrated 3D monolithic chip using printing of semiconductor “inks” as compared to the current method of chip-stacking through 3D interconnect solutions.

The new process technology could help semiconductor manufacturers develop smaller and more versatile components that are less expensive and higher performing by enabling cost-effective integration of additional capabilities such as processing, memory, sensing and display. The low-temperature process is also compatible with polymer substrates, enabling potential new applications in wearable electronics and packaging.

Current efforts on 3D integration have used transfer of thin single crystal semiconductor layers, polycrystalline silicon deposited by chemical vapor disposition, or other growth techniques to realize integrated devices.

“Compared to these approaches, we believe our approach is simpler and potentially with significantly lower cost,” said Vivek Subramanian, professor of Electrical Engineering and Computer Sciences at UC Berkeley. “Our goal in this work is to maximize performance, with the hope that this will make the cost versus performance tradeoff worthwhile relative to other approaches.”

Specifically, the UC Berkeley team is developing directly-printed transparent oxide transistors as a path to realizing additional layers of active devices on top of CMOS metallization.

To fabricate such devices, new material and process methodologies are needed for depositing nanoparticles for semiconductors, dielectrics and conductors. The research is particularly focused on solution-based processing due its low temperature compatibility with CMOS metallization as well as the potential for lower cost manufacturing.

“Initial results from the Berkeley team show that reasonably high performance can be obtained from ink-jet printed devices with process temperatures that are compatible with post-CMOS metallization, thus enabling a new route to monolithic 3D integration,” said Bob Havemann, Director of Nanomanufacturing Sciences at the SRC.

CORRECTION: In a previous version of this article, the headline read “Zeta Instruments hires former KLA-Tencor exec as new CEO.” This information is incorrect – Jeff Donnelly has joined the company as COO. The headline has been changed to reflect this. Solid State Technology regrets the error.

Zeta Instruments, Inc., an optical profiling and inspection company providing solutions for high-tech manufacturing, has announced that Jeff Donnelly has joined the company as its chief operating officer.

Donnelly’s distinguished career spans executive roles at startups and established tech leaders, and is most recently capped by a 15-year tenure at KLA-Tencor. Reporting to the CEO as group vice president of the Growth and Emerging Markets Group, Donnelly was responsible for driving KLA-Tencor’s growth in multiple sectors including the LED and back-end semiconductor markets, and he played a central role in the company’s mergers and acquisitions.

“We are thrilled to have Jeff join the Zeta team. The two of us have a long history of working together developing new products and entering new markets,” said Rusmin Kudinar, CEO and founder of Zeta Instruments. “In addition to being a seasoned public company executive, Jeff is a proven entrepreneur with a demonstrated track record of delivering innovative products, launching new companies and leading mergers and acquisitions. He is the right person at the right time to help take Zeta to the next level.”

Commenting on his arrival, Donnelly stated, “I am excited to join the Zeta team. With several industry-leading products under its belt and strong traction among a blue-chip customer base, Zeta is poised for significant growth. These are some of the most talented people I’ve had the privilege to work with, and I look forward to playing an integral role as we deliver on the company’s full potential.”

Donnelly holds a Bachelor of Science degree in chemical engineering from California State Polytechnic University, Pomona and a Master’s in Business Administration from Stanford University. He has also served as a nuclear engineering officer in the U.S. Navy.

Graphene not all good


April 29, 2014

In a first-of-its-kind study of how a material some think could transform the electronics industry moves in water, researchers at the University of California, Riverside Bourns College of Engineering found graphene oxide nanoparticles are very mobile in lakes or streams and therefore likely to cause negative environmental impacts if released.

Graphene oxide nanoparticles are an oxidized form of graphene, a single layer of carbon atoms prized for its strength, conductivity and flexibility. Applications for graphene include everything from cell phones and tablet computers to biomedical devices and solar panels.

The use of graphene and other carbon-based nanomaterials, such as carbon nanotubes, are growing rapidly. At the same time, recent studies have suggested graphene oxide may be toxic to humans.

Jacob D. Lanphere, left, and Corey Luth, work in the lab of their advisor Sharon Walker.
Jacob D. Lanphere, left, and Corey Luth, work in the lab of their advisor Sharon Walker.

As production of these nanomaterials increase, it is important for regulators, such as the Environmental Protection Agency, to understand their potential environmental impacts, said Jacob D. Lanphere, a UC Riverside graduate student who co-authored a just-published paper about graphene oxide nanoparticles transport in ground and surface water environments.

“The situation today is similar to where we were with chemicals and pharmaceuticals 30 years ago,” Lanphere said. “We just don’t know much about what happens when these engineered nanomaterials get into the ground or water. So we have to be proactive so we have the data available to promote sustainable applications of this technology in the future.”

The paper co-authored by Lanphere, “Stability and Transport of Graphene Oxide Nanoparticles in Groundwater and Surface Water,” was published in a special issue of the journal Environmental Engineering Science.

Other authors were: Sharon L. Walker, an associate professor and the John Babbage Chair in Environmental Engineering at UC Riverside; Brandon Rogers and Corey Luth, both undergraduate students working in Walker’s lab; and Carl H. Bolster, a research hydrologist with the U.S. Department of Agriculture in Bowling Green, Ky.

Walker’s lab is one of only a few in the country studying the environmental impact of graphene oxide. The research that led to the Environmental Engineering Science paper focused on understanding graphene oxide nanoparticles’ stability, or how well they hold together, and movement in groundwater versus surface water.

The researchers found significant differences.

In groundwater, which typically has a higher degree of hardness and a lower concentration of natural organic matter, the graphene oxide nanoparticles tended to become less stable and eventually settle out or be removed in subsurface environments.

In surface waters, where there is more organic material and less hardness, the nanoparticles remained stable and moved farther, especially in the subsurface layers of the water bodies.

The researchers also found that graphene oxide nanoparticles, despite being nearly flat, as opposed to spherical, like many other engineered nanoparticles, follow the same theories of stability and transport.

The research is supported by Lanphere’s National Science Foundation Graduate Research Fellowship; a NSF grant received by the UC Center for Environmental Implications for Nanotechnology, of which Walker is a member; and an NSF Career Award and US Department of Agriculture Hispanic Serving Institution grant, both received by Walker.

Tessera Technologies, Inc. announced today that Invensas Corporation and South Korea-based STS Semiconductor & Telecommunications, a semiconductor assembly and test solution provider, have entered into an agreement to validate high volume manufacturing capability for Invensas’ Bond Via Array (BVATM) technology for next generation smartphone and tablet customers.

BVA is a proven advanced package-on-package (PoP) technology for System on Chip (SOC) and memory integration in mobile devices. Styled as a “Bridge Technology to 3DIC,” it is a unique solution that utilizes established wire-bond assembly techniques to enable low power and high-bandwidth (1000 IO+) packaging in an ultra-small form factor, ideal for mobile devices. STS’s state of the art engineering and worldwide high-volume capabilities provide an ideal platform for high volume manufacturing of BVA.

“We are delighted to partner with Invensas on BVA,” stated Chang-Bum Shim, Chief Operating Officer and Executive Vice President for STS. “STS understands the critical need to increase interconnect bandwidth for the growing Package-on-Package mobile SOC market, without increasing product size or the cost to the end user. Our engineering and manufacturing capabilities are ideally suited to the commercialization of BVA.”

“STS is an ideal partner for BVA,” said Simon McElrea, CTO of Tessera Technologies, Inc. and President of Invensas. “Their continual investment in cutting-edge packaging technology and associated manufacturing capability, coupled with their growth model in mobile and communication devices, is perfectly aligned for BVA commercialization.”

Altera Corporation and TSMC today announced the two companies have worked together to bring TSMC’s patented, fine-pitch copper bump-based packaging technology to Altera’s 20 nm Arria 10 FPGAs and SoCs. Altera is the first company to adopt this technology in commercial production to deliver improved quality, reliability and performance to Altera’s 20nm device family.

“TSMC has provided a very advanced and robust integrated package solution for our Arria 10 devices, the highest-density monolithic 20nm FPGA die in the industry,” said Bill Mazotti, vice president of worldwide operations and engineering at Altera. “Leveraging this technology is a great complement to Arria 10 FPGAs and SoCs and helps us address the packaging challenges at the 20nm node.”

TSMC’s leading-edge flip chip BGA package technology provides Arria 10 devices with better quality and reliability than standard copper bumping solutions through the use of fine-pitch copper bumps. The technology is able to accommodate very high bump counts as required by high-performance FPGA products. It also provides excellent bump joint fatigue life, improved performance in electro-migration current and low stress on the ELK (Extra Low-K) layers, all highly critical features for products employing advanced silicon technologies.

“TSMC’s copper bump-based package technology provides excellent value for small bump pitch (<150um) advanced silicon products featuring ELK,” said David Keller, senior vice president, business management, TSMC North America. “We are pleased that Altera is adopting this highly integrated packaging technology.”

Altera is shipping Arria 10 FPGAs based on TSMC 20SoC process technology and featuring this innovative packaging technology.  Arria 10 FPGAs and SoCs provide the FPGA industry’s highest density in a single monolithic die and up to 40 percent lower power than the previous 28nm Arria family.

TSMC’s copper bump-based package technology is scalable and ideal for products that feature large die size and small bump pitch. It includes a DFM/DFR implementation from TSMC that adjusts package design and structure for wider assembly process windows and higher reliability. The technology has demonstrated better than 99.8 percent production-level assembly yields.

With the SOI business decreasing, the 3D TSV stack beginning, and the competitive environment changing with EV Group, Applied Materials, Tokyo Electron and many new entrants. Yole Développement analyzes the permanent bonding market & technology trends and announces today its new study: Permanent Wafer Bonding report.

Permanent bonding technology is a key process for a wide range of applications in the semiconductor industry such as MEMS, advanced packaging, LED devices, and SOI substrate applications.

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“These have been the 4 main leading applications for permanent bonding for several years. Permanent bonding processes are increasingly more importance within the semiconductor industry”, announces Amandine Pizzagalli, Technology & Market Analyst, Advanced Packaging & Manufacturing, Yole Développement (Yole).

Under this Permanent Wafer Bonding report, Yole’s analysts give an overview of technical characteristics for each existing permanent bonding processes and related applications. They review key technical insight into future permanent bonding technologies trends and challenges. Yole’s experts also analyze the market trends and provide a clear mapping of this industry including market metrics & dynamic from 2013 and 2019.

The permanent bonding market is evolving, and currently dominated and fragmented by three main permanent bonding equipment suppliers: EV Group, SUSS MicroTec, and Tokyo Electron.
“These three vendors today account for almost 80 percent of the permanent bonding equipment market by focusing on MEMS and Advanced Packaging applications including BSI CMOS Image Sensors, CIS capping WLP, and 3D stack TSV,” ensures Amandine Pizzagalli, from Yole Développement.

EV Group is still the market leader in permanent bonding technology with more than 70 percent of market share, but will be challenged by the merging of Tokyo Electron and Applied Materials, two of the largest semiconductor equipment suppliers in the world.

The entrance of aggressive new players is likely to challenge established players in the permanent bonding market:

  • Some players have recently entered the market with low barriers of entry such as Mitsubishi Heavy Industry; mainly with customers involved in the R&D sector.
  • Other big equipment suppliers have created a challenging environment and stimulate technology innovation for further improvements in the advanced packaging area.
  • Tokyo Electron has gained more market share in 2013 from permanent bonding technologies – with significant market share achieved due to their deep involvement in 3D TSV stack bonding technology performed at room temperature.

    The merger of Tokyo Electron and Applied Materials questions the involvement of permanent bonding equipment suppliers in future development.
    In parallel, SUSS MicroTec, who provided automatic bonders for production for 10 years, stopped making them in 2013. This demonstrates that the permanent bonding market is very challenging. This big change in the permanent bonding market environment will create a new battle in this field, which is going to be very interesting in the next five years.

    Yole Développement’s report provides an in-depth competitive analysis of key permanent bonding equipment suppliers, with profiles of the main equipment vendors, and their future in the permanent bonding market. More info. on www.i-micronews.com, reports section.