Category Archives: Materials and Equipment

Tatsuo Enami Executive Officer & General Manager of Sales, Gigaphoton, Inc.

Green is the color for the decade and future decades as each country is developing its own standards for energy consumption and implementing its green initiatives. At one time considered a passing trend, green initiatives are now mandatory and force manufacturers to not only maintain corporate responsibility, but to positively impact the bottom line. As a result, high-volume manufacturers must work with vendors and suppliers that will help enable their overall cost and green manufacturing goals. Tracking and managing total operational costs is critical for sustaining a cost-effective, high-volume manufacturing (HVM) environment. Effective partners are already engaged in and developing systems on ‘green’ platforms using technology and services that balance performance with environmental impact, all within the barriers of cost. It includes companies that are designing systems using innovative techniques and new technologies that not only reduce the cost of energy, but also look at ways to reduce the cost of consumables, and the cost of downtime for HVM. By taking a total cost-of-operation approach when considering vendors and suppliers in a green manufacturing strategy, the resulting energy and environmental improvements can significantly lower fab operating costs.

When considering light sources, the power consumption of excimer lasers will continue to increase, as high-power lasers grow in demand especially for 450-mm processes, it has increased 4.5x over the past 6 years. As these processes gear up for HVM, the environmental impact cannot be ignored. The estimated cost for utilities for lasers, which includes electricity consumption, gas consumption and heat management, will be approximately 30% of the total cost-of-operation. Clearly, reducing utility costs is critical. As a result, the true value of a laser for HVM weighs heavily on its effectiveness in controlling utility costs. To address this issue, several companies are working to find solutions. Gigaphoton is currently developing a new hybrid laser system that utilizes a solid-state laser chamber. This system will require a maximum power of only 36kW compared to 60kW on the current system. When considering costs, the use of a hybrid laser system for HVM can result in approximately 40% less overall power consumption from the laser system alone. As there are others in development by other companies, this is an example of one solution that is in development to reduce energy and help enable HVM.

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Keep in mind, a successful partner in your green manufacturing strategy will develop wider technology solutions that also include reducing the cost of consumables and the cost of downtime. Companies that have invested time and considerable resources to develop eco-friendly systems will provide the most effective all-around solutions. For example, to further reduce the overall cost-of-operation and maintenance, determine if your potential partner has a roadmap to develop longer-life consumables, or develop a system that removes some of the consumables all together. In the case with hybrid lasers, this would be the Line-Narrowing Module (LNM) and the Enhanced Front Mirror (EFM). Gas is another consumable that also affects downtime. New techniques for system optimization have been developed that reduce the amount of gas needed by 50% and minimize the down time for maintenance by half compared to existing laser systems.

There are many companies that are working to provide ‘green’ solutions for its customer. Gigaphoton has been leading the ‘green’ concept since 2007. By working with our customers to identify technology, performance and cost models for HVM, Gigaphoton has developed the EcoPhoton program. When considering a green manufacturing strategy for HVM, to significantly reduce the overall cost-of-operation partner companies need to provide solutions that reduce energy consumption, and also a roadmap to develop longer-life consumables, gas modules with less volume and refill requirements, all of which contribute to minimizing down time for maintenance. The right partner can make the environment greener as well as your bottom line. •

The market for semiconductor packaging materials, including thermal interface materials, is expected to maintain its $20 billion value through 2017, despite shifts away from the use of precious metals such as gold in wire bonding, according to a new study by SEMI and TechSearch International.  Despite continued price pressure, organic substrates remain the largest segment of the market, worth an estimated $7.4 billion globally in 2013 growing to more than $8.7 billion by 2017. Most packaging material segments are encountering low revenue growth as end users seek lower cost solutions for packaging and downward pricing pressures are severe. In addition, the transition to copper and silver bonding wire has significantly reduced impact of gold metal pricing in wire bond packages.

The SEMI report, titled “Global Semiconductor Packaging Materials Outlook—2013/2014 Edition,” covers laminate substrates, flex circuit/tape substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics and thermal interface materials.

Several areas are experiencing stronger growth. The expansion of CSPs with laminate substrates is driven by explosive growth in mobile computing and communications devices such as smartphones and tablets.  The same products are driving growth in wafer level packages (WLPs), which are in turn driving use of dielectric materials used for redistribution.  The growth in flip chip adoption continues to expand the market for underfill materials.  A number of key segments are seeing a consolidation of the supplier base, though new entrants in Asia are entering some segments.

Semiconductor Packaging Materials Segment Estimate of 2013Global Market

($M)
Organic Substrates

$7,408
Leadframes

$3,342
Bonding Wire

$4,455
Mold Compounds

$1,394
Underfill Materials

$208
Liquid Encapsulants

$849
Die Attach Materials

$665
Solder Balls

$280
Wafer Level Package Dielectrics

$94
Thermal Interface Materials

$620

 

The findings in the report are based on more than 150 in-depth interviews conducted with packaging subcontractors, semiconductor manufacturers and materials suppliers.  It includes previously unpublished data on revenue, unit shipments and market shares for each packaging material segment; a five-year forecast of revenue and units (2012-2017); supplier rankings (for key segments) and listing (including new players); and an analysis of regional market trends and size.

The report also identifies important technology and business trends affecting the packaging materials market, as well as opportunities for suppliers. Some of the key opportunities include:

  • Thinner substrates for packages in mobile products and leading-edge CSP substrates to handle fine bump pitch of ≤110 µm
  • Alternatives to the typical epoxy or acrylic resin for thermal interface materials, including filler technologies such as carbon nanotubes or new approaches using graphene
  • Softer Pd-coated copper wire for circuit under pad applications
  • Low moisture level sensitivity mold compounds and encapsulants for bare copper and silver alloy wire
  • Die attach film materials with thickness 10 µm and under
  • No-flow underfill materials
  • Continued trend of Pb-free solder balls for BGAs and CSPs, smaller diameter balls for WLP
  • Wafer-level package dielectrics with low temperature cure, lower dielectric constant, and lower cost

This information was derived from the SEMI Global Semiconductor Packaging Materials Outlook—2013-2014 Edition (www.semi.org/en/node/45446).

Slide 14-1 Slide 14-2 Slide 14-3

High density fin formation is one of the most critical processes in the FinFET device fabrication flow. Given that a typical device is composed of an ensemble of fins, each fin must be nearly identical to avoid performance degradation arising from geometric variation. Thus, techniques for fin patterning must demonstrate the ability to form fins with a high degree of structural precision.

IBM researchers will discuss the use of directed self-assembly using block copolymers (BCP) and 193nm immersion (193i) lithography as a suitable way to make the fins of FinFETs for beyond the 10 nm node. Essentially, a topographic template pattern was created on a chemically neutral surface. Confinement of the BCP between the sidewalls of the template provides an ordering force that drives the pattern into registry with the surface topography. Electrical data produced from fins with a 29-nm pitch patterned with this approach showed good uniformity, with no signs of gross variation in critical dimensions.

(Paper#32.1, “Electrical Characterization of FinFET with Fins Formed by Directed Self Assembly at 29 nm Fin Pitch Using a Self-Aligned Fin Customization Scheme,” H. Tsai et al, IBM)

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Dongbu HiTek today announced that it has begun volume production of 5.0 Megapixel (5M) CMOS Image Sensor (CIS) devices for Superpix Micro Technology Co., Ltd., a fabless customer based in Beijing. Armed with patented SuperPix pixel signal processing and SuperImage image processing techniques, Superpix anticipates strong demand for its 5M CIS devices in China’s rapidly expanding mid-range to low-end smart phone market segments.

According to Maybank, the Chinese smart phone market in the mid-range to low-end segment is forecast to grow from some 216 million units shipped this year to about 400 million units in 2015, thereby exceeding 85% growth over the two year period. In another forecast from iSuppli, smart phones that feature 5M resolution and above will substantially command this segment’s growth as they replace 2M resolution cameras, shipping 187 million units next year and 288 million units in 2015, thus representing a dramatic year-over year growth of more than 50%.

“We continue to expand our foundry relationship with Superpix, and are now on track to begin developing its 8M CIS chips early next year so that volume production can also begin next year,” said Jae Song, Dongbu HiTek EVP of marketing. He noted that his company’s foundry relationship with Superpix has progressively developed from manufacturing QVGA/VGA chips to CIS chips specifying resolutions spanning the 2M–to-8M range.

The Korean specialty foundry continues to manufacture an expanding portfolio of advanced chips for its Chinese customers; this portfolio currently includes CIS devices, touch-screen controllers and power management chips.

GLOBALFOUNDRIES today unveiled details of a project that demonstrates the value of its open and collaborative approach to delivering next-generation chip packaging technologies. The company, in partnership with Open-Silicon (chief architect) and Amkor Technology, Inc. (assembly and test), jointly exhibited a functional system-on-chip (SoC) solution featuring two 28nm logic chips, with embedded ARM processors, connected across a 2.5D silicon interposer. The jointly developed design is a test vehicle that showcases the benefits of 2.5D technology for mobile and low-power server applications and the viability of the Foundry 2.0 collaborative enablement model.

While some semiconductor manufacturers are approaching next-generation packaging technologies through internal development, GLOBALFOUNDRIES is enabling an open supply chain through collaboration with ecosystem partners and customers. This approach allows GLOBALFOUNDRIES’ customers to choose their preferred supply chain partners, while leveraging the experience of ecosystem partners who have developed deep expertise in design, assembly and test methodologies. When combined with GLOBALFOUNDRIES’ leading-edge manufacturing capabilities, this open and collaborative model is expected to deliver lower overall cost and less risk in bringing 2.5D technologies to market.

“As the fabless-foundry business model evolves to address the realities of today’s dynamic market, foundries are taking on increasing responsibility for enabling the supply chain to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs,” said David McCann, vice president of packaging R&D at GLOBALFOUNDRIES. “To help address these challenges, we are driving our ‘Foundry 2.0’ collaborative supply chain model by engaging early with ecosystem partners like Open-Silicon and Amkor to jointly develop solutions that will enable the next wave of innovation in the industry.”

The test vehicle features two ARM Cortex-A9 processors manufactured using GLOBALFOUNDRIES’ 28nm-SLP (Super Low Power) process technology. The processors are attached to a silicon interposer, which is built on a 65nm manufacturing flow with through-silicon-vias (TSVs) to enable high-bandwidth communication between the chips.

Open-Silicon provided the processor, interposer, substrate, and test design, as well as the test and characterization of the final product. GLOBALFOUNDRIES provided the PDKs, interposer reference flow and manufactured both the 28nm ARM processors and the 65nm silicon interposer with embedded TSVs. Amkor provided the package-related design rules and manufacturing processes for back-side integration, copper pillar micro-bumping, and 2.5D product assembly. GLOBALFOUNDRIES and Amkor collaborated closely throughout the project to develop and validate the design rules, assembly processes, and required material sets.

The companies demonstrated first-time functionality of the processor, interposer, and substrate designs, and the die-to-substrate (D2S) process used by the supply chain resulted in high yields. The design tools, process design kit (PDK), design rules, and supply chain are now in place and proven for 2.5D interposer products from GLOBALFOUNDRIES, Amkor, and Open-Silicon.

“This project is a testament to the value of an open and collaborative approach to innovation, leveraging expertise from across the supply chain to demonstrate progress in bringing a critical enabling technology to market,” said Ron Huemoeller, senior vice president of advanced product development at Amkor Technology. “This collaborative model will offer chip designers a flexible approach to 2.5D SoC designs, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.”

“We are pleased to be at the forefront of making 2.5D a reality with our foundry and OSAT partners,” said Dr. Shafy Eltoukhy, vice president of technology development at Open-Silicon. “This approach will allow designers to choose the right technology for each function of their SoC while simultaneously enabling finer grain and lower power connectivity than traditional packaging solutions along with reduced power budgets for next-generation electronic devices.”

STMicroelectronics and Yogitech, a provider of functional safety solutions, have signed an agreement to create a comprehensive package that will simplify the development and certification of safety-critical applications based on STM32 microcontrollers.

ST and Yogitech have agreed to develop a safety manual and software test libraries as a simple, quick, and effective means of detecting and flagging potentially dangerous failures in STM32 designs using tailored development tools from IAR Systems. Directed at a market estimated at over EURO400 million in Europe alone, the initiative aims at allowing engineers to choose from over 500 ST microcontrollers to create innovative and safe industrial products for factory-automation applications.

“The complexity of modern integrated circuits is such that the adoption of a black-box approach for safety analysis is no longer an option,” said Silvano Motto, CEO of Yogitech. “The development of the STM32 safety package takes advantage of fRMethodology, our patented white-box approach to address functional safety analyses of integrated circuits approved by T&Uuml;V S&Uuml;D and by many lead companies in multiple application domains like industrial and automotive.”

“Achieving stringent functional-safety certification on systems where STM32 is the main microcontroller is a very popular request within our industrial customer base,” said Jacky Perdrigeat, EMEA Marketing Vice President for Microcontrollers, STMicroelectronics. “The cooperation with Yogitech sets to speed up time-to-market for critical safety applications, strengthening our offering for the industrial- and factory-automation markets, which are key segments for the STM32 product family.”

The market-proven 32-bit STM32 ARM(R) Cortex(TM)- M microcontrollers combine high performance, real-time capabilities, digital signal processing, and low-power, low-voltage operation, while maintaining ease of development and extensive compatibility between devices, families and software.

FlipChip International announced today the 100% acquisition of Millennium Microtech (Shanghai) – (MMS), a provider of fully integrated semiconductor packaging and testing services situated in the Zhang Jiang Hi- Tech Park, Pudong New Area, Shanghai, China. The MMS name will be changed to FlipChip International.

FCI acquired a majority shareholding in MMS in July 2012 and have since worked diligently with the Chinese authorities over the intervening period to acquire the remaining shares. With 100% ownership of MMS, FCI also gains full ownership of the Joint Venture Bumping facility FCMS. Full ownership will allow FCI to further develop our Shanghai facility with transferred technologies in WLCSP and embedded die technology from FCI Phoenix. These will include our ChipsetT embedded die technology, our Spheron WLCSP, and our plated copper Spheron WLCSP processes.

The strategic 100% acquisition of MMS has extended the global footprint of FCI to offer existing and new customers turnkey services including wafer and final test. FlipChip International will offer the optimum technology for the coming generations of packaging required in the smart phone, tablet, medical and automotive industries. FlipChip International will also provide a complete range of packaging and testing services in Asia to complement the existing bumping and Wafer level Packaging services already associated with FCI in Phoenix, Arizona.

David Wilkie the FCI President and CEO said, “The acquisition of MMS and FCMS is an important part of FlipChip International’s plan to grow the Asian portion of our advanced packaging business. In our class 100 Shanghai bump facility we will add increasingly complex wafer bumping technologies, and offer our Asian customers improved cycle times due to the location near many wafer foundries. Our high volume capability will enable FCI to further develop advanced IC packaging solutions such as Spheron WLCSP and ChipsetT, while still supporting more traditional IC package assembly and test.”

Fabless semiconductor company DecaWave announced today its first single chip of the ScenSor wireless technology family, DW1000, which makes indoor location and communications more accurate, cost-effective and power-efficient than ever before. This is the first integrated circuit on the market to electronically identify the specific distance to any object, person or thing with +/-10cm precision.

With multiple patents, DecaWave’s ScenSor works by transmitting wireless signals to readers that use them to locate the tagged object to within 10cm. The chip is the smallest device of its class, is compliant with IEEE 802.15.4a standards (now IEEE802.15.4-2011), and uses ultra-low power – it can operate several years from a battery cell or within an energy harvesting environment.  These features make the chip functionally and economically viable to deploy, both in volume and in remote locations.

“Until now, 10cm location communications across close distances was not possible and current systems with meter-level accuracy have limited reliability, signals would be lost and there was a high risk for error,” said Ciaran Connell, CEO at DecaWave. “Customers ask for more than average accuracy most of the time. Our new ScenSor chip changes all that, it provides unprecedented accuracy all the time. More than 1,800 firms and institutes have expressed interest in implementing our technology for applications such as factory and building automation, agriculture, healthcare, ePOS and retail, and warehousing. We’ve created a foundation for all locator systems, and the systems can now be tailored to specific applications and environments.”

ScenSor can either replace or complement the Radio Frequency Identification (RFID) and WiFi technology currently used for indoor tracking (where GPS signals are unavailable) by allowing for more specific, minute-to-minute location information for high-value goods over short range and through obstructions providing more accuracy than ever before. This brings new opportunities across multiple industries including future applications for the technology incorporated in smartphones and tablets.

“TCS has for many years been developing equipment and devices using UWB,” said Serge Hethuin, head of secured wireless products at THALES Communications & Security. “TCS has compared the different waveforms that could be qualified has such. It became obvious that the solution proposed by DecaWave was the best suited one in order to satisfy the demanding applications under consideration. TCS has monitored DecaWave’s IC development progress over time, giving evaluation feedback and highlighting application requirements and needs. And today the performance of the DecaWave IC is exceptional and undisputable. TCS focus applications are related to indoor location in urgency situations dealing with different environment types and especially those in severe non line-of-sight conditions, for which multipath fading is a primary concern. The results achieved with the DecaWave IC are particularly good.”

Columbia Engineering researchers have experimentally demonstrated for the first time that it is possible to electrically contact an atomically thin two-dimensional (2D) material only along its one-dimensional (1D) edge, rather than contacting it from the top, which has been the conventional approach. With this new contact architecture, they have developed a new assembly technique for layered materials that prevents contamination at the interfaces, and, using graphene as the model 2D material, show that these two methods in combination result in the cleanest graphene yet realized. The study is published in Science on November 1, 2013.

“This is an exciting new paradigm in materials engineering where instead of the conventional approach of layer by layer growth, hybrid materials can now be fabricated by mechanical assembly of constituent 2D crystals,” says Electrical Engineering Professor Ken Shepard, co-author of the paper. “No other group has been able to successfully achieve a pure edge-contact geometry to 2D materials such as graphene.”

He adds that earlier efforts have looked at how to improve ‘top contacts’ by additional engineering such as adding dopants: “Our novel edge-contact geometry provides more efficient contact than the conventional geometry without the need for further complex processing. There are now many more possibilities in the pursuit of both device applications and fundamental physics explorations.”

First isolated in 2004, graphene is the best-studied 2D material and has been the subject of thousands of papers studying its electrical behavior and device applications. “But in nearly all of this work, the performance of graphene is degraded by exposure to contamination,” notes Mechanical Engineering Professor James Hone who is also a co-author of the study. “It turns out that the problems of contamination and electrical contact are linked. Any high-performance electronic material must be encapsulated in an insulator to protect it from the environment. Graphene lacks the ability to make out-of-plane bonds, which makes electrical contact through its surface difficult, but also prevents bonding to conventional 3D insulators such as oxides. Instead, the best results are obtained by using a 2D insulator, which does not need to make bonds at its surface. However, there has been no way to electrically access a fully-encapsulated graphene sheet until now.”

In this work, says Cory Dean, who led the research as a postdoc at Columbia and is now an assistant professor at The City College of New York, the team solved both the contact and contamination problems at once. “One of the greatest assets of 2D materials such as graphene is that being only one atom thick, we have direct access to its electronic properties. At the same time, this can be one of its worst features since this makes the material extremely sensitive to its environment. Any external contamination quickly degrades performance. The need to protect graphene from unwanted disorder, while still allowing electrical access, has been the most significant roadblock preventing development of graphene-based technologies. By making contact only to the 1D edge of graphene, we have developed a fundamentally new way to bridge our 3D world to this fascinating 2D world, without disturbing its inherent properties. This virtually eliminates external contamination and finally allows graphene to show its true potential in electronic devices”

The researchers fully encapsulated the 2D graphene layer in a sandwich of thin insulating boron nitride crystals, employing a new technique in which crystal layers are stacked one-by-one. “Our approach for assembling these heterostructures completely eliminates any contamination between layers,” Dean explains, “which we confirmed by cross-sectioning the devices and imaging them in a transmission electron microscope with atomic resolution.”

Once they created the stack, they etched it to expose the edge of the graphene layer, and then evaporated metal onto the edge to create the electrical contact. By making contact along the edge, the team realized a 1D interface between the 2D active layer and 3D metal electrode. And, even though electrons entered only at the 1D atomic edge of the graphene sheet, the contact resistance was remarkably low, reaching 100 Ohms per micron of contact width—a value smaller than what can be achieved for contacts at the graphene top surface.

With the two new techniques—the contact architecture through the 1D edge and the stacking assembly method that prevents contamination at the interfaces—the team was able to produce what they say is the “cleanest graphene yet realized.” At room temperature, these devices exhibit previously unachievable performance, including electron mobility at least twice as large as any conventional 2D electron system, and sheet resistivity less than 40 Ohms when sufficient charges are added to the sheet by electrostatic “gating.” Amazingly, this 2D sheet resistance corresponds to a “bulk” 3D resistivity smaller than that of any metal at room temperature. At low temperature, electrons travel through the team’s samples without scattering, a phenomenon known as ballistic transport. Ballistic transport, had previously been observed in samples close to one micrometer in size, but this work demonstrates the same behavior in samples as large as 20 micrometers. “So far this is limited purely by device size,” says Dean, “indicating that the true ‘intrinsic’ behavior is even better.

The team is now working on applying these techniques to develop new hybrid materials by mechanical assembly and edge contact of hybrid materials drawing from the full suite of available 2D layered materials, including graphene, boron nitride, transition metal dichlcogenides (TMDCs), transition metal oxides (TMOs), and topological insulators (TIs). “We are taking advantage of the unprecedented performance we now routinely achieve in graphene-based devices to explore effects and applications related to ballistic electron transport over fantastically large length scales,” Dean adds. “With so much current research focused on developing new devices by integrating layered 2D systems, potential applications are incredible, from vertically structured transistors, tunneling based devices and sensors, photoactive hybrid materials, to flexible and transparent electronics.”

“This work results from a wide collaboration of researchers interested in both pure and applied science,” says Hone. “The unique environment at Columbia provides an unparalleled opportunity for these two communities to interact and build off one another.”

The Columbia team demonstrated the first technique to mechanically layer 2D materials in 2010. These two new techniques, which are critical advancements in the field, are the result of interdisciplinary efforts by Lei Wang (PhD student, Electrical Engineering, Hone group) and Inanc Meric (Postdoc, Electrical Engineering, Shepard group), co-lead authors on this project who worked with the groups of Philip Kim (Physics and Applied Physics and Applied Mathematics, Columbia), James Hone (Mechanical Engineering, Columbia), Ken Shepard (Electrical Engineering, Columbia) and Cory Dean (Physics, City College of New York).

SMT equipment market continues to derive demand from major downstream industry segments including telecommunications, computing and consumer appliances, which are the most prolific users of PCBs, according to a new report from Global Industry Analysts, Inc. However, the market in recent years has been gaining significant opportunities in other industries such as automotive electronics, medical device electronics, defense and aerospace electronic equipment, and industrial equipment among others. With end-use markets for SMT equipment shifting focus from defect detection to defect prevention, SMT equipment manufacturers are turning towards diversification of product offerings. Growing demand for high-quality SMT equipment from contract and OEM manufacturers is poised to benefit the market. In addition, rising demand for light emitting diodes (LED) technology is fuelling demand for SMT equipment. Driven by growing popularity of LEDs, SMT equipment manufacturers are ramping up their production capacity to address demand from commercial and consumer electronics sectors.

Additionally, miniaturization of components is spurring the need for sophisticated SMT placement and inspection equipment. Eliminating rework, improving manufacturing processes, reducing associated costs, increasing yield and enhancing margins represent key benefits driving adoption of SMT inspection equipment. With modern day automobiles coming equipped with high-end entertainment, connectivity systems, and driver safety features, increased integration of power electronics is generating significant demand for SMT equipment in the automobile industry.

As stated by the new market research report on surface mount technology (SMT) equipment, Asia-Pacific represents the single largest market worldwide. With robust pace of industrialization, infrastructure development and GDP growth, the region offers bright growth prospects. Latin America, trailing a CAGR of 7.2% over the analysis period, is projected to emerge as the fastest growing market. While growth in the SMT equipment market in Europe continues to remain subdued amidst volatile economic conditions, long term prospects remain positive with EU gearing up to revive its position in the hardware and manufacturing industry and supporting innovative startups and electronics manufacturing clusters in the region.

SMT placement equipment represents the largest product segment within the SMT equipment market. Growth in the segment is attributed to the burgeoning momentum and thriving product innovation in the electronics market. Though product miniaturization is the most significant factor contributing to the resurgence and subsequent buoyancy in the SMT placement equipment segment, the need for higher accuracy placement equipment, improved speed and flexibility also play vital roles in driving growth. In the SMT Inspection Systems market, Automatic X-Ray Inspection (AXI) Equipment and Automatic Optical Inspection (AOI) Equipment are expected to gain traction over next few years. AXI equipment is expected to gain from the integration of computer tomography and intuitive programming. AOI equipment is projected to benefit from machine vision-based algorithms that feature easy programming capability, flexibility, and enhanced ability to detect faults and with few false call rates.

Major players in the market include ASM Assembly Systems GmbH & Co. KG, Assembléon Netherlands BV, Conceptronic, CyberOptics Corporation, Fuji Machine Manufacturing Co. Ltd., Heller Industries Inc., Juki Automation Systems Inc., Koh Young Technology Inc., Panasonic Corporation, Saki Corporation, and Universal Instruments among others.

The research report titled “Surface Mount Technology (SMT) Equipment: A Global Strategic Business Report” announced by Global Industry Analysts Inc., provides a comprehensive review of market trends, issues, product innovations/introduction, mergers, acquisitions and other strategic industry activities.